LLVMTargetMachine.cpp revision 07680ec7a1ea86e8280c924e84e0eb2455e2483c 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Passes.h"
17#include "llvm/Analysis/Verifier.h"
18#include "llvm/Assembly/PrintModulePass.h"
19#include "llvm/CodeGen/AsmPrinter.h"
20#include "llvm/CodeGen/MachineFunctionAnalysis.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/GCStrategy.h"
23#include "llvm/CodeGen/Passes.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Target/TargetOptions.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/Target/TargetData.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Target/TargetLowering.h"
33#include "llvm/Target/TargetLoweringObjectFile.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Target/TargetSubtargetInfo.h"
36#include "llvm/Transforms/Scalar.h"
37#include "llvm/ADT/OwningPtr.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/FormattedStream.h"
41#include "llvm/Support/TargetRegistry.h"
42using namespace llvm;
43
44static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
45    cl::desc("Disable Post Regalloc"));
46static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
47    cl::desc("Disable branch folding"));
48static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
49    cl::desc("Disable tail duplication"));
50static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
51    cl::desc("Disable pre-register allocation tail duplication"));
52static cl::opt<bool> EnableBlockPlacement("enable-block-placement",
53    cl::Hidden, cl::desc("Enable probability-driven block placement"));
54static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
55    cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
56static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
57    cl::desc("Disable code placement"));
58static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
59    cl::desc("Disable Stack Slot Coloring"));
60static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
61    cl::desc("Disable Machine Dead Code Elimination"));
62static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
63    cl::desc("Disable Machine LICM"));
64static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
65    cl::desc("Disable Machine Common Subexpression Elimination"));
66static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
67    cl::Hidden,
68    cl::desc("Disable Machine LICM"));
69static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70    cl::desc("Disable Machine Sinking"));
71static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72    cl::desc("Disable Loop Strength Reduction Pass"));
73static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
74    cl::desc("Disable Codegen Prepare"));
75static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
76    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
77static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
78    cl::desc("Print LLVM IR input to isel pass"));
79static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
80    cl::desc("Dump garbage collector data"));
81static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
82    cl::desc("Show encoding in .s output"));
83static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
84    cl::desc("Show instruction structure in .s output"));
85static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
86    cl::desc("Verify generated machine code"),
87    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
88
89static cl::opt<cl::boolOrDefault>
90AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
91           cl::init(cl::BOU_UNSET));
92
93static bool getVerboseAsm() {
94  switch (AsmVerbose) {
95  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
96  case cl::BOU_TRUE:  return true;
97  case cl::BOU_FALSE: return false;
98  }
99  llvm_unreachable("Invalid verbose asm state");
100}
101
102// Enable or disable FastISel. Both options are needed, because
103// FastISel is enabled by default with -fast, and we wish to be
104// able to enable or disable fast-isel independently from -O0.
105static cl::opt<cl::boolOrDefault>
106EnableFastISelOption("fast-isel", cl::Hidden,
107  cl::desc("Enable the \"fast\" instruction selector"));
108
109LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
110                                     StringRef CPU, StringRef FS,
111                                     TargetOptions Options,
112                                     Reloc::Model RM, CodeModel::Model CM,
113                                     CodeGenOpt::Level OL)
114  : TargetMachine(T, Triple, CPU, FS, Options) {
115  CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM, OL);
116  AsmInfo = T.createMCAsmInfo(Triple);
117  // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0,
118  // and if the old one gets included then MCAsmInfo will be NULL and
119  // we'll crash later.
120  // Provide the user with a useful error message about what's wrong.
121  assert(AsmInfo && "MCAsmInfo not initialized."
122         "Make sure you include the correct TargetSelect.h"
123         "and that InitializeAllTargetMCs() is being invoked!");
124}
125
126bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
127                                            formatted_raw_ostream &Out,
128                                            CodeGenFileType FileType,
129                                            bool DisableVerify) {
130  // Add common CodeGen passes.
131  MCContext *Context = 0;
132  if (addCommonCodeGenPasses(PM, DisableVerify, Context))
133    return true;
134  assert(Context != 0 && "Failed to get MCContext");
135
136  if (hasMCSaveTempLabels())
137    Context->setAllowTemporaryLabels(false);
138
139  const MCAsmInfo &MAI = *getMCAsmInfo();
140  const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
141  OwningPtr<MCStreamer> AsmStreamer;
142
143  switch (FileType) {
144  case CGFT_AssemblyFile: {
145    MCInstPrinter *InstPrinter =
146      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI);
147
148    // Create a code emitter if asked to show the encoding.
149    MCCodeEmitter *MCE = 0;
150    MCAsmBackend *MAB = 0;
151    if (ShowMCEncoding) {
152      const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
153      MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
154      MAB = getTarget().createMCAsmBackend(getTargetTriple());
155    }
156
157    MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
158                                                  getVerboseAsm(),
159                                                  hasMCUseLoc(),
160                                                  hasMCUseCFI(),
161                                                  hasMCUseDwarfDirectory(),
162                                                  InstPrinter,
163                                                  MCE, MAB,
164                                                  ShowMCInst);
165    AsmStreamer.reset(S);
166    break;
167  }
168  case CGFT_ObjectFile: {
169    // Create the code emitter for the target if it exists.  If not, .o file
170    // emission fails.
171    MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
172                                                         *Context);
173    MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
174    if (MCE == 0 || MAB == 0)
175      return true;
176
177    AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
178                                                         *Context, *MAB, Out,
179                                                         MCE, hasMCRelaxAll(),
180                                                         hasMCNoExecStack()));
181    AsmStreamer.get()->InitSections();
182    break;
183  }
184  case CGFT_Null:
185    // The Null output is intended for use for performance analysis and testing,
186    // not real users.
187    AsmStreamer.reset(createNullStreamer(*Context));
188    break;
189  }
190
191  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
192  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
193  if (Printer == 0)
194    return true;
195
196  // If successful, createAsmPrinter took ownership of AsmStreamer.
197  AsmStreamer.take();
198
199  PM.add(Printer);
200
201  PM.add(createGCInfoDeleter());
202  return false;
203}
204
205/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
206/// get machine code emitted.  This uses a JITCodeEmitter object to handle
207/// actually outputting the machine code and resolving things like the address
208/// of functions.  This method should returns true if machine code emission is
209/// not supported.
210///
211bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
212                                                   JITCodeEmitter &JCE,
213                                                   bool DisableVerify) {
214  // Add common CodeGen passes.
215  MCContext *Ctx = 0;
216  if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
217    return true;
218
219  addCodeEmitter(PM, JCE);
220  PM.add(createGCInfoDeleter());
221
222  return false; // success!
223}
224
225/// addPassesToEmitMC - Add passes to the specified pass manager to get
226/// machine code emitted with the MCJIT. This method returns true if machine
227/// code is not supported. It fills the MCContext Ctx pointer which can be
228/// used to build custom MCStreamer.
229///
230bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
231                                          MCContext *&Ctx,
232                                          raw_ostream &Out,
233                                          bool DisableVerify) {
234  // Add common CodeGen passes.
235  if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
236    return true;
237
238  if (hasMCSaveTempLabels())
239    Ctx->setAllowTemporaryLabels(false);
240
241  // Create the code emitter for the target if it exists.  If not, .o file
242  // emission fails.
243  const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
244  MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
245  MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
246  if (MCE == 0 || MAB == 0)
247    return true;
248
249  OwningPtr<MCStreamer> AsmStreamer;
250  AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
251                                                       *MAB, Out, MCE,
252                                                       hasMCRelaxAll(),
253                                                       hasMCNoExecStack()));
254  AsmStreamer.get()->InitSections();
255
256  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
257  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
258  if (Printer == 0)
259    return true;
260
261  // If successful, createAsmPrinter took ownership of AsmStreamer.
262  AsmStreamer.take();
263
264  PM.add(Printer);
265
266  return false; // success!
267}
268
269void LLVMTargetMachine::printNoVerify(PassManagerBase &PM,
270                                      const char *Banner) const {
271  if (Options.PrintMachineCode)
272    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
273}
274
275void LLVMTargetMachine::printAndVerify(PassManagerBase &PM,
276                                       const char *Banner) const {
277  if (Options.PrintMachineCode)
278    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
279
280  if (VerifyMachineCode)
281    PM.add(createMachineVerifierPass(Banner));
282}
283
284/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
285/// emitting to assembly files or machine code output.
286///
287bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
288                                               bool DisableVerify,
289                                               MCContext *&OutContext) {
290  // Standard LLVM-Level Passes.
291
292  // Basic AliasAnalysis support.
293  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
294  // BasicAliasAnalysis wins if they disagree. This is intended to help
295  // support "obvious" type-punning idioms.
296  PM.add(createTypeBasedAliasAnalysisPass());
297  PM.add(createBasicAliasAnalysisPass());
298
299  // Before running any passes, run the verifier to determine if the input
300  // coming from the front-end and/or optimizer is valid.
301  if (!DisableVerify)
302    PM.add(createVerifierPass());
303
304  // Run loop strength reduction before anything else.
305  if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
306    PM.add(createLoopStrengthReducePass(getTargetLowering()));
307    if (PrintLSR)
308      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
309  }
310
311  PM.add(createGCLoweringPass());
312
313  // Make sure that no unreachable blocks are instruction selected.
314  PM.add(createUnreachableBlockEliminationPass());
315
316  // Turn exception handling constructs into something the code generators can
317  // handle.
318  switch (getMCAsmInfo()->getExceptionHandlingType()) {
319  case ExceptionHandling::SjLj:
320    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
321    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
322    // catch info can get misplaced when a selector ends up more than one block
323    // removed from the parent invoke(s). This could happen when a landing
324    // pad is shared by multiple invokes and is also a target of a normal
325    // edge from elsewhere.
326    PM.add(createSjLjEHPass(getTargetLowering()));
327    // FALLTHROUGH
328  case ExceptionHandling::DwarfCFI:
329  case ExceptionHandling::ARM:
330  case ExceptionHandling::Win64:
331    PM.add(createDwarfEHPass(this));
332    break;
333  case ExceptionHandling::None:
334    PM.add(createLowerInvokePass(getTargetLowering()));
335
336    // The lower invoke pass may create unreachable code. Remove it.
337    PM.add(createUnreachableBlockEliminationPass());
338    break;
339  }
340
341  if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
342    PM.add(createCodeGenPreparePass(getTargetLowering()));
343
344  PM.add(createStackProtectorPass(getTargetLowering()));
345
346  addPreISel(PM);
347
348  if (PrintISelInput)
349    PM.add(createPrintFunctionPass("\n\n"
350                                   "*** Final LLVM Code input to ISel ***\n",
351                                   &dbgs()));
352
353  // All passes which modify the LLVM IR are now complete; run the verifier
354  // to ensure that the IR is valid.
355  if (!DisableVerify)
356    PM.add(createVerifierPass());
357
358  // Standard Lower-Level Passes.
359
360  // Install a MachineModuleInfo class, which is an immutable pass that holds
361  // all the per-module stuff we're generating, including MCContext.
362  MachineModuleInfo *MMI =
363    new MachineModuleInfo(*getMCAsmInfo(), *getRegisterInfo(),
364                          &getTargetLowering()->getObjFileLowering());
365  PM.add(MMI);
366  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
367
368  // Set up a MachineFunction for the rest of CodeGen to work on.
369  PM.add(new MachineFunctionAnalysis(*this));
370
371  // Enable FastISel with -fast, but allow that to be overridden.
372  if (EnableFastISelOption == cl::BOU_TRUE ||
373      (getOptLevel() == CodeGenOpt::None &&
374       EnableFastISelOption != cl::BOU_FALSE))
375    Options.EnableFastISel = true;
376
377  // Ask the target for an isel.
378  if (addInstSelector(PM))
379    return true;
380
381  // Print the instruction selected machine code...
382  printAndVerify(PM, "After Instruction Selection");
383
384  // Expand pseudo-instructions emitted by ISel.
385  PM.add(createExpandISelPseudosPass());
386
387  // Pre-ra tail duplication.
388  if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
389    PM.add(createTailDuplicatePass(true));
390    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
391  }
392
393  // Optimize PHIs before DCE: removing dead PHI cycles may make more
394  // instructions dead.
395  if (getOptLevel() != CodeGenOpt::None)
396    PM.add(createOptimizePHIsPass());
397
398  // If the target requests it, assign local variables to stack slots relative
399  // to one another and simplify frame index references where possible.
400  PM.add(createLocalStackSlotAllocationPass());
401
402  if (getOptLevel() != CodeGenOpt::None) {
403    // With optimization, dead code should already be eliminated. However
404    // there is one known exception: lowered code for arguments that are only
405    // used by tail calls, where the tail calls reuse the incoming stack
406    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
407    if (!DisableMachineDCE)
408      PM.add(createDeadMachineInstructionElimPass());
409    printAndVerify(PM, "After codegen DCE pass");
410
411    if (!DisableMachineLICM)
412      PM.add(createMachineLICMPass());
413    if (!DisableMachineCSE)
414      PM.add(createMachineCSEPass());
415    if (!DisableMachineSink)
416      PM.add(createMachineSinkingPass());
417    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
418
419    PM.add(createPeepholeOptimizerPass());
420    printAndVerify(PM, "After codegen peephole optimization pass");
421  }
422
423  // Run pre-ra passes.
424  if (addPreRegAlloc(PM))
425    printAndVerify(PM, "After PreRegAlloc passes");
426
427  // Perform register allocation.
428  PM.add(createRegisterAllocator(getOptLevel()));
429  printAndVerify(PM, "After Register Allocation");
430
431  // Perform stack slot coloring and post-ra machine LICM.
432  if (getOptLevel() != CodeGenOpt::None) {
433    // FIXME: Re-enable coloring with register when it's capable of adding
434    // kill markers.
435    if (!DisableSSC)
436      PM.add(createStackSlotColoringPass(false));
437
438    // Run post-ra machine LICM to hoist reloads / remats.
439    if (!DisablePostRAMachineLICM)
440      PM.add(createMachineLICMPass(false));
441
442    printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
443  }
444
445  // Run post-ra passes.
446  if (addPostRegAlloc(PM))
447    printAndVerify(PM, "After PostRegAlloc passes");
448
449  // Insert prolog/epilog code.  Eliminate abstract frame index references...
450  PM.add(createPrologEpilogCodeInserter());
451  printAndVerify(PM, "After PrologEpilogCodeInserter");
452
453  // Branch folding must be run after regalloc and prolog/epilog insertion.
454  if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
455    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
456    printNoVerify(PM, "After BranchFolding");
457  }
458
459  // Tail duplication.
460  if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
461    PM.add(createTailDuplicatePass(false));
462    printNoVerify(PM, "After TailDuplicate");
463  }
464
465  // Copy propagation.
466  if (getOptLevel() != CodeGenOpt::None) {
467    PM.add(createMachineCopyPropagationPass());
468    printNoVerify(PM, "After copy propagation pass");
469  }
470
471  // Expand pseudo instructions before second scheduling pass.
472  PM.add(createExpandPostRAPseudosPass());
473  printNoVerify(PM, "After ExpandPostRAPseudos");
474
475  // Run pre-sched2 passes.
476  if (addPreSched2(PM))
477    printNoVerify(PM, "After PreSched2 passes");
478
479  // Second pass scheduler.
480  if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
481    PM.add(createPostRAScheduler(getOptLevel()));
482    printNoVerify(PM, "After PostRAScheduler");
483  }
484
485  PM.add(createGCMachineCodeAnalysisPass());
486
487  if (PrintGCInfo)
488    PM.add(createGCInfoPrinter(dbgs()));
489
490  if (getOptLevel() != CodeGenOpt::None && !DisableCodePlace) {
491    if (EnableBlockPlacement) {
492      // MachineBlockPlacement is an experimental pass which is disabled by
493      // default currently. Eventually it should subsume CodePlacementOpt, so
494      // when enabled, the other is disabled.
495      PM.add(createMachineBlockPlacementPass());
496      printNoVerify(PM, "After MachineBlockPlacement");
497    } else {
498      PM.add(createCodePlacementOptPass());
499      printNoVerify(PM, "After CodePlacementOpt");
500    }
501
502    // Run a separate pass to collect block placement statistics.
503    if (EnableBlockPlacementStats) {
504      PM.add(createMachineBlockPlacementStatsPass());
505      printNoVerify(PM, "After MachineBlockPlacementStats");
506    }
507  }
508
509  if (addPreEmitPass(PM))
510    printNoVerify(PM, "After PreEmit passes");
511
512  return false;
513}
514