LLVMTargetMachine.cpp revision 16e77059ad4eecf63f114e4aa2c808fad3ffb40d 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Verifier.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/MachineFunctionAnalysis.h"
20#include "llvm/CodeGen/MachineModuleInfo.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/Target/TargetData.h"
27#include "llvm/Target/TargetRegistry.h"
28#include "llvm/Transforms/Scalar.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/FormattedStream.h"
33using namespace llvm;
34
35namespace llvm {
36  bool EnableFastISel;
37}
38
39static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40    cl::desc("Disable Post Regalloc"));
41static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42    cl::desc("Disable branch folding"));
43static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44    cl::desc("Disable tail duplication"));
45static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46    cl::desc("Disable pre-register allocation tail duplication"));
47static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48    cl::desc("Disable code placement"));
49static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50    cl::desc("Disable Stack Slot Coloring"));
51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52    cl::desc("Disable Machine LICM"));
53static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
54    cl::desc("Disable Machine Sinking"));
55static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
56    cl::desc("Disable Loop Strength Reduction Pass"));
57static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
58    cl::desc("Disable Codegen Prepare"));
59static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
60    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
61static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
62    cl::desc("Print LLVM IR input to isel pass"));
63static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
64    cl::desc("Dump garbage collector data"));
65static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
66    cl::desc("Verify generated machine code"),
67    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
68
69static cl::opt<cl::boolOrDefault>
70AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
71           cl::init(cl::BOU_UNSET));
72
73static bool getVerboseAsm() {
74  switch (AsmVerbose) {
75  default:
76  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
77  case cl::BOU_TRUE:  return true;
78  case cl::BOU_FALSE: return false;
79  }
80}
81
82// Enable or disable FastISel. Both options are needed, because
83// FastISel is enabled by default with -fast, and we wish to be
84// able to enable or disable fast-isel independently from -O0.
85static cl::opt<cl::boolOrDefault>
86EnableFastISelOption("fast-isel", cl::Hidden,
87  cl::desc("Enable the \"fast\" instruction selector"));
88
89// Enable or disable an experimental optimization to split GEPs
90// and run a special GVN pass which does not examine loads, in
91// an effort to factor out redundancy implicit in complex GEPs.
92static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
93    cl::desc("Split GEPs and run no-load GVN"));
94
95LLVMTargetMachine::LLVMTargetMachine(const Target &T,
96                                     const std::string &Triple)
97  : TargetMachine(T), TargetTriple(Triple) {
98  AsmInfo = T.createAsmInfo(TargetTriple);
99}
100
101// Set the default code model for the JIT for a generic target.
102// FIXME: Is small right here? or .is64Bit() ? Large : Small?
103void LLVMTargetMachine::setCodeModelForJIT() {
104  setCodeModel(CodeModel::Small);
105}
106
107// Set the default code model for static compilation for a generic target.
108void LLVMTargetMachine::setCodeModelForStatic() {
109  setCodeModel(CodeModel::Small);
110}
111
112bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
113                                            formatted_raw_ostream &Out,
114                                            CodeGenFileType FileType,
115                                            CodeGenOpt::Level OptLevel,
116                                            bool DisableVerify) {
117  // Add common CodeGen passes.
118  MCContext *Context = 0;
119  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
120    return true;
121  assert(Context != 0 && "Failed to get MCContext");
122
123  const MCAsmInfo &MAI = *getMCAsmInfo();
124  OwningPtr<MCStreamer> AsmStreamer;
125
126  switch (FileType) {
127  default: return true;
128  case CGFT_AssemblyFile: {
129    MCInstPrinter *InstPrinter =
130      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
131    AsmStreamer.reset(createAsmStreamer(*Context, Out,
132                                        getTargetData()->isLittleEndian(),
133                                        getVerboseAsm(), InstPrinter,
134                                        /*codeemitter*/0));
135    break;
136  }
137  case CGFT_ObjectFile: {
138    // Create the code emitter for the target if it exists.  If not, .o file
139    // emission fails.
140    MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
141    TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
142    if (MCE == 0 || TAB == 0)
143      return true;
144
145    AsmStreamer.reset(createMachOStreamer(*Context, *TAB, Out, MCE));
146    break;
147  }
148  case CGFT_Null:
149    // The Null output is intended for use for performance analysis and testing,
150    // not real users.
151    AsmStreamer.reset(createNullStreamer(*Context));
152    break;
153  }
154
155  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
156  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
157  if (Printer == 0)
158    return true;
159
160  // If successful, createAsmPrinter took ownership of AsmStreamer.
161  AsmStreamer.take();
162
163  PM.add(Printer);
164
165  // Make sure the code model is set.
166  setCodeModelForStatic();
167  PM.add(createGCInfoDeleter());
168  return false;
169}
170
171/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
172/// get machine code emitted.  This uses a JITCodeEmitter object to handle
173/// actually outputting the machine code and resolving things like the address
174/// of functions.  This method should returns true if machine code emission is
175/// not supported.
176///
177bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
178                                                   JITCodeEmitter &JCE,
179                                                   CodeGenOpt::Level OptLevel,
180                                                   bool DisableVerify) {
181  // Make sure the code model is set.
182  setCodeModelForJIT();
183
184  // Add common CodeGen passes.
185  MCContext *Ctx = 0;
186  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
187    return true;
188
189  addCodeEmitter(PM, OptLevel, JCE);
190  PM.add(createGCInfoDeleter());
191
192  return false; // success!
193}
194
195static void printNoVerify(PassManagerBase &PM, const char *Banner) {
196  if (PrintMachineCode)
197    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
198}
199
200static void printAndVerify(PassManagerBase &PM,
201                           const char *Banner,
202                           bool allowDoubleDefs = false) {
203  if (PrintMachineCode)
204    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
205
206  if (VerifyMachineCode)
207    PM.add(createMachineVerifierPass(allowDoubleDefs));
208}
209
210/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
211/// emitting to assembly files or machine code output.
212///
213bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
214                                               CodeGenOpt::Level OptLevel,
215                                               bool DisableVerify,
216                                               MCContext *&OutContext) {
217  // Standard LLVM-Level Passes.
218
219  // Before running any passes, run the verifier to determine if the input
220  // coming from the front-end and/or optimizer is valid.
221  if (!DisableVerify)
222    PM.add(createVerifierPass());
223
224  // Optionally, tun split-GEPs and no-load GVN.
225  if (EnableSplitGEPGVN) {
226    PM.add(createGEPSplitterPass());
227    PM.add(createGVNPass(/*NoLoads=*/true));
228  }
229
230  // Run loop strength reduction before anything else.
231  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
232    PM.add(createLoopStrengthReducePass(getTargetLowering()));
233    if (PrintLSR)
234      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
235  }
236
237  // Turn exception handling constructs into something the code generators can
238  // handle.
239  switch (getMCAsmInfo()->getExceptionHandlingType()) {
240  case ExceptionHandling::SjLj:
241    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
242    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
243    // catch info can get misplaced when a selector ends up more than one block
244    // removed from the parent invoke(s). This could happen when a landing
245    // pad is shared by multiple invokes and is also a target of a normal
246    // edge from elsewhere.
247    PM.add(createSjLjEHPass(getTargetLowering()));
248    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
249    break;
250  case ExceptionHandling::Dwarf:
251    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
252    break;
253  case ExceptionHandling::None:
254    PM.add(createLowerInvokePass(getTargetLowering()));
255    break;
256  }
257
258  PM.add(createGCLoweringPass());
259
260  // Make sure that no unreachable blocks are instruction selected.
261  PM.add(createUnreachableBlockEliminationPass());
262
263  if (OptLevel != CodeGenOpt::None && !DisableCGP)
264    PM.add(createCodeGenPreparePass(getTargetLowering()));
265
266  PM.add(createStackProtectorPass(getTargetLowering()));
267
268  if (PrintISelInput)
269    PM.add(createPrintFunctionPass("\n\n"
270                                   "*** Final LLVM Code input to ISel ***\n",
271                                   &dbgs()));
272
273  // All passes which modify the LLVM IR are now complete; run the verifier
274  // to ensure that the IR is valid.
275  if (!DisableVerify)
276    PM.add(createVerifierPass());
277
278  // Standard Lower-Level Passes.
279
280  // Install a MachineModuleInfo class, which is an immutable pass that holds
281  // all the per-module stuff we're generating, including MCContext.
282  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo());
283  PM.add(MMI);
284  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
285
286
287  // Set up a MachineFunction for the rest of CodeGen to work on.
288  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
289
290  // Enable FastISel with -fast, but allow that to be overridden.
291  if (EnableFastISelOption == cl::BOU_TRUE ||
292      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
293    EnableFastISel = true;
294
295  // Ask the target for an isel.
296  if (addInstSelector(PM, OptLevel))
297    return true;
298
299  // Print the instruction selected machine code...
300  printAndVerify(PM, "After Instruction Selection",
301                 /* allowDoubleDefs= */ true);
302
303  // Optimize PHIs before DCE: removing dead PHI cycles may make more
304  // instructions dead.
305  if (OptLevel != CodeGenOpt::None)
306    PM.add(createOptimizePHIsPass());
307
308  // Delete dead machine instructions regardless of optimization level.
309  PM.add(createDeadMachineInstructionElimPass());
310  printAndVerify(PM, "After codegen DCE pass",
311                 /* allowDoubleDefs= */ true);
312
313  if (OptLevel != CodeGenOpt::None) {
314    PM.add(createOptimizeExtsPass());
315    if (!DisableMachineLICM)
316      PM.add(createMachineLICMPass());
317    PM.add(createMachineCSEPass());
318    if (!DisableMachineSink)
319      PM.add(createMachineSinkingPass());
320    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes",
321                   /* allowDoubleDefs= */ true);
322  }
323
324  // Pre-ra tail duplication.
325  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
326    PM.add(createTailDuplicatePass(true));
327    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
328                   /* allowDoubleDefs= */ true);
329  }
330
331  // Run pre-ra passes.
332  if (addPreRegAlloc(PM, OptLevel))
333    printAndVerify(PM, "After PreRegAlloc passes",
334                   /* allowDoubleDefs= */ true);
335
336  // Perform register allocation.
337  PM.add(createRegisterAllocator());
338  printAndVerify(PM, "After Register Allocation");
339
340  // Perform stack slot coloring.
341  if (OptLevel != CodeGenOpt::None && !DisableSSC) {
342    // FIXME: Re-enable coloring with register when it's capable of adding
343    // kill markers.
344    PM.add(createStackSlotColoringPass(false));
345    printAndVerify(PM, "After StackSlotColoring");
346
347    // Run post-ra machine LICM to hoist reloads / remats.
348    PM.add(createMachineLICMPass(false));
349  }
350
351  // Run post-ra passes.
352  if (addPostRegAlloc(PM, OptLevel))
353    printAndVerify(PM, "After PostRegAlloc passes");
354
355  PM.add(createLowerSubregsPass());
356  printAndVerify(PM, "After LowerSubregs");
357
358  // Insert prolog/epilog code.  Eliminate abstract frame index references...
359  PM.add(createPrologEpilogCodeInserter());
360  printAndVerify(PM, "After PrologEpilogCodeInserter");
361
362  // Run pre-sched2 passes.
363  if (addPreSched2(PM, OptLevel))
364    printAndVerify(PM, "After PreSched2 passes");
365
366  // Second pass scheduler.
367  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
368    PM.add(createPostRAScheduler(OptLevel));
369    printAndVerify(PM, "After PostRAScheduler");
370  }
371
372  // Branch folding must be run after regalloc and prolog/epilog insertion.
373  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
374    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
375    printNoVerify(PM, "After BranchFolding");
376  }
377
378  // Tail duplication.
379  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
380    PM.add(createTailDuplicatePass(false));
381    printNoVerify(PM, "After TailDuplicate");
382  }
383
384  PM.add(createGCMachineCodeAnalysisPass());
385
386  if (PrintGCInfo)
387    PM.add(createGCInfoPrinter(dbgs()));
388
389  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
390    PM.add(createCodePlacementOptPass());
391    printNoVerify(PM, "After CodePlacementOpt");
392  }
393
394  if (addPreEmitPass(PM, OptLevel))
395    printNoVerify(PM, "After PreEmit passes");
396
397  return false;
398}
399