LLVMTargetMachine.cpp revision 31649e61bcead26a63c7cd452da90fff5e000b91 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Verifier.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/MachineFunctionAnalysis.h"
20#include "llvm/CodeGen/MachineModuleInfo.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Target/TargetLowering.h"
24#include "llvm/Target/TargetOptions.h"
25#include "llvm/MC/MCAsmInfo.h"
26#include "llvm/MC/MCStreamer.h"
27#include "llvm/Target/TargetAsmInfo.h"
28#include "llvm/Target/TargetData.h"
29#include "llvm/Target/TargetRegistry.h"
30#include "llvm/Transforms/Scalar.h"
31#include "llvm/ADT/OwningPtr.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Debug.h"
34#include "llvm/Support/FormattedStream.h"
35#include "llvm/Support/StandardPasses.h"
36using namespace llvm;
37
38namespace llvm {
39  bool EnableFastISel;
40}
41
42static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
43    cl::desc("Disable Post Regalloc"));
44static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
45    cl::desc("Disable branch folding"));
46static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
47    cl::desc("Disable tail duplication"));
48static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
49    cl::desc("Disable pre-register allocation tail duplication"));
50static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
51    cl::desc("Disable code placement"));
52static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
53    cl::desc("Disable Stack Slot Coloring"));
54static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
55    cl::desc("Disable Machine LICM"));
56static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
57    cl::Hidden,
58    cl::desc("Disable Machine LICM"));
59static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
60    cl::desc("Disable Machine Sinking"));
61static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
62    cl::desc("Disable Loop Strength Reduction Pass"));
63static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
64    cl::desc("Disable Codegen Prepare"));
65static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
66    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
67static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
68    cl::desc("Print LLVM IR input to isel pass"));
69static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
70    cl::desc("Dump garbage collector data"));
71static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
72    cl::desc("Show encoding in .s output"));
73static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
74    cl::desc("Show instruction structure in .s output"));
75static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
76    cl::desc("Enable MC API logging"));
77static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
78    cl::desc("Verify generated machine code"),
79    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
80
81static cl::opt<cl::boolOrDefault>
82AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
83           cl::init(cl::BOU_UNSET));
84
85static bool getVerboseAsm() {
86  switch (AsmVerbose) {
87  default:
88  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
89  case cl::BOU_TRUE:  return true;
90  case cl::BOU_FALSE: return false;
91  }
92}
93
94// Enable or disable FastISel. Both options are needed, because
95// FastISel is enabled by default with -fast, and we wish to be
96// able to enable or disable fast-isel independently from -O0.
97static cl::opt<cl::boolOrDefault>
98EnableFastISelOption("fast-isel", cl::Hidden,
99  cl::desc("Enable the \"fast\" instruction selector"));
100
101LLVMTargetMachine::LLVMTargetMachine(const Target &T,
102                                     const std::string &Triple)
103  : TargetMachine(T), TargetTriple(Triple) {
104  AsmInfo = T.createAsmInfo(TargetTriple);
105}
106
107// Set the default code model for the JIT for a generic target.
108// FIXME: Is small right here? or .is64Bit() ? Large : Small?
109void LLVMTargetMachine::setCodeModelForJIT() {
110  setCodeModel(CodeModel::Small);
111}
112
113// Set the default code model for static compilation for a generic target.
114void LLVMTargetMachine::setCodeModelForStatic() {
115  setCodeModel(CodeModel::Small);
116}
117
118bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
119                                            formatted_raw_ostream &Out,
120                                            CodeGenFileType FileType,
121                                            CodeGenOpt::Level OptLevel,
122                                            bool DisableVerify) {
123  // Add common CodeGen passes.
124  MCContext *Context = 0;
125  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
126    return true;
127  assert(Context != 0 && "Failed to get MCContext");
128
129  const MCAsmInfo &MAI = *getMCAsmInfo();
130  OwningPtr<MCStreamer> AsmStreamer;
131
132  switch (FileType) {
133  default: return true;
134  case CGFT_AssemblyFile: {
135    MCInstPrinter *InstPrinter =
136      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
137
138    // Create a code emitter if asked to show the encoding.
139    MCCodeEmitter *MCE = 0;
140    TargetAsmBackend *TAB = 0;
141    if (ShowMCEncoding) {
142      MCE = getTarget().createCodeEmitter(*this, *Context);
143      TAB = getTarget().createAsmBackend(TargetTriple);
144    }
145
146    MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
147                                                  getVerboseAsm(),
148                                                  hasMCUseLoc(),
149                                                  InstPrinter,
150                                                  MCE, TAB,
151                                                  ShowMCInst);
152    AsmStreamer.reset(S);
153    break;
154  }
155  case CGFT_ObjectFile: {
156    // Create the code emitter for the target if it exists.  If not, .o file
157    // emission fails.
158    MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
159    TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
160    if (MCE == 0 || TAB == 0)
161      return true;
162
163    AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
164                                                       *TAB, Out, MCE,
165                                                       hasMCRelaxAll(),
166                                                       hasMCNoExecStack()));
167    AsmStreamer.get()->InitSections();
168    break;
169  }
170  case CGFT_Null:
171    // The Null output is intended for use for performance analysis and testing,
172    // not real users.
173    AsmStreamer.reset(createNullStreamer(*Context));
174    break;
175  }
176
177  if (EnableMCLogging)
178    AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
179
180  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
181  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
182  if (Printer == 0)
183    return true;
184
185  // If successful, createAsmPrinter took ownership of AsmStreamer.
186  AsmStreamer.take();
187
188  PM.add(Printer);
189
190  // Make sure the code model is set.
191  setCodeModelForStatic();
192  PM.add(createGCInfoDeleter());
193  return false;
194}
195
196/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
197/// get machine code emitted.  This uses a JITCodeEmitter object to handle
198/// actually outputting the machine code and resolving things like the address
199/// of functions.  This method should returns true if machine code emission is
200/// not supported.
201///
202bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
203                                                   JITCodeEmitter &JCE,
204                                                   CodeGenOpt::Level OptLevel,
205                                                   bool DisableVerify) {
206  // Make sure the code model is set.
207  setCodeModelForJIT();
208
209  // Add common CodeGen passes.
210  MCContext *Ctx = 0;
211  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
212    return true;
213
214  addCodeEmitter(PM, OptLevel, JCE);
215  PM.add(createGCInfoDeleter());
216
217  return false; // success!
218}
219
220/// addPassesToEmitMC - Add passes to the specified pass manager to get
221/// machine code emitted with the MCJIT. This method returns true if machine
222/// code is not supported. It fills the MCContext Ctx pointer which can be
223/// used to build custom MCStreamer.
224///
225bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
226                                          MCContext *&Ctx,
227                                          raw_ostream &Out,
228                                          CodeGenOpt::Level OptLevel,
229                                          bool DisableVerify) {
230  // Add common CodeGen passes.
231  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
232    return true;
233
234  // Create the code emitter for the target if it exists.  If not, .o file
235  // emission fails.
236  MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Ctx);
237  TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
238  if (MCE == 0 || TAB == 0)
239    return true;
240
241  OwningPtr<MCStreamer> AsmStreamer;
242  AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Ctx,
243                                                     *TAB, Out, MCE,
244                                                     hasMCRelaxAll(),
245                                                     hasMCNoExecStack()));
246  AsmStreamer.get()->InitSections();
247
248  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
249  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
250  if (Printer == 0)
251    return true;
252
253  // If successful, createAsmPrinter took ownership of AsmStreamer.
254  AsmStreamer.take();
255
256  PM.add(Printer);
257
258  // Make sure the code model is set.
259  setCodeModelForJIT();
260
261  return false; // success!
262}
263
264static void printNoVerify(PassManagerBase &PM, const char *Banner) {
265  if (PrintMachineCode)
266    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
267}
268
269static void printAndVerify(PassManagerBase &PM,
270                           const char *Banner) {
271  if (PrintMachineCode)
272    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
273
274  if (VerifyMachineCode)
275    PM.add(createMachineVerifierPass(Banner));
276}
277
278/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
279/// emitting to assembly files or machine code output.
280///
281bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
282                                               CodeGenOpt::Level OptLevel,
283                                               bool DisableVerify,
284                                               MCContext *&OutContext) {
285  // Standard LLVM-Level Passes.
286
287  // Basic AliasAnalysis support.
288  createStandardAliasAnalysisPasses(&PM);
289
290  // Before running any passes, run the verifier to determine if the input
291  // coming from the front-end and/or optimizer is valid.
292  if (!DisableVerify)
293    PM.add(createVerifierPass());
294
295  // Run loop strength reduction before anything else.
296  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
297    PM.add(createLoopStrengthReducePass(getTargetLowering()));
298    if (PrintLSR)
299      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
300  }
301
302  PM.add(createGCLoweringPass());
303
304  // Make sure that no unreachable blocks are instruction selected.
305  PM.add(createUnreachableBlockEliminationPass());
306
307  // Turn exception handling constructs into something the code generators can
308  // handle.
309  switch (getMCAsmInfo()->getExceptionHandlingType()) {
310  case ExceptionHandling::SjLj:
311    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
312    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
313    // catch info can get misplaced when a selector ends up more than one block
314    // removed from the parent invoke(s). This could happen when a landing
315    // pad is shared by multiple invokes and is also a target of a normal
316    // edge from elsewhere.
317    PM.add(createSjLjEHPass(getTargetLowering()));
318    // FALLTHROUGH
319  case ExceptionHandling::DwarfCFI:
320  case ExceptionHandling::DwarfTable:
321  case ExceptionHandling::ARM:
322    PM.add(createDwarfEHPass(this));
323    break;
324  case ExceptionHandling::None:
325    PM.add(createLowerInvokePass(getTargetLowering()));
326
327    // The lower invoke pass may create unreachable code. Remove it.
328    PM.add(createUnreachableBlockEliminationPass());
329    break;
330  }
331
332  if (OptLevel != CodeGenOpt::None && !DisableCGP)
333    PM.add(createCodeGenPreparePass(getTargetLowering()));
334
335  PM.add(createStackProtectorPass(getTargetLowering()));
336
337  addPreISel(PM, OptLevel);
338
339  if (PrintISelInput)
340    PM.add(createPrintFunctionPass("\n\n"
341                                   "*** Final LLVM Code input to ISel ***\n",
342                                   &dbgs()));
343
344  // All passes which modify the LLVM IR are now complete; run the verifier
345  // to ensure that the IR is valid.
346  if (!DisableVerify)
347    PM.add(createVerifierPass());
348
349  // Standard Lower-Level Passes.
350
351  // Install a MachineModuleInfo class, which is an immutable pass that holds
352  // all the per-module stuff we're generating, including MCContext.
353  TargetAsmInfo *TAI = new TargetAsmInfo(*this);
354  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), TAI);
355  PM.add(MMI);
356  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
357
358  // Set up a MachineFunction for the rest of CodeGen to work on.
359  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
360
361  // Enable FastISel with -fast, but allow that to be overridden.
362  if (EnableFastISelOption == cl::BOU_TRUE ||
363      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
364    EnableFastISel = true;
365
366  // Ask the target for an isel.
367  if (addInstSelector(PM, OptLevel))
368    return true;
369
370  // Print the instruction selected machine code...
371  printAndVerify(PM, "After Instruction Selection");
372
373  // Expand pseudo-instructions emitted by ISel.
374  PM.add(createExpandISelPseudosPass());
375
376  // Optimize PHIs before DCE: removing dead PHI cycles may make more
377  // instructions dead.
378  if (OptLevel != CodeGenOpt::None)
379    PM.add(createOptimizePHIsPass());
380
381  // If the target requests it, assign local variables to stack slots relative
382  // to one another and simplify frame index references where possible.
383  PM.add(createLocalStackSlotAllocationPass());
384
385  if (OptLevel != CodeGenOpt::None) {
386    // With optimization, dead code should already be eliminated. However
387    // there is one known exception: lowered code for arguments that are only
388    // used by tail calls, where the tail calls reuse the incoming stack
389    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
390    PM.add(createDeadMachineInstructionElimPass());
391    printAndVerify(PM, "After codegen DCE pass");
392
393    if (!DisableMachineLICM)
394      PM.add(createMachineLICMPass());
395    PM.add(createMachineCSEPass());
396    if (!DisableMachineSink)
397      PM.add(createMachineSinkingPass());
398    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
399
400    PM.add(createPeepholeOptimizerPass());
401    printAndVerify(PM, "After codegen peephole optimization pass");
402  }
403
404  // Pre-ra tail duplication.
405  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
406    PM.add(createTailDuplicatePass(true));
407    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
408  }
409
410  // Run pre-ra passes.
411  if (addPreRegAlloc(PM, OptLevel))
412    printAndVerify(PM, "After PreRegAlloc passes");
413
414  // Perform register allocation.
415  PM.add(createRegisterAllocator(OptLevel));
416  printAndVerify(PM, "After Register Allocation");
417
418  // Perform stack slot coloring and post-ra machine LICM.
419  if (OptLevel != CodeGenOpt::None) {
420    // FIXME: Re-enable coloring with register when it's capable of adding
421    // kill markers.
422    if (!DisableSSC)
423      PM.add(createStackSlotColoringPass(false));
424
425    // Run post-ra machine LICM to hoist reloads / remats.
426    if (!DisablePostRAMachineLICM)
427      PM.add(createMachineLICMPass(false));
428
429    printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
430  }
431
432  // Run post-ra passes.
433  if (addPostRegAlloc(PM, OptLevel))
434    printAndVerify(PM, "After PostRegAlloc passes");
435
436  PM.add(createLowerSubregsPass());
437  printAndVerify(PM, "After LowerSubregs");
438
439  // Insert prolog/epilog code.  Eliminate abstract frame index references...
440  PM.add(createPrologEpilogCodeInserter());
441  printAndVerify(PM, "After PrologEpilogCodeInserter");
442
443  // Run pre-sched2 passes.
444  if (addPreSched2(PM, OptLevel))
445    printAndVerify(PM, "After PreSched2 passes");
446
447  // Second pass scheduler.
448  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
449    PM.add(createPostRAScheduler(OptLevel));
450    printAndVerify(PM, "After PostRAScheduler");
451  }
452
453  // Branch folding must be run after regalloc and prolog/epilog insertion.
454  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
455    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
456    printNoVerify(PM, "After BranchFolding");
457  }
458
459  // Tail duplication.
460  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
461    PM.add(createTailDuplicatePass(false));
462    printNoVerify(PM, "After TailDuplicate");
463  }
464
465  PM.add(createGCMachineCodeAnalysisPass());
466
467  if (PrintGCInfo)
468    PM.add(createGCInfoPrinter(dbgs()));
469
470  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
471    PM.add(createCodePlacementOptPass());
472    printNoVerify(PM, "After CodePlacementOpt");
473  }
474
475  if (addPreEmitPass(PM, OptLevel))
476    printNoVerify(PM, "After PreEmit passes");
477
478  return false;
479}
480