LLVMTargetMachine.cpp revision 39bdc78e6fcc2a152c6143952c23fba5db983227 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/FileWriters.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/MachineFunctionAnalysis.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/Target/TargetRegistry.h"
26#include "llvm/Transforms/Scalar.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/FormattedStream.h"
30using namespace llvm;
31
32namespace llvm {
33  bool EnableFastISel;
34}
35
36static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
37    cl::desc("Disable Post Regalloc"));
38static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
39    cl::desc("Disable branch folding"));
40static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
41    cl::desc("Disable tail duplication"));
42static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
43    cl::desc("Disable pre-register allocation tail duplication"));
44static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
45    cl::desc("Disable code placement"));
46static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
47    cl::desc("Disable Stack Slot Coloring"));
48static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
49    cl::desc("Disable Machine LICM"));
50static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
51    cl::desc("Disable Machine Sinking"));
52static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
53    cl::desc("Disable Loop Strength Reduction Pass"));
54static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
55    cl::desc("Disable Codegen Prepare"));
56static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
57    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
58static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
59    cl::desc("Print LLVM IR input to isel pass"));
60static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
61    cl::desc("Dump emitter generated instructions as assembly"));
62static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
63    cl::desc("Dump garbage collector data"));
64static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
65    cl::desc("Verify generated machine code"),
66    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
67
68
69// Enable or disable FastISel. Both options are needed, because
70// FastISel is enabled by default with -fast, and we wish to be
71// able to enable or disable fast-isel independently from -O0.
72static cl::opt<cl::boolOrDefault>
73EnableFastISelOption("fast-isel", cl::Hidden,
74  cl::desc("Enable the \"fast\" instruction selector"));
75
76// Enable or disable an experimental optimization to split GEPs
77// and run a special GVN pass which does not examine loads, in
78// an effort to factor out redundancy implicit in complex GEPs.
79static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
80    cl::desc("Split GEPs and run no-load GVN"));
81
82LLVMTargetMachine::LLVMTargetMachine(const Target &T,
83                                     const std::string &TargetTriple)
84  : TargetMachine(T) {
85  AsmInfo = T.createAsmInfo(TargetTriple);
86}
87
88// Set the default code model for the JIT for a generic target.
89// FIXME: Is small right here? or .is64Bit() ? Large : Small?
90void
91LLVMTargetMachine::setCodeModelForJIT() {
92  setCodeModel(CodeModel::Small);
93}
94
95// Set the default code model for static compilation for a generic target.
96void
97LLVMTargetMachine::setCodeModelForStatic() {
98  setCodeModel(CodeModel::Small);
99}
100
101FileModel::Model
102LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
103                                       formatted_raw_ostream &Out,
104                                       CodeGenFileType FileType,
105                                       CodeGenOpt::Level OptLevel) {
106  // Add common CodeGen passes.
107  if (addCommonCodeGenPasses(PM, OptLevel))
108    return FileModel::Error;
109
110  switch (FileType) {
111  default:
112    break;
113  case TargetMachine::AssemblyFile:
114    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
115      return FileModel::Error;
116    return FileModel::AsmFile;
117  case TargetMachine::ObjectFile:
118    return FileModel::Error;
119  }
120  return FileModel::Error;
121}
122
123bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
124                                           CodeGenOpt::Level OptLevel,
125                                           bool Verbose,
126                                           formatted_raw_ostream &Out) {
127  FunctionPass *Printer =
128    getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
129  if (!Printer)
130    return true;
131
132  PM.add(Printer);
133  return false;
134}
135
136/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
137/// be split up (e.g., to add an object writer pass), this method can be used to
138/// finish up adding passes to emit the file, if necessary.
139bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
140                                                  MachineCodeEmitter *MCE,
141                                                  CodeGenOpt::Level OptLevel) {
142  // Make sure the code model is set.
143  setCodeModelForStatic();
144
145  if (MCE)
146    addSimpleCodeEmitter(PM, OptLevel, *MCE);
147  if (PrintEmittedAsm)
148    addAssemblyEmitter(PM, OptLevel, true, ferrs());
149
150  PM.add(createGCInfoDeleter());
151
152  return false; // success!
153}
154
155/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
156/// be split up (e.g., to add an object writer pass), this method can be used to
157/// finish up adding passes to emit the file, if necessary.
158bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
159                                                  JITCodeEmitter *JCE,
160                                                  CodeGenOpt::Level OptLevel) {
161  // Make sure the code model is set.
162  setCodeModelForJIT();
163
164  if (JCE)
165    addSimpleCodeEmitter(PM, OptLevel, *JCE);
166  if (PrintEmittedAsm)
167    addAssemblyEmitter(PM, OptLevel, true, ferrs());
168
169  PM.add(createGCInfoDeleter());
170
171  return false; // success!
172}
173
174/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
175/// be split up (e.g., to add an object writer pass), this method can be used to
176/// finish up adding passes to emit the file, if necessary.
177bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
178                                                  ObjectCodeEmitter *OCE,
179                                                  CodeGenOpt::Level OptLevel) {
180  // Make sure the code model is set.
181  setCodeModelForStatic();
182
183  if (PrintEmittedAsm)
184    addAssemblyEmitter(PM, OptLevel, true, ferrs());
185
186  PM.add(createGCInfoDeleter());
187
188  return false; // success!
189}
190
191/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
192/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
193/// actually outputting the machine code and resolving things like the address
194/// of functions.  This method should returns true if machine code emission is
195/// not supported.
196///
197bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
198                                                   MachineCodeEmitter &MCE,
199                                                   CodeGenOpt::Level OptLevel) {
200  // Make sure the code model is set.
201  setCodeModelForJIT();
202
203  // Add common CodeGen passes.
204  if (addCommonCodeGenPasses(PM, OptLevel))
205    return true;
206
207  addCodeEmitter(PM, OptLevel, MCE);
208  if (PrintEmittedAsm)
209    addAssemblyEmitter(PM, OptLevel, true, ferrs());
210
211  PM.add(createGCInfoDeleter());
212
213  return false; // success!
214}
215
216/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
217/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
218/// actually outputting the machine code and resolving things like the address
219/// of functions.  This method should returns true if machine code emission is
220/// not supported.
221///
222bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
223                                                   JITCodeEmitter &JCE,
224                                                   CodeGenOpt::Level OptLevel) {
225  // Make sure the code model is set.
226  setCodeModelForJIT();
227
228  // Add common CodeGen passes.
229  if (addCommonCodeGenPasses(PM, OptLevel))
230    return true;
231
232  addCodeEmitter(PM, OptLevel, JCE);
233  if (PrintEmittedAsm)
234    addAssemblyEmitter(PM, OptLevel, true, ferrs());
235
236  PM.add(createGCInfoDeleter());
237
238  return false; // success!
239}
240
241static void printAndVerify(PassManagerBase &PM,
242                           const char *Banner,
243                           bool allowDoubleDefs = false) {
244  if (PrintMachineCode)
245    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
246
247  if (VerifyMachineCode)
248    PM.add(createMachineVerifierPass(allowDoubleDefs));
249}
250
251/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
252/// emitting to assembly files or machine code output.
253///
254bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
255                                               CodeGenOpt::Level OptLevel) {
256  // Standard LLVM-Level Passes.
257
258  // Optionally, tun split-GEPs and no-load GVN.
259  if (EnableSplitGEPGVN) {
260    PM.add(createGEPSplitterPass());
261    PM.add(createGVNPass(/*NoPRE=*/false, /*NoLoads=*/true));
262  }
263
264  // Run loop strength reduction before anything else.
265  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
266    PM.add(createLoopStrengthReducePass(getTargetLowering()));
267    if (PrintLSR)
268      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
269  }
270
271  // Turn exception handling constructs into something the code generators can
272  // handle.
273  switch (getMCAsmInfo()->getExceptionHandlingType())
274  {
275  case ExceptionHandling::SjLj:
276    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
277    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
278    // catch info can get misplaced when a selector ends up more than one block
279    // removed from the parent invoke(s). This could happen when a landing
280    // pad is shared by multiple invokes and is also a target of a normal
281    // edge from elsewhere.
282    PM.add(createSjLjEHPass(getTargetLowering()));
283    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
284    break;
285  case ExceptionHandling::Dwarf:
286    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
287    break;
288  case ExceptionHandling::None:
289    PM.add(createLowerInvokePass(getTargetLowering()));
290    break;
291  }
292
293  PM.add(createGCLoweringPass());
294
295  // Make sure that no unreachable blocks are instruction selected.
296  PM.add(createUnreachableBlockEliminationPass());
297
298  if (OptLevel != CodeGenOpt::None && !DisableCGP)
299    PM.add(createCodeGenPreparePass(getTargetLowering()));
300
301  PM.add(createStackProtectorPass(getTargetLowering()));
302
303  if (PrintISelInput)
304    PM.add(createPrintFunctionPass("\n\n"
305                                   "*** Final LLVM Code input to ISel ***\n",
306                                   &dbgs()));
307
308  // Standard Lower-Level Passes.
309
310  // Set up a MachineFunction for the rest of CodeGen to work on.
311  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
312
313  // Enable FastISel with -fast, but allow that to be overridden.
314  if (EnableFastISelOption == cl::BOU_TRUE ||
315      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
316    EnableFastISel = true;
317
318  // Ask the target for an isel.
319  if (addInstSelector(PM, OptLevel))
320    return true;
321
322  // Print the instruction selected machine code...
323  printAndVerify(PM, "After Instruction Selection",
324                 /* allowDoubleDefs= */ true);
325
326  if (OptLevel != CodeGenOpt::None) {
327    PM.add(createOptimizeExtsPass());
328    if (!DisableMachineLICM)
329      PM.add(createMachineLICMPass());
330    if (!DisableMachineSink)
331      PM.add(createMachineSinkingPass());
332    printAndVerify(PM, "After MachineLICM and MachineSinking",
333                   /* allowDoubleDefs= */ true);
334  }
335
336  // Pre-ra tail duplication.
337  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
338    PM.add(createTailDuplicatePass(true));
339    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
340                   /* allowDoubleDefs= */ true);
341  }
342
343  // Run pre-ra passes.
344  if (addPreRegAlloc(PM, OptLevel))
345    printAndVerify(PM, "After PreRegAlloc passes",
346                   /* allowDoubleDefs= */ true);
347
348  // Perform register allocation.
349  PM.add(createRegisterAllocator());
350  printAndVerify(PM, "After Register Allocation");
351
352  // Perform stack slot coloring.
353  if (OptLevel != CodeGenOpt::None && !DisableSSC) {
354    // FIXME: Re-enable coloring with register when it's capable of adding
355    // kill markers.
356    PM.add(createStackSlotColoringPass(false));
357    printAndVerify(PM, "After StackSlotColoring");
358  }
359
360  // Run post-ra passes.
361  if (addPostRegAlloc(PM, OptLevel))
362    printAndVerify(PM, "After PostRegAlloc passes");
363
364  PM.add(createLowerSubregsPass());
365  printAndVerify(PM, "After LowerSubregs");
366
367  // Insert prolog/epilog code.  Eliminate abstract frame index references...
368  PM.add(createPrologEpilogCodeInserter());
369  printAndVerify(PM, "After PrologEpilogCodeInserter");
370
371  // Run pre-sched2 passes.
372  if (addPreSched2(PM, OptLevel))
373    printAndVerify(PM, "After PreSched2 passes");
374
375  // Second pass scheduler.
376  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
377    PM.add(createPostRAScheduler(OptLevel));
378    printAndVerify(PM, "After PostRAScheduler");
379  }
380
381  // Branch folding must be run after regalloc and prolog/epilog insertion.
382  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
383    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
384    printAndVerify(PM, "After BranchFolding");
385  }
386
387  // Tail duplication.
388  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
389    PM.add(createTailDuplicatePass(false));
390    printAndVerify(PM, "After TailDuplicate");
391  }
392
393  PM.add(createGCMachineCodeAnalysisPass());
394
395  if (PrintGCInfo)
396    PM.add(createGCInfoPrinter(dbgs()));
397
398  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
399    PM.add(createCodePlacementOptPass());
400    printAndVerify(PM, "After CodePlacementOpt");
401  }
402
403  if (addPreEmitPass(PM, OptLevel))
404    printAndVerify(PM, "After PreEmit passes");
405
406  return false;
407}
408