LLVMTargetMachine.cpp revision 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Passes.h"
17#include "llvm/Analysis/Verifier.h"
18#include "llvm/Assembly/PrintModulePass.h"
19#include "llvm/CodeGen/AsmPrinter.h"
20#include "llvm/CodeGen/MachineFunctionAnalysis.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/GCStrategy.h"
23#include "llvm/CodeGen/Passes.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Target/TargetOptions.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCStreamer.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/Target/TargetData.h"
31#include "llvm/Target/TargetInstrInfo.h"
32#include "llvm/Target/TargetLowering.h"
33#include "llvm/Target/TargetLoweringObjectFile.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Target/TargetSubtargetInfo.h"
36#include "llvm/Transforms/Scalar.h"
37#include "llvm/ADT/OwningPtr.h"
38#include "llvm/Support/CommandLine.h"
39#include "llvm/Support/Debug.h"
40#include "llvm/Support/FormattedStream.h"
41#include "llvm/Support/TargetRegistry.h"
42using namespace llvm;
43
44namespace llvm {
45  bool EnableFastISel;
46}
47
48static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
49    cl::desc("Disable Post Regalloc"));
50static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
51    cl::desc("Disable branch folding"));
52static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
53    cl::desc("Disable tail duplication"));
54static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
55    cl::desc("Disable pre-register allocation tail duplication"));
56static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
57    cl::desc("Disable code placement"));
58static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
59    cl::desc("Disable Stack Slot Coloring"));
60static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
61    cl::desc("Disable Machine Dead Code Elimination"));
62static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
63    cl::desc("Disable Machine LICM"));
64static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
65    cl::desc("Disable Machine Common Subexpression Elimination"));
66static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
67    cl::Hidden,
68    cl::desc("Disable Machine LICM"));
69static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
70    cl::desc("Disable Machine Sinking"));
71static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
72    cl::desc("Disable Loop Strength Reduction Pass"));
73static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
74    cl::desc("Disable Codegen Prepare"));
75static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
76    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
77static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
78    cl::desc("Print LLVM IR input to isel pass"));
79static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
80    cl::desc("Dump garbage collector data"));
81static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
82    cl::desc("Show encoding in .s output"));
83static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
84    cl::desc("Show instruction structure in .s output"));
85static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
86    cl::desc("Enable MC API logging"));
87static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
88    cl::desc("Verify generated machine code"),
89    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
90
91static cl::opt<cl::boolOrDefault>
92AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
93           cl::init(cl::BOU_UNSET));
94
95static bool getVerboseAsm() {
96  switch (AsmVerbose) {
97  default:
98  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
99  case cl::BOU_TRUE:  return true;
100  case cl::BOU_FALSE: return false;
101  }
102}
103
104// Enable or disable FastISel. Both options are needed, because
105// FastISel is enabled by default with -fast, and we wish to be
106// able to enable or disable fast-isel independently from -O0.
107static cl::opt<cl::boolOrDefault>
108EnableFastISelOption("fast-isel", cl::Hidden,
109  cl::desc("Enable the \"fast\" instruction selector"));
110
111LLVMTargetMachine::LLVMTargetMachine(const Target &T, StringRef Triple,
112                                     StringRef CPU, StringRef FS,
113                                     Reloc::Model RM, CodeModel::Model CM)
114  : TargetMachine(T, Triple, CPU, FS) {
115  CodeGenInfo = T.createMCCodeGenInfo(Triple, RM, CM);
116  AsmInfo = T.createMCAsmInfo(Triple);
117}
118
119bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
120                                            formatted_raw_ostream &Out,
121                                            CodeGenFileType FileType,
122                                            CodeGenOpt::Level OptLevel,
123                                            bool DisableVerify) {
124  // Add common CodeGen passes.
125  MCContext *Context = 0;
126  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
127    return true;
128  assert(Context != 0 && "Failed to get MCContext");
129
130  if (hasMCSaveTempLabels())
131    Context->setAllowTemporaryLabels(false);
132
133  const MCAsmInfo &MAI = *getMCAsmInfo();
134  OwningPtr<MCStreamer> AsmStreamer;
135
136  switch (FileType) {
137  default: return true;
138  case CGFT_AssemblyFile: {
139    MCInstPrinter *InstPrinter =
140      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
141
142    // Create a code emitter if asked to show the encoding.
143    MCCodeEmitter *MCE = 0;
144    MCAsmBackend *MAB = 0;
145    if (ShowMCEncoding) {
146      const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
147      MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI, *Context);
148      MAB = getTarget().createMCAsmBackend(getTargetTriple());
149    }
150
151    MCStreamer *S = getTarget().createAsmStreamer(*Context, Out,
152                                                  getVerboseAsm(),
153                                                  hasMCUseLoc(),
154                                                  hasMCUseCFI(),
155                                                  InstPrinter,
156                                                  MCE, MAB,
157                                                  ShowMCInst);
158    AsmStreamer.reset(S);
159    break;
160  }
161  case CGFT_ObjectFile: {
162    // Create the code emitter for the target if it exists.  If not, .o file
163    // emission fails.
164    const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
165    MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(), STI,
166                                                         *Context);
167    MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
168    if (MCE == 0 || MAB == 0)
169      return true;
170
171    AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(),
172                                                         *Context, *MAB, Out,
173                                                         MCE, hasMCRelaxAll(),
174                                                         hasMCNoExecStack()));
175    AsmStreamer.get()->InitSections();
176    break;
177  }
178  case CGFT_Null:
179    // The Null output is intended for use for performance analysis and testing,
180    // not real users.
181    AsmStreamer.reset(createNullStreamer(*Context));
182    break;
183  }
184
185  if (EnableMCLogging)
186    AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
187
188  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
189  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
190  if (Printer == 0)
191    return true;
192
193  // If successful, createAsmPrinter took ownership of AsmStreamer.
194  AsmStreamer.take();
195
196  PM.add(Printer);
197
198  PM.add(createGCInfoDeleter());
199  return false;
200}
201
202/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
203/// get machine code emitted.  This uses a JITCodeEmitter object to handle
204/// actually outputting the machine code and resolving things like the address
205/// of functions.  This method should returns true if machine code emission is
206/// not supported.
207///
208bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
209                                                   JITCodeEmitter &JCE,
210                                                   CodeGenOpt::Level OptLevel,
211                                                   bool DisableVerify) {
212  // Add common CodeGen passes.
213  MCContext *Ctx = 0;
214  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
215    return true;
216
217  addCodeEmitter(PM, OptLevel, JCE);
218  PM.add(createGCInfoDeleter());
219
220  return false; // success!
221}
222
223/// addPassesToEmitMC - Add passes to the specified pass manager to get
224/// machine code emitted with the MCJIT. This method returns true if machine
225/// code is not supported. It fills the MCContext Ctx pointer which can be
226/// used to build custom MCStreamer.
227///
228bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
229                                          MCContext *&Ctx,
230                                          raw_ostream &Out,
231                                          CodeGenOpt::Level OptLevel,
232                                          bool DisableVerify) {
233  // Add common CodeGen passes.
234  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
235    return true;
236
237  if (hasMCSaveTempLabels())
238    Ctx->setAllowTemporaryLabels(false);
239
240  // Create the code emitter for the target if it exists.  If not, .o file
241  // emission fails.
242  const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>();
243  MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(*getInstrInfo(),STI, *Ctx);
244  MCAsmBackend *MAB = getTarget().createMCAsmBackend(getTargetTriple());
245  if (MCE == 0 || MAB == 0)
246    return true;
247
248  OwningPtr<MCStreamer> AsmStreamer;
249  AsmStreamer.reset(getTarget().createMCObjectStreamer(getTargetTriple(), *Ctx,
250                                                       *MAB, Out, MCE,
251                                                       hasMCRelaxAll(),
252                                                       hasMCNoExecStack()));
253  AsmStreamer.get()->InitSections();
254
255  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
256  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
257  if (Printer == 0)
258    return true;
259
260  // If successful, createAsmPrinter took ownership of AsmStreamer.
261  AsmStreamer.take();
262
263  PM.add(Printer);
264
265  return false; // success!
266}
267
268static void printNoVerify(PassManagerBase &PM, const char *Banner) {
269  if (PrintMachineCode)
270    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
271}
272
273static void printAndVerify(PassManagerBase &PM,
274                           const char *Banner) {
275  if (PrintMachineCode)
276    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
277
278  if (VerifyMachineCode)
279    PM.add(createMachineVerifierPass(Banner));
280}
281
282/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
283/// emitting to assembly files or machine code output.
284///
285bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
286                                               CodeGenOpt::Level OptLevel,
287                                               bool DisableVerify,
288                                               MCContext *&OutContext) {
289  // Standard LLVM-Level Passes.
290
291  // Basic AliasAnalysis support.
292  // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
293  // BasicAliasAnalysis wins if they disagree. This is intended to help
294  // support "obvious" type-punning idioms.
295  PM.add(createTypeBasedAliasAnalysisPass());
296  PM.add(createBasicAliasAnalysisPass());
297
298  // Before running any passes, run the verifier to determine if the input
299  // coming from the front-end and/or optimizer is valid.
300  if (!DisableVerify)
301    PM.add(createVerifierPass());
302
303  // Run loop strength reduction before anything else.
304  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
305    PM.add(createLoopStrengthReducePass(getTargetLowering()));
306    if (PrintLSR)
307      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
308  }
309
310  PM.add(createGCLoweringPass());
311
312  // Make sure that no unreachable blocks are instruction selected.
313  PM.add(createUnreachableBlockEliminationPass());
314
315  // Turn exception handling constructs into something the code generators can
316  // handle.
317  switch (getMCAsmInfo()->getExceptionHandlingType()) {
318  case ExceptionHandling::SjLj:
319    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
320    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
321    // catch info can get misplaced when a selector ends up more than one block
322    // removed from the parent invoke(s). This could happen when a landing
323    // pad is shared by multiple invokes and is also a target of a normal
324    // edge from elsewhere.
325    PM.add(createSjLjEHPass(getTargetLowering()));
326    // FALLTHROUGH
327  case ExceptionHandling::DwarfCFI:
328  case ExceptionHandling::ARM:
329  case ExceptionHandling::Win64:
330    PM.add(createDwarfEHPass(this));
331    break;
332  case ExceptionHandling::None:
333    PM.add(createLowerInvokePass(getTargetLowering()));
334
335    // The lower invoke pass may create unreachable code. Remove it.
336    PM.add(createUnreachableBlockEliminationPass());
337    break;
338  }
339
340  if (OptLevel != CodeGenOpt::None && !DisableCGP)
341    PM.add(createCodeGenPreparePass(getTargetLowering()));
342
343  PM.add(createStackProtectorPass(getTargetLowering()));
344
345  addPreISel(PM, OptLevel);
346
347  if (PrintISelInput)
348    PM.add(createPrintFunctionPass("\n\n"
349                                   "*** Final LLVM Code input to ISel ***\n",
350                                   &dbgs()));
351
352  // All passes which modify the LLVM IR are now complete; run the verifier
353  // to ensure that the IR is valid.
354  if (!DisableVerify)
355    PM.add(createVerifierPass());
356
357  // Standard Lower-Level Passes.
358
359  // Install a MachineModuleInfo class, which is an immutable pass that holds
360  // all the per-module stuff we're generating, including MCContext.
361  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
362                                                 *getRegisterInfo(),
363                                     &getTargetLowering()->getObjFileLowering());
364  PM.add(MMI);
365  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
366
367  // Set up a MachineFunction for the rest of CodeGen to work on.
368  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
369
370  // Enable FastISel with -fast, but allow that to be overridden.
371  if (EnableFastISelOption == cl::BOU_TRUE ||
372      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
373    EnableFastISel = true;
374
375  // Ask the target for an isel.
376  if (addInstSelector(PM, OptLevel))
377    return true;
378
379  // Print the instruction selected machine code...
380  printAndVerify(PM, "After Instruction Selection");
381
382  // Expand pseudo-instructions emitted by ISel.
383  PM.add(createExpandISelPseudosPass());
384
385  // Pre-ra tail duplication.
386  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
387    PM.add(createTailDuplicatePass(true));
388    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
389  }
390
391  // Optimize PHIs before DCE: removing dead PHI cycles may make more
392  // instructions dead.
393  if (OptLevel != CodeGenOpt::None)
394    PM.add(createOptimizePHIsPass());
395
396  // If the target requests it, assign local variables to stack slots relative
397  // to one another and simplify frame index references where possible.
398  PM.add(createLocalStackSlotAllocationPass());
399
400  if (OptLevel != CodeGenOpt::None) {
401    // With optimization, dead code should already be eliminated. However
402    // there is one known exception: lowered code for arguments that are only
403    // used by tail calls, where the tail calls reuse the incoming stack
404    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
405    if (!DisableMachineDCE)
406      PM.add(createDeadMachineInstructionElimPass());
407    printAndVerify(PM, "After codegen DCE pass");
408
409    if (!DisableMachineLICM)
410      PM.add(createMachineLICMPass());
411    if (!DisableMachineCSE)
412      PM.add(createMachineCSEPass());
413    if (!DisableMachineSink)
414      PM.add(createMachineSinkingPass());
415    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
416
417    PM.add(createPeepholeOptimizerPass());
418    printAndVerify(PM, "After codegen peephole optimization pass");
419  }
420
421  // Run pre-ra passes.
422  if (addPreRegAlloc(PM, OptLevel))
423    printAndVerify(PM, "After PreRegAlloc passes");
424
425  // Perform register allocation.
426  PM.add(createRegisterAllocator(OptLevel));
427  printAndVerify(PM, "After Register Allocation");
428
429  // Perform stack slot coloring and post-ra machine LICM.
430  if (OptLevel != CodeGenOpt::None) {
431    // FIXME: Re-enable coloring with register when it's capable of adding
432    // kill markers.
433    if (!DisableSSC)
434      PM.add(createStackSlotColoringPass(false));
435
436    // Run post-ra machine LICM to hoist reloads / remats.
437    if (!DisablePostRAMachineLICM)
438      PM.add(createMachineLICMPass(false));
439
440    printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
441  }
442
443  // Run post-ra passes.
444  if (addPostRegAlloc(PM, OptLevel))
445    printAndVerify(PM, "After PostRegAlloc passes");
446
447  PM.add(createLowerSubregsPass());
448  printAndVerify(PM, "After LowerSubregs");
449
450  // Insert prolog/epilog code.  Eliminate abstract frame index references...
451  PM.add(createPrologEpilogCodeInserter());
452  printAndVerify(PM, "After PrologEpilogCodeInserter");
453
454  // Run pre-sched2 passes.
455  if (addPreSched2(PM, OptLevel))
456    printAndVerify(PM, "After PreSched2 passes");
457
458  // Second pass scheduler.
459  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
460    PM.add(createPostRAScheduler(OptLevel));
461    printAndVerify(PM, "After PostRAScheduler");
462  }
463
464  // Branch folding must be run after regalloc and prolog/epilog insertion.
465  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
466    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
467    printNoVerify(PM, "After BranchFolding");
468  }
469
470  // Tail duplication.
471  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
472    PM.add(createTailDuplicatePass(false));
473    printNoVerify(PM, "After TailDuplicate");
474  }
475
476  PM.add(createGCMachineCodeAnalysisPass());
477
478  if (PrintGCInfo)
479    PM.add(createGCInfoPrinter(dbgs()));
480
481  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
482    PM.add(createCodePlacementOptPass());
483    printNoVerify(PM, "After CodePlacementOpt");
484  }
485
486  if (addPreEmitPass(PM, OptLevel))
487    printNoVerify(PM, "After PreEmit passes");
488
489  return false;
490}
491