LLVMTargetMachine.cpp revision 4ae641f4d12c60ee1aaca5e42b6de231c6a02c40 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/Analysis/LoopPass.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/GCStrategy.h"
21#include "llvm/Target/TargetOptions.h"
22#include "llvm/Target/TargetAsmInfo.h"
23#include "llvm/Transforms/Scalar.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/raw_ostream.h"
26using namespace llvm;
27
28namespace llvm {
29  bool EnableFastISel;
30}
31
32static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35    cl::desc("Print LLVM IR input to isel pass"));
36static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37    cl::desc("Dump emitter generated instructions as assembly"));
38static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39    cl::desc("Dump garbage collector data"));
40
41// Hidden options to help debugging
42static cl::opt<bool>
43EnableSinking("enable-sinking", cl::init(false), cl::Hidden,
44              cl::desc("Perform sinking on machine code"));
45static cl::opt<bool>
46EnableLICM("machine-licm",
47           cl::init(false), cl::Hidden,
48           cl::desc("Perform loop-invariant code motion on machine code"));
49
50// When this works it will be on by default.
51static cl::opt<bool>
52DisablePostRAScheduler("disable-post-RA-scheduler",
53                       cl::desc("Disable scheduling after register allocation"),
54                       cl::init(true));
55
56// Enable or disable FastISel. Both options are needed, because
57// FastISel is enabled by default with -fast, and we wish to be
58// able to enable or disable fast-isel independently from -fast.
59static cl::opt<bool>
60EnableFastISelOption("fast-isel", cl::Hidden,
61  cl::desc("Enable the experimental \"fast\" instruction selector"));
62static cl::opt<bool>
63DisableFastISelOption("disable-fast-isel", cl::Hidden,
64  cl::desc("Disable the experimental \"fast\" instruction selector"));
65
66FileModel::Model
67LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
68                                       raw_ostream &Out,
69                                       CodeGenFileType FileType,
70                                       bool Fast) {
71  // Add common CodeGen passes.
72  if (addCommonCodeGenPasses(PM, Fast))
73    return FileModel::Error;
74
75  // Fold redundant debug labels.
76  PM.add(createDebugLabelFoldingPass());
77
78  if (PrintMachineCode)
79    PM.add(createMachineFunctionPrinterPass(cerr));
80
81  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
82    PM.add(createMachineFunctionPrinterPass(cerr));
83
84  if (!Fast)
85    PM.add(createLoopAlignerPass());
86
87  switch (FileType) {
88  default:
89    break;
90  case TargetMachine::AssemblyFile:
91    if (addAssemblyEmitter(PM, Fast, Out))
92      return FileModel::Error;
93    return FileModel::AsmFile;
94  case TargetMachine::ObjectFile:
95    if (getMachOWriterInfo())
96      return FileModel::MachOFile;
97    else if (getELFWriterInfo())
98      return FileModel::ElfFile;
99  }
100
101  return FileModel::Error;
102}
103
104/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
105/// be split up (e.g., to add an object writer pass), this method can be used to
106/// finish up adding passes to emit the file, if necessary.
107bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
108                                                  MachineCodeEmitter *MCE,
109                                                  bool Fast) {
110  if (MCE)
111    addSimpleCodeEmitter(PM, Fast, PrintEmittedAsm, *MCE);
112
113  PM.add(createGCInfoDeleter());
114
115  // Delete machine code for this function
116  PM.add(createMachineCodeDeleter());
117
118  return false; // success!
119}
120
121/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
122/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
123/// actually outputting the machine code and resolving things like the address
124/// of functions.  This method should returns true if machine code emission is
125/// not supported.
126///
127bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
128                                                   MachineCodeEmitter &MCE,
129                                                   bool Fast) {
130  // Add common CodeGen passes.
131  if (addCommonCodeGenPasses(PM, Fast))
132    return true;
133
134  if (addPreEmitPass(PM, Fast) && PrintMachineCode)
135    PM.add(createMachineFunctionPrinterPass(cerr));
136
137  addCodeEmitter(PM, Fast, PrintEmittedAsm, MCE);
138
139  PM.add(createGCInfoDeleter());
140
141  // Delete machine code for this function
142  PM.add(createMachineCodeDeleter());
143
144  return false; // success!
145}
146
147/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
148/// both emitting to assembly files or machine code output.
149///
150bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, bool Fast) {
151  // Standard LLVM-Level Passes.
152
153  // Run loop strength reduction before anything else.
154  if (!Fast) {
155    PM.add(createLoopStrengthReducePass(getTargetLowering()));
156    if (PrintLSR)
157      PM.add(new PrintFunctionPass("\n\n*** Code after LSR ***\n", &cerr));
158  }
159
160  PM.add(createGCLoweringPass());
161
162  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
163    PM.add(createLowerInvokePass(getTargetLowering()));
164
165  // Make sure that no unreachable blocks are instruction selected.
166  PM.add(createUnreachableBlockEliminationPass());
167
168  if (!Fast)
169    PM.add(createCodeGenPreparePass(getTargetLowering()));
170
171  if (PrintISelInput)
172    PM.add(new PrintFunctionPass("\n\n*** Final LLVM Code input to ISel ***\n",
173                                 &cerr));
174
175  // Standard Lower-Level Passes.
176
177  // Enable FastISel with -fast, but allow that to be overridden.
178  assert((!EnableFastISelOption || !DisableFastISelOption) &&
179         "Both -fast-isel and -disable-fast-isel given!");
180  if (EnableFastISelOption ||
181      (Fast && !DisableFastISelOption))
182    EnableFastISel = true;
183
184  // Ask the target for an isel.
185  if (addInstSelector(PM, Fast))
186    return true;
187
188  // Print the instruction selected machine code...
189  if (PrintMachineCode)
190    PM.add(createMachineFunctionPrinterPass(cerr));
191
192  // If we're using Fast-ISel, clean up the mess.
193  if (EnableFastISel)
194    PM.add(createDeadMachineInstructionElimPass());
195
196  if (EnableLICM)
197    PM.add(createMachineLICMPass());
198
199  if (EnableSinking)
200    PM.add(createMachineSinkingPass());
201
202  // Run pre-ra passes.
203  if (addPreRegAlloc(PM, Fast) && PrintMachineCode)
204    PM.add(createMachineFunctionPrinterPass(cerr));
205
206  // Perform register allocation.
207  PM.add(createRegisterAllocator());
208
209  // Perform stack slot coloring.
210  if (!Fast)
211    PM.add(createStackSlotColoringPass());
212
213  if (PrintMachineCode)  // Print the register-allocated code
214    PM.add(createMachineFunctionPrinterPass(cerr));
215
216  // Run post-ra passes.
217  if (addPostRegAlloc(PM, Fast) && PrintMachineCode)
218    PM.add(createMachineFunctionPrinterPass(cerr));
219
220  if (PrintMachineCode)
221    PM.add(createMachineFunctionPrinterPass(cerr));
222
223  PM.add(createLowerSubregsPass());
224
225  if (PrintMachineCode)  // Print the subreg lowered code
226    PM.add(createMachineFunctionPrinterPass(cerr));
227
228  // Insert prolog/epilog code.  Eliminate abstract frame index references...
229  PM.add(createPrologEpilogCodeInserter());
230
231  if (PrintMachineCode)
232    PM.add(createMachineFunctionPrinterPass(cerr));
233
234  // Second pass scheduler.
235  if (!Fast && !DisablePostRAScheduler)
236    PM.add(createPostRAScheduler());
237
238  // Branch folding must be run after regalloc and prolog/epilog insertion.
239  if (!Fast)
240    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
241
242  PM.add(createGCMachineCodeAnalysisPass());
243
244  if (PrintMachineCode)
245    PM.add(createMachineFunctionPrinterPass(cerr));
246
247  if (PrintGCInfo)
248    PM.add(createGCInfoPrinter(*cerr));
249
250  return false;
251}
252