LLVMTargetMachine.cpp revision 977dfcefa1b139de56fd17e108b263e39e16504f 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Verifier.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/MachineFunctionAnalysis.h"
20#include "llvm/CodeGen/MachineModuleInfo.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/Target/TargetData.h"
27#include "llvm/Target/TargetRegistry.h"
28#include "llvm/Transforms/Scalar.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/FormattedStream.h"
33using namespace llvm;
34
35namespace llvm {
36  bool EnableFastISel;
37}
38
39static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40    cl::desc("Disable Post Regalloc"));
41static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42    cl::desc("Disable branch folding"));
43static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44    cl::desc("Disable tail duplication"));
45static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46    cl::desc("Disable pre-register allocation tail duplication"));
47static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48    cl::desc("Disable code placement"));
49static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50    cl::desc("Disable Stack Slot Coloring"));
51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52    cl::desc("Disable Machine LICM"));
53static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
54    cl::desc("Disable Machine Sinking"));
55static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
56    cl::desc("Disable Loop Strength Reduction Pass"));
57static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
58    cl::desc("Disable Codegen Prepare"));
59static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
60    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
61static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
62    cl::desc("Print LLVM IR input to isel pass"));
63static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
64    cl::desc("Dump garbage collector data"));
65static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
66    cl::desc("Verify generated machine code"),
67    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
68
69static cl::opt<bool> PostRAMachineLICM("postra-machine-licm", cl::Hidden,
70    cl::desc("Enable post-regalloc Machine LICM"));
71
72static cl::opt<cl::boolOrDefault>
73AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
74           cl::init(cl::BOU_UNSET));
75
76static bool getVerboseAsm() {
77  switch (AsmVerbose) {
78  default:
79  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
80  case cl::BOU_TRUE:  return true;
81  case cl::BOU_FALSE: return false;
82  }
83}
84
85// Enable or disable FastISel. Both options are needed, because
86// FastISel is enabled by default with -fast, and we wish to be
87// able to enable or disable fast-isel independently from -O0.
88static cl::opt<cl::boolOrDefault>
89EnableFastISelOption("fast-isel", cl::Hidden,
90  cl::desc("Enable the \"fast\" instruction selector"));
91
92// Enable or disable an experimental optimization to split GEPs
93// and run a special GVN pass which does not examine loads, in
94// an effort to factor out redundancy implicit in complex GEPs.
95static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
96    cl::desc("Split GEPs and run no-load GVN"));
97
98LLVMTargetMachine::LLVMTargetMachine(const Target &T,
99                                     const std::string &Triple)
100  : TargetMachine(T), TargetTriple(Triple) {
101  AsmInfo = T.createAsmInfo(TargetTriple);
102}
103
104// Set the default code model for the JIT for a generic target.
105// FIXME: Is small right here? or .is64Bit() ? Large : Small?
106void LLVMTargetMachine::setCodeModelForJIT() {
107  setCodeModel(CodeModel::Small);
108}
109
110// Set the default code model for static compilation for a generic target.
111void LLVMTargetMachine::setCodeModelForStatic() {
112  setCodeModel(CodeModel::Small);
113}
114
115bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
116                                            formatted_raw_ostream &Out,
117                                            CodeGenFileType FileType,
118                                            CodeGenOpt::Level OptLevel,
119                                            bool DisableVerify) {
120  // Add common CodeGen passes.
121  MCContext *Context = 0;
122  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
123    return true;
124  assert(Context != 0 && "Failed to get MCContext");
125
126  const MCAsmInfo &MAI = *getMCAsmInfo();
127  OwningPtr<MCStreamer> AsmStreamer;
128
129  switch (FileType) {
130  default: return true;
131  case CGFT_AssemblyFile: {
132    MCInstPrinter *InstPrinter =
133      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
134    AsmStreamer.reset(createAsmStreamer(*Context, Out,
135                                        getTargetData()->isLittleEndian(),
136                                        getVerboseAsm(), InstPrinter,
137                                        /*codeemitter*/0));
138    break;
139  }
140  case CGFT_ObjectFile: {
141    // Create the code emitter for the target if it exists.  If not, .o file
142    // emission fails.
143    MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
144    TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
145    if (MCE == 0 || TAB == 0)
146      return true;
147
148    AsmStreamer.reset(createMachOStreamer(*Context, *TAB, Out, MCE));
149    break;
150  }
151  case CGFT_Null:
152    // The Null output is intended for use for performance analysis and testing,
153    // not real users.
154    AsmStreamer.reset(createNullStreamer(*Context));
155    break;
156  }
157
158  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
159  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
160  if (Printer == 0)
161    return true;
162
163  // If successful, createAsmPrinter took ownership of AsmStreamer.
164  AsmStreamer.take();
165
166  PM.add(Printer);
167
168  // Make sure the code model is set.
169  setCodeModelForStatic();
170  PM.add(createGCInfoDeleter());
171  return false;
172}
173
174/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
175/// get machine code emitted.  This uses a JITCodeEmitter object to handle
176/// actually outputting the machine code and resolving things like the address
177/// of functions.  This method should returns true if machine code emission is
178/// not supported.
179///
180bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
181                                                   JITCodeEmitter &JCE,
182                                                   CodeGenOpt::Level OptLevel,
183                                                   bool DisableVerify) {
184  // Make sure the code model is set.
185  setCodeModelForJIT();
186
187  // Add common CodeGen passes.
188  MCContext *Ctx = 0;
189  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
190    return true;
191
192  addCodeEmitter(PM, OptLevel, JCE);
193  PM.add(createGCInfoDeleter());
194
195  return false; // success!
196}
197
198static void printNoVerify(PassManagerBase &PM, const char *Banner) {
199  if (PrintMachineCode)
200    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
201}
202
203static void printAndVerify(PassManagerBase &PM,
204                           const char *Banner,
205                           bool allowDoubleDefs = false) {
206  if (PrintMachineCode)
207    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
208
209  if (VerifyMachineCode)
210    PM.add(createMachineVerifierPass(allowDoubleDefs));
211}
212
213/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
214/// emitting to assembly files or machine code output.
215///
216bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
217                                               CodeGenOpt::Level OptLevel,
218                                               bool DisableVerify,
219                                               MCContext *&OutContext) {
220  // Standard LLVM-Level Passes.
221
222  // Before running any passes, run the verifier to determine if the input
223  // coming from the front-end and/or optimizer is valid.
224  if (!DisableVerify)
225    PM.add(createVerifierPass());
226
227  // Optionally, tun split-GEPs and no-load GVN.
228  if (EnableSplitGEPGVN) {
229    PM.add(createGEPSplitterPass());
230    PM.add(createGVNPass(/*NoLoads=*/true));
231  }
232
233  // Run loop strength reduction before anything else.
234  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
235    PM.add(createLoopStrengthReducePass(getTargetLowering()));
236    if (PrintLSR)
237      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
238  }
239
240  // Turn exception handling constructs into something the code generators can
241  // handle.
242  switch (getMCAsmInfo()->getExceptionHandlingType()) {
243  case ExceptionHandling::SjLj:
244    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
245    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
246    // catch info can get misplaced when a selector ends up more than one block
247    // removed from the parent invoke(s). This could happen when a landing
248    // pad is shared by multiple invokes and is also a target of a normal
249    // edge from elsewhere.
250    PM.add(createSjLjEHPass(getTargetLowering()));
251    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
252    break;
253  case ExceptionHandling::Dwarf:
254    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
255    break;
256  case ExceptionHandling::None:
257    PM.add(createLowerInvokePass(getTargetLowering()));
258    break;
259  }
260
261  PM.add(createGCLoweringPass());
262
263  // Make sure that no unreachable blocks are instruction selected.
264  PM.add(createUnreachableBlockEliminationPass());
265
266  if (OptLevel != CodeGenOpt::None && !DisableCGP)
267    PM.add(createCodeGenPreparePass(getTargetLowering()));
268
269  PM.add(createStackProtectorPass(getTargetLowering()));
270
271  addPreISel(PM, OptLevel);
272
273  if (PrintISelInput)
274    PM.add(createPrintFunctionPass("\n\n"
275                                   "*** Final LLVM Code input to ISel ***\n",
276                                   &dbgs()));
277
278  // All passes which modify the LLVM IR are now complete; run the verifier
279  // to ensure that the IR is valid.
280  if (!DisableVerify)
281    PM.add(createVerifierPass());
282
283  // Standard Lower-Level Passes.
284
285  // Install a MachineModuleInfo class, which is an immutable pass that holds
286  // all the per-module stuff we're generating, including MCContext.
287  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo());
288  PM.add(MMI);
289  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
290
291
292  // Set up a MachineFunction for the rest of CodeGen to work on.
293  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
294
295  // Enable FastISel with -fast, but allow that to be overridden.
296  if (EnableFastISelOption == cl::BOU_TRUE ||
297      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
298    EnableFastISel = true;
299
300  // Ask the target for an isel.
301  if (addInstSelector(PM, OptLevel))
302    return true;
303
304  // Print the instruction selected machine code...
305  printAndVerify(PM, "After Instruction Selection",
306                 /* allowDoubleDefs= */ true);
307
308  // Optimize PHIs before DCE: removing dead PHI cycles may make more
309  // instructions dead.
310  if (OptLevel != CodeGenOpt::None)
311    PM.add(createOptimizePHIsPass());
312
313  // Delete dead machine instructions regardless of optimization level.
314  PM.add(createDeadMachineInstructionElimPass());
315  printAndVerify(PM, "After codegen DCE pass",
316                 /* allowDoubleDefs= */ true);
317
318  if (OptLevel != CodeGenOpt::None) {
319    PM.add(createOptimizeExtsPass());
320    if (!DisableMachineLICM)
321      PM.add(createMachineLICMPass());
322    PM.add(createMachineCSEPass());
323    if (!DisableMachineSink)
324      PM.add(createMachineSinkingPass());
325    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes",
326                   /* allowDoubleDefs= */ true);
327  }
328
329  // Pre-ra tail duplication.
330  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
331    PM.add(createTailDuplicatePass(true));
332    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
333                   /* allowDoubleDefs= */ true);
334  }
335
336  // Run pre-ra passes.
337  if (addPreRegAlloc(PM, OptLevel))
338    printAndVerify(PM, "After PreRegAlloc passes",
339                   /* allowDoubleDefs= */ true);
340
341  // Perform register allocation.
342  PM.add(createRegisterAllocator());
343  printAndVerify(PM, "After Register Allocation");
344
345  // Perform stack slot coloring.
346  if (OptLevel != CodeGenOpt::None && !DisableSSC) {
347    // FIXME: Re-enable coloring with register when it's capable of adding
348    // kill markers.
349    PM.add(createStackSlotColoringPass(false));
350    printAndVerify(PM, "After StackSlotColoring");
351
352    // Run post-ra machine LICM to hoist reloads / remats.
353    if (PostRAMachineLICM)
354      PM.add(createMachineLICMPass(false));
355  }
356
357  // Run post-ra passes.
358  if (addPostRegAlloc(PM, OptLevel))
359    printAndVerify(PM, "After PostRegAlloc passes");
360
361  PM.add(createLowerSubregsPass());
362  printAndVerify(PM, "After LowerSubregs");
363
364  // Insert prolog/epilog code.  Eliminate abstract frame index references...
365  PM.add(createPrologEpilogCodeInserter());
366  printAndVerify(PM, "After PrologEpilogCodeInserter");
367
368  // Run pre-sched2 passes.
369  if (addPreSched2(PM, OptLevel))
370    printAndVerify(PM, "After PreSched2 passes");
371
372  // Second pass scheduler.
373  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
374    PM.add(createPostRAScheduler(OptLevel));
375    printAndVerify(PM, "After PostRAScheduler");
376  }
377
378  // Branch folding must be run after regalloc and prolog/epilog insertion.
379  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
380    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
381    printNoVerify(PM, "After BranchFolding");
382  }
383
384  // Tail duplication.
385  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
386    PM.add(createTailDuplicatePass(false));
387    printNoVerify(PM, "After TailDuplicate");
388  }
389
390  PM.add(createGCMachineCodeAnalysisPass());
391
392  if (PrintGCInfo)
393    PM.add(createGCInfoPrinter(dbgs()));
394
395  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
396    PM.add(createCodePlacementOptPass());
397    printNoVerify(PM, "After CodePlacementOpt");
398  }
399
400  if (addPreEmitPass(PM, OptLevel))
401    printNoVerify(PM, "After PreEmit passes");
402
403  return false;
404}
405