LLVMTargetMachine.cpp revision a3f99f90338d89354384ca25f53ca4450a1a9d18 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/Analysis/LoopPass.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/GCStrategy.h"
21#include "llvm/Target/TargetOptions.h"
22#include "llvm/Target/TargetAsmInfo.h"
23#include "llvm/Transforms/Scalar.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/raw_ostream.h"
26using namespace llvm;
27
28namespace llvm {
29  bool EnableFastISel;
30}
31
32static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35    cl::desc("Print LLVM IR input to isel pass"));
36static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37    cl::desc("Dump emitter generated instructions as assembly"));
38static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39    cl::desc("Dump garbage collector data"));
40static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
41    cl::desc("Verify generated machine code"),
42    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
43
44// When this works it will be on by default.
45static cl::opt<bool>
46DisablePostRAScheduler("disable-post-RA-scheduler",
47                       cl::desc("Disable scheduling after register allocation"),
48                       cl::init(true));
49
50// Enable or disable FastISel. Both options are needed, because
51// FastISel is enabled by default with -fast, and we wish to be
52// able to enable or disable fast-isel independently from -fast.
53static cl::opt<cl::boolOrDefault>
54EnableFastISelOption("fast-isel", cl::Hidden,
55  cl::desc("Enable the experimental \"fast\" instruction selector"));
56
57FileModel::Model
58LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
59                                       raw_ostream &Out,
60                                       CodeGenFileType FileType,
61                                       CodeGenOpt::Level OptLevel) {
62  // Add common CodeGen passes.
63  if (addCommonCodeGenPasses(PM, OptLevel))
64    return FileModel::Error;
65
66  // Fold redundant debug labels.
67  PM.add(createDebugLabelFoldingPass());
68
69  if (PrintMachineCode)
70    PM.add(createMachineFunctionPrinterPass(cerr));
71
72  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
73    PM.add(createMachineFunctionPrinterPass(cerr));
74
75  if (OptLevel != CodeGenOpt::None)
76    PM.add(createCodePlacementOptPass());
77
78  switch (FileType) {
79  default:
80    break;
81  case TargetMachine::AssemblyFile:
82    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
83      return FileModel::Error;
84    return FileModel::AsmFile;
85  case TargetMachine::ObjectFile:
86    if (getMachOWriterInfo())
87      return FileModel::MachOFile;
88    else if (getELFWriterInfo())
89      return FileModel::ElfFile;
90  }
91
92  return FileModel::Error;
93}
94
95/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
96/// be split up (e.g., to add an object writer pass), this method can be used to
97/// finish up adding passes to emit the file, if necessary.
98bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
99                                                  MachineCodeEmitter *MCE,
100                                                  CodeGenOpt::Level OptLevel) {
101  if (MCE)
102    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
103
104  PM.add(createGCInfoDeleter());
105
106  // Delete machine code for this function
107  PM.add(createMachineCodeDeleter());
108
109  return false; // success!
110}
111
112/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
113/// be split up (e.g., to add an object writer pass), this method can be used to
114/// finish up adding passes to emit the file, if necessary.
115bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
116                                                  JITCodeEmitter *JCE,
117                                                  CodeGenOpt::Level OptLevel) {
118  if (JCE)
119    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *JCE);
120
121  PM.add(createGCInfoDeleter());
122
123  // Delete machine code for this function
124  PM.add(createMachineCodeDeleter());
125
126  return false; // success!
127}
128
129/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
130/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
131/// actually outputting the machine code and resolving things like the address
132/// of functions.  This method should returns true if machine code emission is
133/// not supported.
134///
135bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
136                                                   MachineCodeEmitter &MCE,
137                                                   CodeGenOpt::Level OptLevel) {
138  // Add common CodeGen passes.
139  if (addCommonCodeGenPasses(PM, OptLevel))
140    return true;
141
142  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
143    PM.add(createMachineFunctionPrinterPass(cerr));
144
145  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
146
147  PM.add(createGCInfoDeleter());
148
149  // Delete machine code for this function
150  PM.add(createMachineCodeDeleter());
151
152  return false; // success!
153}
154
155/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
156/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
157/// actually outputting the machine code and resolving things like the address
158/// of functions.  This method should returns true if machine code emission is
159/// not supported.
160///
161bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
162                                                   JITCodeEmitter &JCE,
163                                                   CodeGenOpt::Level OptLevel) {
164  // Add common CodeGen passes.
165  if (addCommonCodeGenPasses(PM, OptLevel))
166    return true;
167
168  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
169    PM.add(createMachineFunctionPrinterPass(cerr));
170
171  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, JCE);
172
173  PM.add(createGCInfoDeleter());
174
175  // Delete machine code for this function
176  PM.add(createMachineCodeDeleter());
177
178  return false; // success!
179}
180
181static void printAndVerify(PassManagerBase &PM,
182                           bool allowDoubleDefs = false) {
183  if (PrintMachineCode)
184    PM.add(createMachineFunctionPrinterPass(cerr));
185
186  if (VerifyMachineCode)
187    PM.add(createMachineVerifierPass(allowDoubleDefs));
188}
189
190/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
191/// emitting to assembly files or machine code output.
192///
193bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
194                                               CodeGenOpt::Level OptLevel) {
195  // Standard LLVM-Level Passes.
196
197  // Run loop strength reduction before anything else.
198  if (OptLevel != CodeGenOpt::None) {
199    PM.add(createLoopStrengthReducePass(getTargetLowering()));
200    if (PrintLSR)
201      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
202  }
203
204  // Turn exception handling constructs into something the code generators can
205  // handle.
206  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
207    PM.add(createLowerInvokePass(getTargetLowering()));
208  else
209    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
210
211  PM.add(createGCLoweringPass());
212
213  // Make sure that no unreachable blocks are instruction selected.
214  PM.add(createUnreachableBlockEliminationPass());
215
216  if (OptLevel != CodeGenOpt::None)
217    PM.add(createCodeGenPreparePass(getTargetLowering()));
218
219  PM.add(createStackProtectorPass(getTargetLowering()));
220
221  if (PrintISelInput)
222    PM.add(createPrintFunctionPass("\n\n"
223                                   "*** Final LLVM Code input to ISel ***\n",
224                                   &errs()));
225
226  // Standard Lower-Level Passes.
227
228  // Enable FastISel with -fast, but allow that to be overridden.
229  if (EnableFastISelOption == cl::BOU_TRUE ||
230      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
231    EnableFastISel = true;
232
233  // Ask the target for an isel.
234  if (addInstSelector(PM, OptLevel))
235    return true;
236
237  // Print the instruction selected machine code...
238  printAndVerify(PM, /* allowDoubleDefs= */ true);
239
240  if (OptLevel != CodeGenOpt::None) {
241    PM.add(createMachineLICMPass());
242    PM.add(createMachineSinkingPass());
243    printAndVerify(PM, /* allowDoubleDefs= */ true);
244  }
245
246  // Run pre-ra passes.
247  if (addPreRegAlloc(PM, OptLevel))
248    printAndVerify(PM);
249
250  // Perform register allocation.
251  PM.add(createRegisterAllocator());
252
253  // Perform stack slot coloring.
254  if (OptLevel != CodeGenOpt::None)
255    PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
256
257  printAndVerify(PM);           // Print the register-allocated code
258
259  // Run post-ra passes.
260  if (addPostRegAlloc(PM, OptLevel))
261    printAndVerify(PM);
262
263  PM.add(createLowerSubregsPass());
264  printAndVerify(PM);
265
266  // Insert prolog/epilog code.  Eliminate abstract frame index references...
267  PM.add(createPrologEpilogCodeInserter());
268  printAndVerify(PM);
269
270  // Second pass scheduler.
271  if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
272    PM.add(createPostRAScheduler());
273    printAndVerify(PM);
274  }
275
276  // Branch folding must be run after regalloc and prolog/epilog insertion.
277  if (OptLevel != CodeGenOpt::None) {
278    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
279    printAndVerify(PM);
280  }
281
282  PM.add(createGCMachineCodeAnalysisPass());
283  printAndVerify(PM);
284
285  if (PrintGCInfo)
286    PM.add(createGCInfoPrinter(*cerr));
287
288  return false;
289}
290