LLVMTargetMachine.cpp revision ac32dd9c5f1c6c6dab23a47068498c30b1d087f0 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/Analysis/LoopPass.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/GCStrategy.h"
21#include "llvm/Target/TargetOptions.h"
22#include "llvm/Target/TargetAsmInfo.h"
23#include "llvm/Transforms/Scalar.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/raw_ostream.h"
26using namespace llvm;
27
28namespace llvm {
29  bool EnableFastISel;
30}
31
32static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
33    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
34static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
35    cl::desc("Print LLVM IR input to isel pass"));
36static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
37    cl::desc("Dump emitter generated instructions as assembly"));
38static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
39    cl::desc("Dump garbage collector data"));
40static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
41    cl::desc("Verify generated machine code"),
42    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
43
44// When this works it will be on by default.
45static cl::opt<bool>
46DisablePostRAScheduler("disable-post-RA-scheduler",
47                       cl::desc("Disable scheduling after register allocation"),
48                       cl::init(true));
49
50// Enable or disable FastISel. Both options are needed, because
51// FastISel is enabled by default with -fast, and we wish to be
52// able to enable or disable fast-isel independently from -fast.
53static cl::opt<cl::boolOrDefault>
54EnableFastISelOption("fast-isel", cl::Hidden,
55  cl::desc("Enable the experimental \"fast\" instruction selector"));
56
57FileModel::Model
58LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
59                                       raw_ostream &Out,
60                                       CodeGenFileType FileType,
61                                       CodeGenOpt::Level OptLevel) {
62  // Add common CodeGen passes.
63  if (addCommonCodeGenPasses(PM, OptLevel))
64    return FileModel::Error;
65
66  // Fold redundant debug labels.
67  PM.add(createDebugLabelFoldingPass());
68
69  if (PrintMachineCode)
70    PM.add(createMachineFunctionPrinterPass(cerr));
71
72  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
73    PM.add(createMachineFunctionPrinterPass(cerr));
74
75  if (OptLevel != CodeGenOpt::None)
76    PM.add(createCodePlacementOptPass());
77
78  switch (FileType) {
79  default:
80    break;
81  case TargetMachine::AssemblyFile:
82    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
83      return FileModel::Error;
84    return FileModel::AsmFile;
85  case TargetMachine::ObjectFile:
86    if (getMachOWriterInfo())
87      return FileModel::MachOFile;
88    else if (getELFWriterInfo())
89      return FileModel::ElfFile;
90  }
91
92  return FileModel::Error;
93}
94
95/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
96/// be split up (e.g., to add an object writer pass), this method can be used to
97/// finish up adding passes to emit the file, if necessary.
98bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
99                                                  MachineCodeEmitter *MCE,
100                                                  CodeGenOpt::Level OptLevel) {
101  if (MCE)
102    addSimpleCodeEmitter(PM, OptLevel, PrintEmittedAsm, *MCE);
103
104  PM.add(createGCInfoDeleter());
105
106  // Delete machine code for this function
107  PM.add(createMachineCodeDeleter());
108
109  return false; // success!
110}
111
112/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
113/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
114/// actually outputting the machine code and resolving things like the address
115/// of functions.  This method should returns true if machine code emission is
116/// not supported.
117///
118bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
119                                                   MachineCodeEmitter &MCE,
120                                                   CodeGenOpt::Level OptLevel) {
121  // Add common CodeGen passes.
122  if (addCommonCodeGenPasses(PM, OptLevel))
123    return true;
124
125  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
126    PM.add(createMachineFunctionPrinterPass(cerr));
127
128  addCodeEmitter(PM, OptLevel, PrintEmittedAsm, MCE);
129
130  PM.add(createGCInfoDeleter());
131
132  // Delete machine code for this function
133  PM.add(createMachineCodeDeleter());
134
135  return false; // success!
136}
137
138static void printAndVerify(PassManagerBase &PM,
139                           bool allowDoubleDefs = false) {
140  if (PrintMachineCode)
141    PM.add(createMachineFunctionPrinterPass(cerr));
142
143  if (VerifyMachineCode)
144    PM.add(createMachineVerifierPass(allowDoubleDefs));
145}
146
147/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
148/// emitting to assembly files or machine code output.
149///
150bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
151                                               CodeGenOpt::Level OptLevel) {
152  // Standard LLVM-Level Passes.
153
154  // Run loop strength reduction before anything else.
155  if (OptLevel != CodeGenOpt::None) {
156    PM.add(createLoopStrengthReducePass(getTargetLowering()));
157    if (PrintLSR)
158      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
159  }
160
161  PM.add(createGCLoweringPass());
162
163  if (!getTargetAsmInfo()->doesSupportExceptionHandling())
164    PM.add(createLowerInvokePass(getTargetLowering()));
165
166  // Make sure that no unreachable blocks are instruction selected.
167  PM.add(createUnreachableBlockEliminationPass());
168
169  if (OptLevel != CodeGenOpt::None)
170    PM.add(createCodeGenPreparePass(getTargetLowering()));
171
172  PM.add(createStackProtectorPass(getTargetLowering()));
173
174  if (PrintISelInput)
175    PM.add(createPrintFunctionPass("\n\n"
176                                   "*** Final LLVM Code input to ISel ***\n",
177                                   &errs()));
178
179  // Standard Lower-Level Passes.
180
181  // Enable FastISel with -fast, but allow that to be overridden.
182  if (EnableFastISelOption == cl::BOU_TRUE ||
183      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
184    EnableFastISel = true;
185
186  // Ask the target for an isel.
187  if (addInstSelector(PM, OptLevel))
188    return true;
189
190  // Print the instruction selected machine code...
191  printAndVerify(PM, /* allowDoubleDefs= */ true);
192
193  if (OptLevel != CodeGenOpt::None) {
194    PM.add(createMachineLICMPass());
195    PM.add(createMachineSinkingPass());
196    printAndVerify(PM, /* allowDoubleDefs= */ true);
197  }
198
199  // Run pre-ra passes.
200  if (addPreRegAlloc(PM, OptLevel))
201    printAndVerify(PM);
202
203  // Perform register allocation.
204  PM.add(createRegisterAllocator());
205
206  // Perform stack slot coloring.
207  if (OptLevel != CodeGenOpt::None)
208    PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
209
210  printAndVerify(PM);           // Print the register-allocated code
211
212  // Run post-ra passes.
213  if (addPostRegAlloc(PM, OptLevel))
214    printAndVerify(PM);
215
216  PM.add(createLowerSubregsPass());
217  printAndVerify(PM);
218
219  // Insert prolog/epilog code.  Eliminate abstract frame index references...
220  PM.add(createPrologEpilogCodeInserter());
221  printAndVerify(PM);
222
223  // Second pass scheduler.
224  if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
225    PM.add(createPostRAScheduler());
226    printAndVerify(PM);
227  }
228
229  // Branch folding must be run after regalloc and prolog/epilog insertion.
230  if (OptLevel != CodeGenOpt::None) {
231    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
232    printAndVerify(PM);
233  }
234
235  PM.add(createGCMachineCodeAnalysisPass());
236  printAndVerify(PM);
237
238  if (PrintGCInfo)
239    PM.add(createGCInfoPrinter(*cerr));
240
241  return false;
242}
243