LLVMTargetMachine.cpp revision caa654136388c6b3b1909149a5d9002159983ee1 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/Passes.h"
20#include "llvm/CodeGen/GCStrategy.h"
21#include "llvm/CodeGen/MachineFunctionAnalysis.h"
22#include "llvm/Target/TargetOptions.h"
23#include "llvm/MC/MCAsmInfo.h"
24#include "llvm/Target/TargetRegistry.h"
25#include "llvm/Transforms/Scalar.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/FormattedStream.h"
28using namespace llvm;
29
30namespace llvm {
31  bool EnableFastISel;
32}
33
34static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
35    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
36static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
37    cl::desc("Print LLVM IR input to isel pass"));
38static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
39    cl::desc("Dump emitter generated instructions as assembly"));
40static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
41    cl::desc("Dump garbage collector data"));
42static cl::opt<bool> HoistConstants("hoist-constants", cl::Hidden,
43    cl::desc("Hoist constants out of loops"));
44static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
45    cl::desc("Verify generated machine code"),
46    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
47
48// Enable or disable FastISel. Both options are needed, because
49// FastISel is enabled by default with -fast, and we wish to be
50// able to enable or disable fast-isel independently from -O0.
51static cl::opt<cl::boolOrDefault>
52EnableFastISelOption("fast-isel", cl::Hidden,
53  cl::desc("Enable the \"fast\" instruction selector"));
54
55
56LLVMTargetMachine::LLVMTargetMachine(const Target &T,
57                                     const std::string &TargetTriple)
58  : TargetMachine(T) {
59  AsmInfo = T.createAsmInfo(TargetTriple);
60}
61
62
63
64FileModel::Model
65LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
66                                       formatted_raw_ostream &Out,
67                                       CodeGenFileType FileType,
68                                       CodeGenOpt::Level OptLevel) {
69  // Add common CodeGen passes.
70  if (addCommonCodeGenPasses(PM, OptLevel))
71    return FileModel::Error;
72
73  // Fold redundant debug labels.
74  PM.add(createDebugLabelFoldingPass());
75
76  if (PrintMachineCode)
77    PM.add(createMachineFunctionPrinterPass(errs()));
78
79  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
80    PM.add(createMachineFunctionPrinterPass(errs()));
81
82  if (OptLevel != CodeGenOpt::None)
83    PM.add(createCodePlacementOptPass());
84
85  switch (FileType) {
86  default:
87    break;
88  case TargetMachine::AssemblyFile:
89    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
90      return FileModel::Error;
91    return FileModel::AsmFile;
92  case TargetMachine::ObjectFile:
93    if (getMachOWriterInfo())
94      return FileModel::MachOFile;
95    else if (getELFWriterInfo())
96      return FileModel::ElfFile;
97  }
98
99  return FileModel::Error;
100}
101
102bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
103                                           CodeGenOpt::Level OptLevel,
104                                           bool Verbose,
105                                           formatted_raw_ostream &Out) {
106  FunctionPass *Printer =
107    getTarget().createAsmPrinter(Out, *this, getMCAsmInfo(), Verbose);
108  if (!Printer)
109    return true;
110
111  PM.add(Printer);
112  return false;
113}
114
115/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
116/// be split up (e.g., to add an object writer pass), this method can be used to
117/// finish up adding passes to emit the file, if necessary.
118bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
119                                                  MachineCodeEmitter *MCE,
120                                                  CodeGenOpt::Level OptLevel) {
121  if (MCE)
122    addSimpleCodeEmitter(PM, OptLevel, *MCE);
123  if (PrintEmittedAsm)
124    addAssemblyEmitter(PM, OptLevel, true, ferrs());
125
126  PM.add(createGCInfoDeleter());
127
128  return false; // success!
129}
130
131/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
132/// be split up (e.g., to add an object writer pass), this method can be used to
133/// finish up adding passes to emit the file, if necessary.
134bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
135                                                  JITCodeEmitter *JCE,
136                                                  CodeGenOpt::Level OptLevel) {
137  if (JCE)
138    addSimpleCodeEmitter(PM, OptLevel, *JCE);
139  if (PrintEmittedAsm)
140    addAssemblyEmitter(PM, OptLevel, true, ferrs());
141
142  PM.add(createGCInfoDeleter());
143
144  return false; // success!
145}
146
147/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
148/// be split up (e.g., to add an object writer pass), this method can be used to
149/// finish up adding passes to emit the file, if necessary.
150bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
151                                                  ObjectCodeEmitter *OCE,
152                                                  CodeGenOpt::Level OptLevel) {
153  if (OCE)
154    addSimpleCodeEmitter(PM, OptLevel, *OCE);
155  if (PrintEmittedAsm)
156    addAssemblyEmitter(PM, OptLevel, true, ferrs());
157
158  PM.add(createGCInfoDeleter());
159
160  return false; // success!
161}
162
163/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
164/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
165/// actually outputting the machine code and resolving things like the address
166/// of functions.  This method should returns true if machine code emission is
167/// not supported.
168///
169bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
170                                                   MachineCodeEmitter &MCE,
171                                                   CodeGenOpt::Level OptLevel) {
172  // Add common CodeGen passes.
173  if (addCommonCodeGenPasses(PM, OptLevel))
174    return true;
175
176  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
177    PM.add(createMachineFunctionPrinterPass(errs()));
178
179  addCodeEmitter(PM, OptLevel, MCE);
180  if (PrintEmittedAsm)
181    addAssemblyEmitter(PM, OptLevel, true, ferrs());
182
183  PM.add(createGCInfoDeleter());
184
185  return false; // success!
186}
187
188/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
189/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
190/// actually outputting the machine code and resolving things like the address
191/// of functions.  This method should returns true if machine code emission is
192/// not supported.
193///
194bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
195                                                   JITCodeEmitter &JCE,
196                                                   CodeGenOpt::Level OptLevel) {
197  // Add common CodeGen passes.
198  if (addCommonCodeGenPasses(PM, OptLevel))
199    return true;
200
201  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
202    PM.add(createMachineFunctionPrinterPass(errs()));
203
204  addCodeEmitter(PM, OptLevel, JCE);
205  if (PrintEmittedAsm)
206    addAssemblyEmitter(PM, OptLevel, true, ferrs());
207
208  PM.add(createGCInfoDeleter());
209
210  return false; // success!
211}
212
213static void printAndVerify(PassManagerBase &PM,
214                           bool allowDoubleDefs = false) {
215  if (PrintMachineCode)
216    PM.add(createMachineFunctionPrinterPass(errs()));
217
218  if (VerifyMachineCode)
219    PM.add(createMachineVerifierPass(allowDoubleDefs));
220}
221
222/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
223/// emitting to assembly files or machine code output.
224///
225bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
226                                               CodeGenOpt::Level OptLevel) {
227  // Standard LLVM-Level Passes.
228
229  // Run loop strength reduction before anything else.
230  if (OptLevel != CodeGenOpt::None) {
231    PM.add(createLoopStrengthReducePass(getTargetLowering()));
232    if (PrintLSR)
233      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
234  }
235
236  // Turn exception handling constructs into something the code generators can
237  // handle.
238  switch (getMCAsmInfo()->getExceptionHandlingType())
239  {
240  case ExceptionHandling::SjLj:
241    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
242    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
243    PM.add(createSjLjEHPass(getTargetLowering()));
244    break;
245  case ExceptionHandling::Dwarf:
246    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
247    break;
248  case ExceptionHandling::None:
249    PM.add(createLowerInvokePass(getTargetLowering()));
250    break;
251  }
252
253  PM.add(createGCLoweringPass());
254
255  // Make sure that no unreachable blocks are instruction selected.
256  PM.add(createUnreachableBlockEliminationPass());
257
258  if (OptLevel != CodeGenOpt::None) {
259    if (HoistConstants)
260      PM.add(createCodeGenLICMPass());
261    PM.add(createCodeGenPreparePass(getTargetLowering()));
262  }
263
264  PM.add(createStackProtectorPass(getTargetLowering()));
265
266  if (PrintISelInput)
267    PM.add(createPrintFunctionPass("\n\n"
268                                   "*** Final LLVM Code input to ISel ***\n",
269                                   &errs()));
270
271  // Standard Lower-Level Passes.
272
273  // Set up a MachineFunction for the rest of CodeGen to work on.
274  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
275
276  // Enable FastISel with -fast, but allow that to be overridden.
277  if (EnableFastISelOption == cl::BOU_TRUE ||
278      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
279    EnableFastISel = true;
280
281  // Ask the target for an isel.
282  if (addInstSelector(PM, OptLevel))
283    return true;
284
285  // Print the instruction selected machine code...
286  printAndVerify(PM, /* allowDoubleDefs= */ true);
287
288  if (OptLevel != CodeGenOpt::None) {
289    PM.add(createMachineLICMPass());
290    PM.add(createMachineSinkingPass());
291    printAndVerify(PM, /* allowDoubleDefs= */ true);
292  }
293
294  // Run pre-ra passes.
295  if (addPreRegAlloc(PM, OptLevel))
296    printAndVerify(PM, /* allowDoubleDefs= */ true);
297
298  // Perform register allocation.
299  PM.add(createRegisterAllocator());
300
301  // Perform stack slot coloring.
302  if (OptLevel != CodeGenOpt::None)
303    // FIXME: Re-enable coloring with register when it's capable of adding
304    // kill markers.
305    PM.add(createStackSlotColoringPass(false));
306
307  printAndVerify(PM);           // Print the register-allocated code
308
309  // Run post-ra passes.
310  if (addPostRegAlloc(PM, OptLevel))
311    printAndVerify(PM);
312
313  PM.add(createLowerSubregsPass());
314  printAndVerify(PM);
315
316  // Insert prolog/epilog code.  Eliminate abstract frame index references...
317  PM.add(createPrologEpilogCodeInserter());
318  printAndVerify(PM);
319
320  // Run pre-sched2 passes.
321  if (addPreSched2(PM, OptLevel))
322    printAndVerify(PM);
323
324  // Second pass scheduler.
325  if (OptLevel != CodeGenOpt::None) {
326    PM.add(createPostRAScheduler());
327    printAndVerify(PM);
328  }
329
330  // Branch folding must be run after regalloc and prolog/epilog insertion.
331  if (OptLevel != CodeGenOpt::None) {
332    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
333    printAndVerify(PM);
334  }
335
336  PM.add(createGCMachineCodeAnalysisPass());
337  printAndVerify(PM);
338
339  if (PrintGCInfo)
340    PM.add(createGCInfoPrinter(errs()));
341
342  return false;
343}
344