LLVMTargetMachine.cpp revision ef5abb43c2b98118d24f587d2aa9d6448466df72 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Pass.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/CodeGen/GCStrategy.h"
20#include "llvm/CodeGen/MachineFunctionAnalysis.h"
21#include "llvm/Target/TargetOptions.h"
22#include "llvm/Target/TargetAsmInfo.h"
23#include "llvm/Target/TargetRegistry.h"
24#include "llvm/Transforms/Scalar.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/FormattedStream.h"
27using namespace llvm;
28
29namespace llvm {
30  bool EnableFastISel;
31}
32
33static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
34    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
35static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
36    cl::desc("Print LLVM IR input to isel pass"));
37static cl::opt<bool> PrintEmittedAsm("print-emitted-asm", cl::Hidden,
38    cl::desc("Dump emitter generated instructions as assembly"));
39static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
40    cl::desc("Dump garbage collector data"));
41static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
42    cl::desc("Verify generated machine code"),
43    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
44
45// When this works it will be on by default.
46static cl::opt<bool>
47DisablePostRAScheduler("disable-post-RA-scheduler",
48                       cl::desc("Disable scheduling after register allocation"),
49                       cl::init(true));
50
51// Enable or disable FastISel. Both options are needed, because
52// FastISel is enabled by default with -fast, and we wish to be
53// able to enable or disable fast-isel independently from -fast.
54static cl::opt<cl::boolOrDefault>
55EnableFastISelOption("fast-isel", cl::Hidden,
56  cl::desc("Enable the experimental \"fast\" instruction selector"));
57
58
59LLVMTargetMachine::LLVMTargetMachine(const Target &T,
60                                     const std::string &TargetTriple)
61  : TargetMachine(T) {
62  AsmInfo = T.createAsmInfo(TargetTriple);
63}
64
65
66
67FileModel::Model
68LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
69                                       formatted_raw_ostream &Out,
70                                       CodeGenFileType FileType,
71                                       CodeGenOpt::Level OptLevel) {
72  // Add common CodeGen passes.
73  if (addCommonCodeGenPasses(PM, OptLevel))
74    return FileModel::Error;
75
76  // Fold redundant debug labels.
77  PM.add(createDebugLabelFoldingPass());
78
79  if (PrintMachineCode)
80    PM.add(createMachineFunctionPrinterPass(cerr));
81
82  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
83    PM.add(createMachineFunctionPrinterPass(cerr));
84
85  if (OptLevel != CodeGenOpt::None)
86    PM.add(createCodePlacementOptPass());
87
88  switch (FileType) {
89  default:
90    break;
91  case TargetMachine::AssemblyFile:
92    if (addAssemblyEmitter(PM, OptLevel, getAsmVerbosityDefault(), Out))
93      return FileModel::Error;
94    return FileModel::AsmFile;
95  case TargetMachine::ObjectFile:
96    if (getMachOWriterInfo())
97      return FileModel::MachOFile;
98    else if (getELFWriterInfo())
99      return FileModel::ElfFile;
100  }
101
102  return FileModel::Error;
103}
104
105bool LLVMTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
106                                           CodeGenOpt::Level OptLevel,
107                                           bool Verbose,
108                                           formatted_raw_ostream &Out) {
109  FunctionPass *Printer =
110    getTarget().createAsmPrinter(Out, *this, getTargetAsmInfo(), Verbose);
111  if (!Printer)
112    return true;
113
114  PM.add(Printer);
115  return false;
116}
117
118/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
119/// be split up (e.g., to add an object writer pass), this method can be used to
120/// finish up adding passes to emit the file, if necessary.
121bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
122                                                  MachineCodeEmitter *MCE,
123                                                  CodeGenOpt::Level OptLevel) {
124  if (MCE)
125    addSimpleCodeEmitter(PM, OptLevel, *MCE);
126  if (PrintEmittedAsm)
127    addAssemblyEmitter(PM, OptLevel, true, ferrs());
128
129  PM.add(createGCInfoDeleter());
130
131  return false; // success!
132}
133
134/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
135/// be split up (e.g., to add an object writer pass), this method can be used to
136/// finish up adding passes to emit the file, if necessary.
137bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
138                                                  JITCodeEmitter *JCE,
139                                                  CodeGenOpt::Level OptLevel) {
140  if (JCE)
141    addSimpleCodeEmitter(PM, OptLevel, *JCE);
142  if (PrintEmittedAsm)
143    addAssemblyEmitter(PM, OptLevel, true, ferrs());
144
145  PM.add(createGCInfoDeleter());
146
147  return false; // success!
148}
149
150/// addPassesToEmitFileFinish - If the passes to emit the specified file had to
151/// be split up (e.g., to add an object writer pass), this method can be used to
152/// finish up adding passes to emit the file, if necessary.
153bool LLVMTargetMachine::addPassesToEmitFileFinish(PassManagerBase &PM,
154                                                  ObjectCodeEmitter *OCE,
155                                                  CodeGenOpt::Level OptLevel) {
156  if (OCE)
157    addSimpleCodeEmitter(PM, OptLevel, *OCE);
158  if (PrintEmittedAsm)
159    addAssemblyEmitter(PM, OptLevel, true, ferrs());
160
161  PM.add(createGCInfoDeleter());
162
163  return false; // success!
164}
165
166/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
167/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
168/// actually outputting the machine code and resolving things like the address
169/// of functions.  This method should returns true if machine code emission is
170/// not supported.
171///
172bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
173                                                   MachineCodeEmitter &MCE,
174                                                   CodeGenOpt::Level OptLevel) {
175  // Add common CodeGen passes.
176  if (addCommonCodeGenPasses(PM, OptLevel))
177    return true;
178
179  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
180    PM.add(createMachineFunctionPrinterPass(cerr));
181
182  addCodeEmitter(PM, OptLevel, MCE);
183  if (PrintEmittedAsm)
184    addAssemblyEmitter(PM, OptLevel, true, ferrs());
185
186  PM.add(createGCInfoDeleter());
187
188  return false; // success!
189}
190
191/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
192/// get machine code emitted.  This uses a MachineCodeEmitter object to handle
193/// actually outputting the machine code and resolving things like the address
194/// of functions.  This method should returns true if machine code emission is
195/// not supported.
196///
197bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
198                                                   JITCodeEmitter &JCE,
199                                                   CodeGenOpt::Level OptLevel) {
200  // Add common CodeGen passes.
201  if (addCommonCodeGenPasses(PM, OptLevel))
202    return true;
203
204  if (addPreEmitPass(PM, OptLevel) && PrintMachineCode)
205    PM.add(createMachineFunctionPrinterPass(cerr));
206
207  addCodeEmitter(PM, OptLevel, JCE);
208  if (PrintEmittedAsm)
209    addAssemblyEmitter(PM, OptLevel, true, ferrs());
210
211  PM.add(createGCInfoDeleter());
212
213  return false; // success!
214}
215
216static void printAndVerify(PassManagerBase &PM,
217                           bool allowDoubleDefs = false) {
218  if (PrintMachineCode)
219    PM.add(createMachineFunctionPrinterPass(cerr));
220
221  if (VerifyMachineCode)
222    PM.add(createMachineVerifierPass(allowDoubleDefs));
223}
224
225/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
226/// emitting to assembly files or machine code output.
227///
228bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
229                                               CodeGenOpt::Level OptLevel) {
230  // Standard LLVM-Level Passes.
231
232  // Run loop strength reduction before anything else.
233  if (OptLevel != CodeGenOpt::None) {
234    PM.add(createLoopStrengthReducePass(getTargetLowering()));
235    if (PrintLSR)
236      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &errs()));
237  }
238
239  // Turn exception handling constructs into something the code generators can
240  // handle.
241  switch (getTargetAsmInfo()->getExceptionHandlingType())
242  {
243  // SjLj piggy-backs on dwarf for this bit
244  case ExceptionHandling::SjLj:
245  case ExceptionHandling::Dwarf:
246    PM.add(createDwarfEHPass(getTargetLowering(), OptLevel==CodeGenOpt::None));
247    break;
248  case ExceptionHandling::None:
249    PM.add(createLowerInvokePass(getTargetLowering()));
250    break;
251  }
252
253  PM.add(createGCLoweringPass());
254
255  // Make sure that no unreachable blocks are instruction selected.
256  PM.add(createUnreachableBlockEliminationPass());
257
258  if (OptLevel != CodeGenOpt::None)
259    PM.add(createCodeGenPreparePass(getTargetLowering()));
260
261  PM.add(createStackProtectorPass(getTargetLowering()));
262
263  if (PrintISelInput)
264    PM.add(createPrintFunctionPass("\n\n"
265                                   "*** Final LLVM Code input to ISel ***\n",
266                                   &errs()));
267
268  // Standard Lower-Level Passes.
269
270  // Set up a MachineFunction for the rest of CodeGen to work on.
271  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
272
273  // Enable FastISel with -fast, but allow that to be overridden.
274  if (EnableFastISelOption == cl::BOU_TRUE ||
275      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
276    EnableFastISel = true;
277
278  // Ask the target for an isel.
279  if (addInstSelector(PM, OptLevel))
280    return true;
281
282  // Print the instruction selected machine code...
283  printAndVerify(PM, /* allowDoubleDefs= */ true);
284
285  if (OptLevel != CodeGenOpt::None) {
286    PM.add(createMachineLICMPass());
287    PM.add(createMachineSinkingPass());
288    printAndVerify(PM, /* allowDoubleDefs= */ true);
289  }
290
291  // Run pre-ra passes.
292  if (addPreRegAlloc(PM, OptLevel))
293    printAndVerify(PM);
294
295  // Perform register allocation.
296  PM.add(createRegisterAllocator());
297
298  // Perform stack slot coloring.
299  if (OptLevel != CodeGenOpt::None)
300    // FIXME: Re-enable coloring with register when it's capable of adding
301    // kill markers.
302    PM.add(createStackSlotColoringPass(false));
303
304  printAndVerify(PM);           // Print the register-allocated code
305
306  // Run post-ra passes.
307  if (addPostRegAlloc(PM, OptLevel))
308    printAndVerify(PM);
309
310  PM.add(createLowerSubregsPass());
311  printAndVerify(PM);
312
313  // Insert prolog/epilog code.  Eliminate abstract frame index references...
314  PM.add(createPrologEpilogCodeInserter());
315  printAndVerify(PM);
316
317  // Second pass scheduler.
318  if (OptLevel != CodeGenOpt::None && !DisablePostRAScheduler) {
319    PM.add(createPostRAScheduler());
320    printAndVerify(PM);
321  }
322
323  // Branch folding must be run after regalloc and prolog/epilog insertion.
324  if (OptLevel != CodeGenOpt::None) {
325    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
326    printAndVerify(PM);
327  }
328
329  PM.add(createGCMachineCodeAnalysisPass());
330  printAndVerify(PM);
331
332  if (PrintGCInfo)
333    PM.add(createGCInfoPrinter(*cerr));
334
335  return false;
336}
337