LLVMTargetMachine.cpp revision f0b7b5f0d6afdcac071356692a80ab17488ae2ff 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Verifier.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/MachineFunctionAnalysis.h"
20#include "llvm/CodeGen/MachineModuleInfo.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/Target/TargetData.h"
27#include "llvm/Target/TargetRegistry.h"
28#include "llvm/Transforms/Scalar.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/FormattedStream.h"
33using namespace llvm;
34
35namespace llvm {
36  bool EnableFastISel;
37}
38
39static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40    cl::desc("Disable Post Regalloc"));
41static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42    cl::desc("Disable branch folding"));
43static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44    cl::desc("Disable tail duplication"));
45static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46    cl::desc("Disable pre-register allocation tail duplication"));
47static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48    cl::desc("Disable code placement"));
49static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50    cl::desc("Disable Stack Slot Coloring"));
51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52    cl::desc("Disable Machine LICM"));
53static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
54    cl::Hidden,
55    cl::desc("Disable Machine LICM"));
56static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
57    cl::desc("Disable Machine Sinking"));
58static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
59    cl::desc("Disable Loop Strength Reduction Pass"));
60static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
61    cl::desc("Disable Codegen Prepare"));
62static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
63    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
64static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
65    cl::desc("Print LLVM IR input to isel pass"));
66static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
67    cl::desc("Dump garbage collector data"));
68static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
69    cl::desc("Show encoding in .s output"));
70static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
71    cl::desc("Show instruction structure in .s output"));
72static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
73    cl::desc("Enable MC API logging"));
74static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
75    cl::desc("Verify generated machine code"),
76    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
77// Enabled or disable local stack object block allocation. This is an
78// experimental pass that allocates locals relative to one another before
79// register allocation and then assigns them to actual stack slots as a block
80// later in PEI. This will eventually allow targets with limited index offset
81// range to allocate additional base registers (not just FP and SP) to
82// more efficiently reference locals, as well as handle situations where
83// locals cannot be referenced via SP or FP at all (dynamic stack realignment
84// together with variable sized objects, for example).
85cl::opt<bool> EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(false),
86    cl::Hidden, cl::desc("Enable pre-regalloc stack frame index allocation"));
87
88static cl::opt<cl::boolOrDefault>
89AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
90           cl::init(cl::BOU_UNSET));
91
92static bool getVerboseAsm() {
93  switch (AsmVerbose) {
94  default:
95  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
96  case cl::BOU_TRUE:  return true;
97  case cl::BOU_FALSE: return false;
98  }
99}
100
101// Enable or disable FastISel. Both options are needed, because
102// FastISel is enabled by default with -fast, and we wish to be
103// able to enable or disable fast-isel independently from -O0.
104static cl::opt<cl::boolOrDefault>
105EnableFastISelOption("fast-isel", cl::Hidden,
106  cl::desc("Enable the \"fast\" instruction selector"));
107
108// Enable or disable an experimental optimization to split GEPs
109// and run a special GVN pass which does not examine loads, in
110// an effort to factor out redundancy implicit in complex GEPs.
111static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
112    cl::desc("Split GEPs and run no-load GVN"));
113
114LLVMTargetMachine::LLVMTargetMachine(const Target &T,
115                                     const std::string &Triple)
116  : TargetMachine(T), TargetTriple(Triple) {
117  AsmInfo = T.createAsmInfo(TargetTriple);
118}
119
120// Set the default code model for the JIT for a generic target.
121// FIXME: Is small right here? or .is64Bit() ? Large : Small?
122void LLVMTargetMachine::setCodeModelForJIT() {
123  setCodeModel(CodeModel::Small);
124}
125
126// Set the default code model for static compilation for a generic target.
127void LLVMTargetMachine::setCodeModelForStatic() {
128  setCodeModel(CodeModel::Small);
129}
130
131bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
132                                            formatted_raw_ostream &Out,
133                                            CodeGenFileType FileType,
134                                            CodeGenOpt::Level OptLevel,
135                                            bool DisableVerify) {
136  // Add common CodeGen passes.
137  MCContext *Context = 0;
138  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
139    return true;
140  assert(Context != 0 && "Failed to get MCContext");
141
142  const MCAsmInfo &MAI = *getMCAsmInfo();
143  OwningPtr<MCStreamer> AsmStreamer;
144
145  switch (FileType) {
146  default: return true;
147  case CGFT_AssemblyFile: {
148    MCInstPrinter *InstPrinter =
149      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
150
151    // Create a code emitter if asked to show the encoding.
152    MCCodeEmitter *MCE = 0;
153    if (ShowMCEncoding)
154      MCE = getTarget().createCodeEmitter(*this, *Context);
155
156    AsmStreamer.reset(createAsmStreamer(*Context, Out,
157                                        getTargetData()->isLittleEndian(),
158                                        getVerboseAsm(), InstPrinter,
159                                        MCE, ShowMCInst));
160    break;
161  }
162  case CGFT_ObjectFile: {
163    // Create the code emitter for the target if it exists.  If not, .o file
164    // emission fails.
165    MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
166    TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
167    if (MCE == 0 || TAB == 0)
168      return true;
169
170    AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
171                                                       *TAB, Out, MCE,
172                                                       hasMCRelaxAll()));
173    break;
174  }
175  case CGFT_Null:
176    // The Null output is intended for use for performance analysis and testing,
177    // not real users.
178    AsmStreamer.reset(createNullStreamer(*Context));
179    break;
180  }
181
182  if (EnableMCLogging)
183    AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
184
185  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
186  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
187  if (Printer == 0)
188    return true;
189
190  // If successful, createAsmPrinter took ownership of AsmStreamer.
191  AsmStreamer.take();
192
193  PM.add(Printer);
194
195  // Make sure the code model is set.
196  setCodeModelForStatic();
197  PM.add(createGCInfoDeleter());
198  return false;
199}
200
201/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
202/// get machine code emitted.  This uses a JITCodeEmitter object to handle
203/// actually outputting the machine code and resolving things like the address
204/// of functions.  This method should returns true if machine code emission is
205/// not supported.
206///
207bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
208                                                   JITCodeEmitter &JCE,
209                                                   CodeGenOpt::Level OptLevel,
210                                                   bool DisableVerify) {
211  // Make sure the code model is set.
212  setCodeModelForJIT();
213
214  // Add common CodeGen passes.
215  MCContext *Ctx = 0;
216  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
217    return true;
218
219  addCodeEmitter(PM, OptLevel, JCE);
220  PM.add(createGCInfoDeleter());
221
222  return false; // success!
223}
224
225/// addPassesToEmitMC - Add passes to the specified pass manager to get
226/// machine code emitted with the MCJIT. This method returns true if machine
227/// code is not supported. It fills the MCContext Ctx pointer which can be
228/// used to build custom MCStreamer.
229///
230bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
231                                          MCContext *&Ctx,
232                                          CodeGenOpt::Level OptLevel,
233                                          bool DisableVerify) {
234  // Add common CodeGen passes.
235  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
236    return true;
237  // Make sure the code model is set.
238  setCodeModelForJIT();
239
240  return false; // success!
241}
242
243static void printNoVerify(PassManagerBase &PM, const char *Banner) {
244  if (PrintMachineCode)
245    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
246}
247
248static void printAndVerify(PassManagerBase &PM,
249                           const char *Banner) {
250  if (PrintMachineCode)
251    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
252
253  if (VerifyMachineCode)
254    PM.add(createMachineVerifierPass());
255}
256
257/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
258/// emitting to assembly files or machine code output.
259///
260bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
261                                               CodeGenOpt::Level OptLevel,
262                                               bool DisableVerify,
263                                               MCContext *&OutContext) {
264  // Standard LLVM-Level Passes.
265
266  // Before running any passes, run the verifier to determine if the input
267  // coming from the front-end and/or optimizer is valid.
268  if (!DisableVerify)
269    PM.add(createVerifierPass());
270
271  // Optionally, tun split-GEPs and no-load GVN.
272  if (EnableSplitGEPGVN) {
273    PM.add(createGEPSplitterPass());
274    PM.add(createGVNPass(/*NoLoads=*/true));
275  }
276
277  // Run loop strength reduction before anything else.
278  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
279    PM.add(createLoopStrengthReducePass(getTargetLowering()));
280    if (PrintLSR)
281      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
282  }
283
284  PM.add(createGCLoweringPass());
285
286  // Make sure that no unreachable blocks are instruction selected.
287  PM.add(createUnreachableBlockEliminationPass());
288
289  // Turn exception handling constructs into something the code generators can
290  // handle.
291  switch (getMCAsmInfo()->getExceptionHandlingType()) {
292  case ExceptionHandling::SjLj:
293    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
294    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
295    // catch info can get misplaced when a selector ends up more than one block
296    // removed from the parent invoke(s). This could happen when a landing
297    // pad is shared by multiple invokes and is also a target of a normal
298    // edge from elsewhere.
299    PM.add(createSjLjEHPass(getTargetLowering()));
300    // FALLTHROUGH
301  case ExceptionHandling::Dwarf:
302    PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
303    break;
304  case ExceptionHandling::None:
305    PM.add(createLowerInvokePass(getTargetLowering()));
306
307    // The lower invoke pass may create unreachable code. Remove it.
308    PM.add(createUnreachableBlockEliminationPass());
309    break;
310  }
311
312  if (OptLevel != CodeGenOpt::None && !DisableCGP)
313    PM.add(createCodeGenPreparePass(getTargetLowering()));
314
315  PM.add(createStackProtectorPass(getTargetLowering()));
316
317  addPreISel(PM, OptLevel);
318
319  if (PrintISelInput)
320    PM.add(createPrintFunctionPass("\n\n"
321                                   "*** Final LLVM Code input to ISel ***\n",
322                                   &dbgs()));
323
324  // All passes which modify the LLVM IR are now complete; run the verifier
325  // to ensure that the IR is valid.
326  if (!DisableVerify)
327    PM.add(createVerifierPass());
328
329  // Standard Lower-Level Passes.
330
331  // Install a MachineModuleInfo class, which is an immutable pass that holds
332  // all the per-module stuff we're generating, including MCContext.
333  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo());
334  PM.add(MMI);
335  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
336
337  // Set up a MachineFunction for the rest of CodeGen to work on.
338  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
339
340  // Enable FastISel with -fast, but allow that to be overridden.
341  if (EnableFastISelOption == cl::BOU_TRUE ||
342      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
343    EnableFastISel = true;
344
345  // Ask the target for an isel.
346  if (addInstSelector(PM, OptLevel))
347    return true;
348
349  // Print the instruction selected machine code...
350  printAndVerify(PM, "After Instruction Selection");
351
352  // Optimize PHIs before DCE: removing dead PHI cycles may make more
353  // instructions dead.
354  if (OptLevel != CodeGenOpt::None)
355    PM.add(createOptimizePHIsPass());
356
357  // Assign local variables to stack slots relative to one another and simplify
358  // frame index references where possible. Final stack slot locations will be
359  // assigned in PEI.
360  if (EnableLocalStackAlloc)
361    PM.add(createLocalStackSlotAllocationPass());
362
363  if (OptLevel != CodeGenOpt::None) {
364    // With optimization, dead code should already be eliminated. However
365    // there is one known exception: lowered code for arguments that are only
366    // used by tail calls, where the tail calls reuse the incoming stack
367    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
368    PM.add(createDeadMachineInstructionElimPass());
369    printAndVerify(PM, "After codegen DCE pass");
370
371    PM.add(createPeepholeOptimizerPass());
372    if (!DisableMachineLICM)
373      PM.add(createMachineLICMPass());
374    PM.add(createMachineCSEPass());
375    if (!DisableMachineSink)
376      PM.add(createMachineSinkingPass());
377    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
378  }
379
380  // Pre-ra tail duplication.
381  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
382    PM.add(createTailDuplicatePass(true));
383    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
384  }
385
386  // Run pre-ra passes.
387  if (addPreRegAlloc(PM, OptLevel))
388    printAndVerify(PM, "After PreRegAlloc passes");
389
390  // Perform register allocation.
391  PM.add(createRegisterAllocator(OptLevel));
392  printAndVerify(PM, "After Register Allocation");
393
394  // Perform stack slot coloring and post-ra machine LICM.
395  if (OptLevel != CodeGenOpt::None) {
396    // FIXME: Re-enable coloring with register when it's capable of adding
397    // kill markers.
398    if (!DisableSSC)
399      PM.add(createStackSlotColoringPass(false));
400
401    // Run post-ra machine LICM to hoist reloads / remats.
402    if (!DisablePostRAMachineLICM)
403      PM.add(createMachineLICMPass(false));
404
405    printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
406  }
407
408  // Run post-ra passes.
409  if (addPostRegAlloc(PM, OptLevel))
410    printAndVerify(PM, "After PostRegAlloc passes");
411
412  PM.add(createLowerSubregsPass());
413  printAndVerify(PM, "After LowerSubregs");
414
415  // Insert prolog/epilog code.  Eliminate abstract frame index references...
416  PM.add(createPrologEpilogCodeInserter());
417  printAndVerify(PM, "After PrologEpilogCodeInserter");
418
419  // Run pre-sched2 passes.
420  if (addPreSched2(PM, OptLevel))
421    printAndVerify(PM, "After PreSched2 passes");
422
423  // Second pass scheduler.
424  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
425    PM.add(createPostRAScheduler(OptLevel));
426    printAndVerify(PM, "After PostRAScheduler");
427  }
428
429  // Branch folding must be run after regalloc and prolog/epilog insertion.
430  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
431    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
432    printNoVerify(PM, "After BranchFolding");
433  }
434
435  // Tail duplication.
436  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
437    PM.add(createTailDuplicatePass(false));
438    printNoVerify(PM, "After TailDuplicate");
439  }
440
441  PM.add(createGCMachineCodeAnalysisPass());
442
443  if (PrintGCInfo)
444    PM.add(createGCInfoPrinter(dbgs()));
445
446  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
447    PM.add(createCodePlacementOptPass());
448    printNoVerify(PM, "After CodePlacementOpt");
449  }
450
451  if (addPreEmitPass(PM, OptLevel))
452    printNoVerify(PM, "After PreEmit passes");
453
454  return false;
455}
456