LLVMTargetMachine.cpp revision f59514152511694d46ca8b8d2db466d256ab5759 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Verifier.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/MachineFunctionAnalysis.h"
20#include "llvm/CodeGen/MachineModuleInfo.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/Target/TargetData.h"
27#include "llvm/Target/TargetRegistry.h"
28#include "llvm/Transforms/Scalar.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/FormattedStream.h"
33using namespace llvm;
34
35namespace llvm {
36  bool EnableFastISel;
37}
38
39static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40    cl::desc("Disable Post Regalloc"));
41static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42    cl::desc("Disable branch folding"));
43static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44    cl::desc("Disable tail duplication"));
45static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46    cl::desc("Disable pre-register allocation tail duplication"));
47static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48    cl::desc("Disable code placement"));
49static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50    cl::desc("Disable Stack Slot Coloring"));
51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52    cl::desc("Disable Machine LICM"));
53static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
54    cl::Hidden,
55    cl::desc("Disable Machine LICM"));
56static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
57    cl::desc("Disable Machine Sinking"));
58static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
59    cl::desc("Disable Loop Strength Reduction Pass"));
60static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
61    cl::desc("Disable Codegen Prepare"));
62static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
63    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
64static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
65    cl::desc("Print LLVM IR input to isel pass"));
66static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
67    cl::desc("Dump garbage collector data"));
68static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
69    cl::desc("Show encoding in .s output"));
70static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
71    cl::desc("Show instruction structure in .s output"));
72static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
73    cl::desc("Enable MC API logging"));
74static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
75    cl::desc("Verify generated machine code"),
76    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
77
78static cl::opt<cl::boolOrDefault>
79AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
80           cl::init(cl::BOU_UNSET));
81
82static bool getVerboseAsm() {
83  switch (AsmVerbose) {
84  default:
85  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
86  case cl::BOU_TRUE:  return true;
87  case cl::BOU_FALSE: return false;
88  }
89}
90
91// Enable or disable FastISel. Both options are needed, because
92// FastISel is enabled by default with -fast, and we wish to be
93// able to enable or disable fast-isel independently from -O0.
94static cl::opt<cl::boolOrDefault>
95EnableFastISelOption("fast-isel", cl::Hidden,
96  cl::desc("Enable the \"fast\" instruction selector"));
97
98// Enable or disable an experimental optimization to split GEPs
99// and run a special GVN pass which does not examine loads, in
100// an effort to factor out redundancy implicit in complex GEPs.
101static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
102    cl::desc("Split GEPs and run no-load GVN"));
103
104LLVMTargetMachine::LLVMTargetMachine(const Target &T,
105                                     const std::string &Triple)
106  : TargetMachine(T), TargetTriple(Triple) {
107  AsmInfo = T.createAsmInfo(TargetTriple);
108}
109
110// Set the default code model for the JIT for a generic target.
111// FIXME: Is small right here? or .is64Bit() ? Large : Small?
112void LLVMTargetMachine::setCodeModelForJIT() {
113  setCodeModel(CodeModel::Small);
114}
115
116// Set the default code model for static compilation for a generic target.
117void LLVMTargetMachine::setCodeModelForStatic() {
118  setCodeModel(CodeModel::Small);
119}
120
121bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
122                                            formatted_raw_ostream &Out,
123                                            CodeGenFileType FileType,
124                                            CodeGenOpt::Level OptLevel,
125                                            bool DisableVerify) {
126  // Add common CodeGen passes.
127  MCContext *Context = 0;
128  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
129    return true;
130  assert(Context != 0 && "Failed to get MCContext");
131
132  const MCAsmInfo &MAI = *getMCAsmInfo();
133  OwningPtr<MCStreamer> AsmStreamer;
134
135  switch (FileType) {
136  default: return true;
137  case CGFT_AssemblyFile: {
138    MCInstPrinter *InstPrinter =
139      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
140
141    // Create a code emitter if asked to show the encoding.
142    //
143    // FIXME: These are currently leaked.
144    MCCodeEmitter *MCE = 0;
145    if (ShowMCEncoding)
146      MCE = getTarget().createCodeEmitter(*this, *Context);
147
148    AsmStreamer.reset(createAsmStreamer(*Context, Out,
149                                        getTargetData()->isLittleEndian(),
150                                        getVerboseAsm(), InstPrinter,
151                                        MCE, ShowMCInst));
152    break;
153  }
154  case CGFT_ObjectFile: {
155    // Create the code emitter for the target if it exists.  If not, .o file
156    // emission fails.
157    //
158    // FIXME: These are currently leaked.
159    MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
160    TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
161    if (MCE == 0 || TAB == 0)
162      return true;
163
164    AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
165                                                       *TAB, Out, MCE,
166                                                       hasMCRelaxAll()));
167    break;
168  }
169  case CGFT_Null:
170    // The Null output is intended for use for performance analysis and testing,
171    // not real users.
172    AsmStreamer.reset(createNullStreamer(*Context));
173    break;
174  }
175
176  if (EnableMCLogging)
177    AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
178
179  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
180  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
181  if (Printer == 0)
182    return true;
183
184  // If successful, createAsmPrinter took ownership of AsmStreamer.
185  AsmStreamer.take();
186
187  PM.add(Printer);
188
189  // Make sure the code model is set.
190  setCodeModelForStatic();
191  PM.add(createGCInfoDeleter());
192  return false;
193}
194
195/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
196/// get machine code emitted.  This uses a JITCodeEmitter object to handle
197/// actually outputting the machine code and resolving things like the address
198/// of functions.  This method should returns true if machine code emission is
199/// not supported.
200///
201bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
202                                                   JITCodeEmitter &JCE,
203                                                   CodeGenOpt::Level OptLevel,
204                                                   bool DisableVerify) {
205  // Make sure the code model is set.
206  setCodeModelForJIT();
207
208  // Add common CodeGen passes.
209  MCContext *Ctx = 0;
210  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
211    return true;
212
213  addCodeEmitter(PM, OptLevel, JCE);
214  PM.add(createGCInfoDeleter());
215
216  return false; // success!
217}
218
219static void printNoVerify(PassManagerBase &PM, const char *Banner) {
220  if (PrintMachineCode)
221    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
222}
223
224static void printAndVerify(PassManagerBase &PM,
225                           const char *Banner,
226                           bool allowDoubleDefs = false) {
227  if (PrintMachineCode)
228    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
229
230  if (VerifyMachineCode)
231    PM.add(createMachineVerifierPass(allowDoubleDefs));
232}
233
234/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
235/// emitting to assembly files or machine code output.
236///
237bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
238                                               CodeGenOpt::Level OptLevel,
239                                               bool DisableVerify,
240                                               MCContext *&OutContext) {
241  // Standard LLVM-Level Passes.
242
243  // Before running any passes, run the verifier to determine if the input
244  // coming from the front-end and/or optimizer is valid.
245  if (!DisableVerify)
246    PM.add(createVerifierPass());
247
248  // Optionally, tun split-GEPs and no-load GVN.
249  if (EnableSplitGEPGVN) {
250    PM.add(createGEPSplitterPass());
251    PM.add(createGVNPass(/*NoLoads=*/true));
252  }
253
254  // Run loop strength reduction before anything else.
255  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
256    PM.add(createLoopStrengthReducePass(getTargetLowering()));
257    if (PrintLSR)
258      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
259  }
260
261  // Turn exception handling constructs into something the code generators can
262  // handle.
263  switch (getMCAsmInfo()->getExceptionHandlingType()) {
264  case ExceptionHandling::SjLj:
265    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
266    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
267    // catch info can get misplaced when a selector ends up more than one block
268    // removed from the parent invoke(s). This could happen when a landing
269    // pad is shared by multiple invokes and is also a target of a normal
270    // edge from elsewhere.
271    PM.add(createSjLjEHPass(getTargetLowering()));
272    PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
273    break;
274  case ExceptionHandling::Dwarf:
275    PM.add(createDwarfEHPass(this, OptLevel==CodeGenOpt::None));
276    break;
277  case ExceptionHandling::None:
278    PM.add(createLowerInvokePass(getTargetLowering()));
279    break;
280  }
281
282  PM.add(createGCLoweringPass());
283
284  // Make sure that no unreachable blocks are instruction selected.
285  PM.add(createUnreachableBlockEliminationPass());
286
287  if (OptLevel != CodeGenOpt::None && !DisableCGP)
288    PM.add(createCodeGenPreparePass(getTargetLowering()));
289
290  PM.add(createStackProtectorPass(getTargetLowering()));
291
292  if (PrintISelInput)
293    PM.add(createPrintFunctionPass("\n\n"
294                                   "*** Final LLVM Code input to ISel ***\n",
295                                   &dbgs()));
296
297  // All passes which modify the LLVM IR are now complete; run the verifier
298  // to ensure that the IR is valid.
299  if (!DisableVerify)
300    PM.add(createVerifierPass());
301
302  // Standard Lower-Level Passes.
303
304  // Install a MachineModuleInfo class, which is an immutable pass that holds
305  // all the per-module stuff we're generating, including MCContext.
306  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo());
307  PM.add(MMI);
308  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
309
310
311  // Set up a MachineFunction for the rest of CodeGen to work on.
312  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
313
314  // Enable FastISel with -fast, but allow that to be overridden.
315  if (EnableFastISelOption == cl::BOU_TRUE ||
316      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
317    EnableFastISel = true;
318
319  // Ask the target for an isel.
320  if (addInstSelector(PM, OptLevel))
321    return true;
322
323  // Print the instruction selected machine code...
324  printAndVerify(PM, "After Instruction Selection",
325                 /* allowDoubleDefs= */ true);
326
327  // Optimize PHIs before DCE: removing dead PHI cycles may make more
328  // instructions dead.
329  if (OptLevel != CodeGenOpt::None)
330    PM.add(createOptimizePHIsPass());
331
332  // Delete dead machine instructions regardless of optimization level.
333  //
334  // At -O0, fast-isel frequently creates dead instructions.
335  //
336  // With optimization, dead code should already be eliminated. However
337  // there is one known exception: lowered code for arguments that are only
338  // used by tail calls, where the tail calls reuse the incoming stack
339  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
340  PM.add(createDeadMachineInstructionElimPass());
341  printAndVerify(PM, "After codegen DCE pass",
342                 /* allowDoubleDefs= */ true);
343
344  if (OptLevel != CodeGenOpt::None) {
345    PM.add(createOptimizeExtsPass());
346    if (!DisableMachineLICM)
347      PM.add(createMachineLICMPass());
348    PM.add(createMachineCSEPass());
349    if (!DisableMachineSink)
350      PM.add(createMachineSinkingPass());
351    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes",
352                   /* allowDoubleDefs= */ true);
353  }
354
355  // Pre-ra tail duplication.
356  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
357    PM.add(createTailDuplicatePass(true));
358    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate",
359                   /* allowDoubleDefs= */ true);
360  }
361
362  // Run pre-ra passes.
363  if (addPreRegAlloc(PM, OptLevel))
364    printAndVerify(PM, "After PreRegAlloc passes",
365                   /* allowDoubleDefs= */ true);
366
367  // Perform register allocation.
368  PM.add(createRegisterAllocator(OptLevel));
369  printAndVerify(PM, "After Register Allocation");
370
371  // Perform stack slot coloring and post-ra machine LICM.
372  if (OptLevel != CodeGenOpt::None) {
373    // FIXME: Re-enable coloring with register when it's capable of adding
374    // kill markers.
375    if (!DisableSSC)
376      PM.add(createStackSlotColoringPass(false));
377
378    // Run post-ra machine LICM to hoist reloads / remats.
379    if (!DisablePostRAMachineLICM)
380      PM.add(createMachineLICMPass(false));
381
382    printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
383  }
384
385  // Run post-ra passes.
386  if (addPostRegAlloc(PM, OptLevel))
387    printAndVerify(PM, "After PostRegAlloc passes");
388
389  PM.add(createLowerSubregsPass());
390  printAndVerify(PM, "After LowerSubregs");
391
392  // Insert prolog/epilog code.  Eliminate abstract frame index references...
393  PM.add(createPrologEpilogCodeInserter());
394  printAndVerify(PM, "After PrologEpilogCodeInserter");
395
396  // Run pre-sched2 passes.
397  if (addPreSched2(PM, OptLevel))
398    printAndVerify(PM, "After PreSched2 passes");
399
400  // Second pass scheduler.
401  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
402    PM.add(createPostRAScheduler(OptLevel));
403    printAndVerify(PM, "After PostRAScheduler");
404  }
405
406  // Branch folding must be run after regalloc and prolog/epilog insertion.
407  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
408    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
409    printNoVerify(PM, "After BranchFolding");
410  }
411
412  // Tail duplication.
413  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
414    PM.add(createTailDuplicatePass(false));
415    printNoVerify(PM, "After TailDuplicate");
416  }
417
418  PM.add(createGCMachineCodeAnalysisPass());
419
420  if (PrintGCInfo)
421    PM.add(createGCInfoPrinter(dbgs()));
422
423  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
424    PM.add(createCodePlacementOptPass());
425    printNoVerify(PM, "After CodePlacementOpt");
426  }
427
428  if (addPreEmitPass(PM, OptLevel))
429    printNoVerify(PM, "After PreEmit passes");
430
431  return false;
432}
433