LLVMTargetMachine.cpp revision ff9dfedd101e1a591ec8f7fac9999777cde80efb 
1//===-- LLVMTargetMachine.cpp - Implement the LLVMTargetMachine class -----===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LLVMTargetMachine class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetMachine.h"
15#include "llvm/PassManager.h"
16#include "llvm/Analysis/Verifier.h"
17#include "llvm/Assembly/PrintModulePass.h"
18#include "llvm/CodeGen/AsmPrinter.h"
19#include "llvm/CodeGen/MachineFunctionAnalysis.h"
20#include "llvm/CodeGen/MachineModuleInfo.h"
21#include "llvm/CodeGen/GCStrategy.h"
22#include "llvm/CodeGen/Passes.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/MC/MCAsmInfo.h"
25#include "llvm/MC/MCStreamer.h"
26#include "llvm/Target/TargetData.h"
27#include "llvm/Target/TargetRegistry.h"
28#include "llvm/Transforms/Scalar.h"
29#include "llvm/ADT/OwningPtr.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/FormattedStream.h"
33using namespace llvm;
34
35namespace llvm {
36  bool EnableFastISel;
37}
38
39static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
40    cl::desc("Disable Post Regalloc"));
41static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
42    cl::desc("Disable branch folding"));
43static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
44    cl::desc("Disable tail duplication"));
45static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
46    cl::desc("Disable pre-register allocation tail duplication"));
47static cl::opt<bool> DisableCodePlace("disable-code-place", cl::Hidden,
48    cl::desc("Disable code placement"));
49static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
50    cl::desc("Disable Stack Slot Coloring"));
51static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52    cl::desc("Disable Machine LICM"));
53static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
54    cl::Hidden,
55    cl::desc("Disable Machine LICM"));
56static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
57    cl::desc("Disable Machine Sinking"));
58static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
59    cl::desc("Disable Loop Strength Reduction Pass"));
60static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
61    cl::desc("Disable Codegen Prepare"));
62static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
63    cl::desc("Print LLVM IR produced by the loop-reduce pass"));
64static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
65    cl::desc("Print LLVM IR input to isel pass"));
66static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
67    cl::desc("Dump garbage collector data"));
68static cl::opt<bool> ShowMCEncoding("show-mc-encoding", cl::Hidden,
69    cl::desc("Show encoding in .s output"));
70static cl::opt<bool> ShowMCInst("show-mc-inst", cl::Hidden,
71    cl::desc("Show instruction structure in .s output"));
72static cl::opt<bool> EnableMCLogging("enable-mc-api-logging", cl::Hidden,
73    cl::desc("Enable MC API logging"));
74static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
75    cl::desc("Verify generated machine code"),
76    cl::init(getenv("LLVM_VERIFY_MACHINEINSTRS")!=NULL));
77
78static cl::opt<cl::boolOrDefault>
79AsmVerbose("asm-verbose", cl::desc("Add comments to directives."),
80           cl::init(cl::BOU_UNSET));
81
82static bool getVerboseAsm() {
83  switch (AsmVerbose) {
84  default:
85  case cl::BOU_UNSET: return TargetMachine::getAsmVerbosityDefault();
86  case cl::BOU_TRUE:  return true;
87  case cl::BOU_FALSE: return false;
88  }
89}
90
91// Enable or disable FastISel. Both options are needed, because
92// FastISel is enabled by default with -fast, and we wish to be
93// able to enable or disable fast-isel independently from -O0.
94static cl::opt<cl::boolOrDefault>
95EnableFastISelOption("fast-isel", cl::Hidden,
96  cl::desc("Enable the \"fast\" instruction selector"));
97
98// Enable or disable an experimental optimization to split GEPs
99// and run a special GVN pass which does not examine loads, in
100// an effort to factor out redundancy implicit in complex GEPs.
101static cl::opt<bool> EnableSplitGEPGVN("split-gep-gvn", cl::Hidden,
102    cl::desc("Split GEPs and run no-load GVN"));
103
104LLVMTargetMachine::LLVMTargetMachine(const Target &T,
105                                     const std::string &Triple)
106  : TargetMachine(T), TargetTriple(Triple) {
107  AsmInfo = T.createAsmInfo(TargetTriple);
108}
109
110// Set the default code model for the JIT for a generic target.
111// FIXME: Is small right here? or .is64Bit() ? Large : Small?
112void LLVMTargetMachine::setCodeModelForJIT() {
113  setCodeModel(CodeModel::Small);
114}
115
116// Set the default code model for static compilation for a generic target.
117void LLVMTargetMachine::setCodeModelForStatic() {
118  setCodeModel(CodeModel::Small);
119}
120
121bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
122                                            formatted_raw_ostream &Out,
123                                            CodeGenFileType FileType,
124                                            CodeGenOpt::Level OptLevel,
125                                            bool DisableVerify) {
126  // Add common CodeGen passes.
127  MCContext *Context = 0;
128  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context))
129    return true;
130  assert(Context != 0 && "Failed to get MCContext");
131
132  const MCAsmInfo &MAI = *getMCAsmInfo();
133  OwningPtr<MCStreamer> AsmStreamer;
134
135  switch (FileType) {
136  default: return true;
137  case CGFT_AssemblyFile: {
138    MCInstPrinter *InstPrinter =
139      getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI);
140
141    // Create a code emitter if asked to show the encoding.
142    MCCodeEmitter *MCE = 0;
143    if (ShowMCEncoding)
144      MCE = getTarget().createCodeEmitter(*this, *Context);
145
146    AsmStreamer.reset(createAsmStreamer(*Context, Out,
147                                        getTargetData()->isLittleEndian(),
148                                        getVerboseAsm(), InstPrinter,
149                                        MCE, ShowMCInst));
150    break;
151  }
152  case CGFT_ObjectFile: {
153    // Create the code emitter for the target if it exists.  If not, .o file
154    // emission fails.
155    MCCodeEmitter *MCE = getTarget().createCodeEmitter(*this, *Context);
156    TargetAsmBackend *TAB = getTarget().createAsmBackend(TargetTriple);
157    if (MCE == 0 || TAB == 0)
158      return true;
159
160    AsmStreamer.reset(getTarget().createObjectStreamer(TargetTriple, *Context,
161                                                       *TAB, Out, MCE,
162                                                       hasMCRelaxAll()));
163    AsmStreamer.get()->InitSections();
164    break;
165  }
166  case CGFT_Null:
167    // The Null output is intended for use for performance analysis and testing,
168    // not real users.
169    AsmStreamer.reset(createNullStreamer(*Context));
170    break;
171  }
172
173  if (EnableMCLogging)
174    AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs()));
175
176  // Create the AsmPrinter, which takes ownership of AsmStreamer if successful.
177  FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer);
178  if (Printer == 0)
179    return true;
180
181  // If successful, createAsmPrinter took ownership of AsmStreamer.
182  AsmStreamer.take();
183
184  PM.add(Printer);
185
186  // Make sure the code model is set.
187  setCodeModelForStatic();
188  PM.add(createGCInfoDeleter());
189  return false;
190}
191
192/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
193/// get machine code emitted.  This uses a JITCodeEmitter object to handle
194/// actually outputting the machine code and resolving things like the address
195/// of functions.  This method should returns true if machine code emission is
196/// not supported.
197///
198bool LLVMTargetMachine::addPassesToEmitMachineCode(PassManagerBase &PM,
199                                                   JITCodeEmitter &JCE,
200                                                   CodeGenOpt::Level OptLevel,
201                                                   bool DisableVerify) {
202  // Make sure the code model is set.
203  setCodeModelForJIT();
204
205  // Add common CodeGen passes.
206  MCContext *Ctx = 0;
207  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
208    return true;
209
210  addCodeEmitter(PM, OptLevel, JCE);
211  PM.add(createGCInfoDeleter());
212
213  return false; // success!
214}
215
216/// addPassesToEmitMC - Add passes to the specified pass manager to get
217/// machine code emitted with the MCJIT. This method returns true if machine
218/// code is not supported. It fills the MCContext Ctx pointer which can be
219/// used to build custom MCStreamer.
220///
221bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM,
222                                          MCContext *&Ctx,
223                                          CodeGenOpt::Level OptLevel,
224                                          bool DisableVerify) {
225  // Add common CodeGen passes.
226  if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Ctx))
227    return true;
228  // Make sure the code model is set.
229  setCodeModelForJIT();
230
231  return false; // success!
232}
233
234static void printNoVerify(PassManagerBase &PM, const char *Banner) {
235  if (PrintMachineCode)
236    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
237}
238
239static void printAndVerify(PassManagerBase &PM,
240                           const char *Banner) {
241  if (PrintMachineCode)
242    PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
243
244  if (VerifyMachineCode)
245    PM.add(createMachineVerifierPass());
246}
247
248/// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
249/// emitting to assembly files or machine code output.
250///
251bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
252                                               CodeGenOpt::Level OptLevel,
253                                               bool DisableVerify,
254                                               MCContext *&OutContext) {
255  // Standard LLVM-Level Passes.
256
257  // Before running any passes, run the verifier to determine if the input
258  // coming from the front-end and/or optimizer is valid.
259  if (!DisableVerify)
260    PM.add(createVerifierPass());
261
262  // Optionally, tun split-GEPs and no-load GVN.
263  if (EnableSplitGEPGVN) {
264    PM.add(createGEPSplitterPass());
265    PM.add(createGVNPass(/*NoLoads=*/true));
266  }
267
268  // Run loop strength reduction before anything else.
269  if (OptLevel != CodeGenOpt::None && !DisableLSR) {
270    PM.add(createLoopStrengthReducePass(getTargetLowering()));
271    if (PrintLSR)
272      PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
273  }
274
275  PM.add(createGCLoweringPass());
276
277  // Make sure that no unreachable blocks are instruction selected.
278  PM.add(createUnreachableBlockEliminationPass());
279
280  // Turn exception handling constructs into something the code generators can
281  // handle.
282  switch (getMCAsmInfo()->getExceptionHandlingType()) {
283  case ExceptionHandling::SjLj:
284    // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
285    // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
286    // catch info can get misplaced when a selector ends up more than one block
287    // removed from the parent invoke(s). This could happen when a landing
288    // pad is shared by multiple invokes and is also a target of a normal
289    // edge from elsewhere.
290    PM.add(createSjLjEHPass(getTargetLowering()));
291    // FALLTHROUGH
292  case ExceptionHandling::Dwarf:
293    PM.add(createDwarfEHPass(this));
294    break;
295  case ExceptionHandling::None:
296    PM.add(createLowerInvokePass(getTargetLowering()));
297
298    // The lower invoke pass may create unreachable code. Remove it.
299    PM.add(createUnreachableBlockEliminationPass());
300    break;
301  }
302
303  if (OptLevel != CodeGenOpt::None && !DisableCGP)
304    PM.add(createCodeGenPreparePass(getTargetLowering()));
305
306  PM.add(createStackProtectorPass(getTargetLowering()));
307
308  addPreISel(PM, OptLevel);
309
310  if (PrintISelInput)
311    PM.add(createPrintFunctionPass("\n\n"
312                                   "*** Final LLVM Code input to ISel ***\n",
313                                   &dbgs()));
314
315  // All passes which modify the LLVM IR are now complete; run the verifier
316  // to ensure that the IR is valid.
317  if (!DisableVerify)
318    PM.add(createVerifierPass());
319
320  // Standard Lower-Level Passes.
321
322  // Install a MachineModuleInfo class, which is an immutable pass that holds
323  // all the per-module stuff we're generating, including MCContext.
324  MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo());
325  PM.add(MMI);
326  OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
327
328  // Set up a MachineFunction for the rest of CodeGen to work on.
329  PM.add(new MachineFunctionAnalysis(*this, OptLevel));
330
331  // Enable FastISel with -fast, but allow that to be overridden.
332  if (EnableFastISelOption == cl::BOU_TRUE ||
333      (OptLevel == CodeGenOpt::None && EnableFastISelOption != cl::BOU_FALSE))
334    EnableFastISel = true;
335
336  // Ask the target for an isel.
337  if (addInstSelector(PM, OptLevel))
338    return true;
339
340  // Print the instruction selected machine code...
341  printAndVerify(PM, "After Instruction Selection");
342
343  // Optimize PHIs before DCE: removing dead PHI cycles may make more
344  // instructions dead.
345  if (OptLevel != CodeGenOpt::None)
346    PM.add(createOptimizePHIsPass());
347
348  // If the target requests it, assign local variables to stack slots relative
349  // to one another and simplify frame index references where possible.
350  PM.add(createLocalStackSlotAllocationPass());
351
352  if (OptLevel != CodeGenOpt::None) {
353    // With optimization, dead code should already be eliminated. However
354    // there is one known exception: lowered code for arguments that are only
355    // used by tail calls, where the tail calls reuse the incoming stack
356    // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
357    PM.add(createDeadMachineInstructionElimPass());
358    printAndVerify(PM, "After codegen DCE pass");
359
360    PM.add(createPeepholeOptimizerPass());
361    if (!DisableMachineLICM)
362      PM.add(createMachineLICMPass());
363    PM.add(createMachineCSEPass());
364    if (!DisableMachineSink)
365      PM.add(createMachineSinkingPass());
366    printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
367  }
368
369  // Pre-ra tail duplication.
370  if (OptLevel != CodeGenOpt::None && !DisableEarlyTailDup) {
371    PM.add(createTailDuplicatePass(true));
372    printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
373  }
374
375  // Run pre-ra passes.
376  if (addPreRegAlloc(PM, OptLevel))
377    printAndVerify(PM, "After PreRegAlloc passes");
378
379  // Perform register allocation.
380  PM.add(createRegisterAllocator(OptLevel));
381  printAndVerify(PM, "After Register Allocation");
382
383  // Perform stack slot coloring and post-ra machine LICM.
384  if (OptLevel != CodeGenOpt::None) {
385    // FIXME: Re-enable coloring with register when it's capable of adding
386    // kill markers.
387    if (!DisableSSC)
388      PM.add(createStackSlotColoringPass(false));
389
390    // Run post-ra machine LICM to hoist reloads / remats.
391    if (!DisablePostRAMachineLICM)
392      PM.add(createMachineLICMPass(false));
393
394    printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
395  }
396
397  // Run post-ra passes.
398  if (addPostRegAlloc(PM, OptLevel))
399    printAndVerify(PM, "After PostRegAlloc passes");
400
401  PM.add(createLowerSubregsPass());
402  printAndVerify(PM, "After LowerSubregs");
403
404  // Insert prolog/epilog code.  Eliminate abstract frame index references...
405  PM.add(createPrologEpilogCodeInserter());
406  printAndVerify(PM, "After PrologEpilogCodeInserter");
407
408  // Run pre-sched2 passes.
409  if (addPreSched2(PM, OptLevel))
410    printAndVerify(PM, "After PreSched2 passes");
411
412  // Second pass scheduler.
413  if (OptLevel != CodeGenOpt::None && !DisablePostRA) {
414    PM.add(createPostRAScheduler(OptLevel));
415    printAndVerify(PM, "After PostRAScheduler");
416  }
417
418  // Branch folding must be run after regalloc and prolog/epilog insertion.
419  if (OptLevel != CodeGenOpt::None && !DisableBranchFold) {
420    PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
421    printNoVerify(PM, "After BranchFolding");
422  }
423
424  // Tail duplication.
425  if (OptLevel != CodeGenOpt::None && !DisableTailDuplicate) {
426    PM.add(createTailDuplicatePass(false));
427    printNoVerify(PM, "After TailDuplicate");
428  }
429
430  PM.add(createGCMachineCodeAnalysisPass());
431
432  if (PrintGCInfo)
433    PM.add(createGCInfoPrinter(dbgs()));
434
435  if (OptLevel != CodeGenOpt::None && !DisableCodePlace) {
436    PM.add(createCodePlacementOptPass());
437    printNoVerify(PM, "After CodePlacementOpt");
438  }
439
440  if (addPreEmitPass(PM, OptLevel))
441    printNoVerify(PM, "After PreEmit passes");
442
443  return false;
444}
445