LiveIntervalAnalysis.cpp revision 060913cce42d8b746194c7ebd8b19c9789a03909
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "LiveIntervalAnalysis.h" 20#include "llvm/Value.h" 21#include "llvm/Analysis/LoopInfo.h" 22#include "llvm/CodeGen/LiveVariables.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineInstr.h" 25#include "llvm/CodeGen/Passes.h" 26#include "llvm/CodeGen/SSARegMap.h" 27#include "llvm/Target/MRegisterInfo.h" 28#include "llvm/Target/TargetInstrInfo.h" 29#include "llvm/Target/TargetMachine.h" 30#include "Support/CommandLine.h" 31#include "Support/Debug.h" 32#include "Support/Statistic.h" 33#include "Support/STLExtras.h" 34#include "VirtRegMap.h" 35#include <cmath> 36 37using namespace llvm; 38 39namespace { 40 RegisterAnalysis<LiveIntervals> X("liveintervals", 41 "Live Interval Analysis"); 42 43 Statistic<> numIntervals 44 ("liveintervals", "Number of original intervals"); 45 46 Statistic<> numIntervalsAfter 47 ("liveintervals", "Number of intervals after coalescing"); 48 49 Statistic<> numJoins 50 ("liveintervals", "Number of interval joins performed"); 51 52 Statistic<> numPeep 53 ("liveintervals", "Number of identity moves eliminated after coalescing"); 54 55 Statistic<> numFolded 56 ("liveintervals", "Number of loads/stores folded into instructions"); 57 58 cl::opt<bool> 59 EnableJoining("join-liveintervals", 60 cl::desc("Join compatible live intervals"), 61 cl::init(true)); 62}; 63 64void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const 65{ 66 AU.addPreserved<LiveVariables>(); 67 AU.addRequired<LiveVariables>(); 68 AU.addPreservedID(PHIEliminationID); 69 AU.addRequiredID(PHIEliminationID); 70 AU.addRequiredID(TwoAddressInstructionPassID); 71 AU.addRequired<LoopInfo>(); 72 MachineFunctionPass::getAnalysisUsage(AU); 73} 74 75void LiveIntervals::releaseMemory() 76{ 77 mi2iMap_.clear(); 78 i2miMap_.clear(); 79 for (std::map<unsigned, LiveInterval*>::iterator I = r2iMap_.begin(), 80 E = r2iMap_.end(); I != E; ++I) 81 delete I->second; // free all intervals. 82 r2iMap_.clear(); 83 84 r2rMap_.clear(); 85} 86 87 88/// runOnMachineFunction - Register allocate the whole function 89/// 90bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 91 mf_ = &fn; 92 tm_ = &fn.getTarget(); 93 mri_ = tm_->getRegisterInfo(); 94 lv_ = &getAnalysis<LiveVariables>(); 95 96 // number MachineInstrs 97 unsigned miIndex = 0; 98 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); 99 mbb != mbbEnd; ++mbb) 100 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 101 mi != miEnd; ++mi) { 102 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; 103 assert(inserted && "multiple MachineInstr -> index mappings"); 104 i2miMap_.push_back(mi); 105 miIndex += InstrSlots::NUM; 106 } 107 108 computeIntervals(); 109 110 numIntervals += getNumIntervals(); 111 112#if 1 113 DEBUG(std::cerr << "********** INTERVALS **********\n"); 114 DEBUG(for (iterator I = begin(), E = end(); I != E; ++I) 115 std::cerr << *I->second << "\n"); 116#endif 117 118 // join intervals if requested 119 if (EnableJoining) joinIntervals(); 120 121 numIntervalsAfter += getNumIntervals(); 122 123 // perform a final pass over the instructions and compute spill 124 // weights, coalesce virtual registers and remove identity moves 125 const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); 126 const TargetInstrInfo& tii = *tm_->getInstrInfo(); 127 128 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 129 mbbi != mbbe; ++mbbi) { 130 MachineBasicBlock* mbb = mbbi; 131 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 132 133 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 134 mii != mie; ) { 135 // if the move will be an identity move delete it 136 unsigned srcReg, dstReg, RegRep; 137 if (tii.isMoveInstr(*mii, srcReg, dstReg) && 138 (RegRep = rep(srcReg)) == rep(dstReg)) { 139 // remove from def list 140 LiveInterval &interval = getOrCreateInterval(RegRep); 141 // remove index -> MachineInstr and 142 // MachineInstr -> index mappings 143 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); 144 if (mi2i != mi2iMap_.end()) { 145 i2miMap_[mi2i->second/InstrSlots::NUM] = 0; 146 mi2iMap_.erase(mi2i); 147 } 148 mii = mbbi->erase(mii); 149 ++numPeep; 150 } 151 else { 152 for (unsigned i = 0; i < mii->getNumOperands(); ++i) { 153 const MachineOperand& mop = mii->getOperand(i); 154 if (mop.isRegister() && mop.getReg() && 155 MRegisterInfo::isVirtualRegister(mop.getReg())) { 156 // replace register with representative register 157 unsigned reg = rep(mop.getReg()); 158 mii->SetMachineOperandReg(i, reg); 159 160 LiveInterval &RegInt = getInterval(reg); 161 RegInt.weight += 162 (mop.isUse() + mop.isDef()) * pow(10.0F, loopDepth); 163 } 164 } 165 ++mii; 166 } 167 } 168 } 169 170 DEBUG(std::cerr << "********** INTERVALS **********\n"); 171 DEBUG (for (iterator I = begin(), E = end(); I != E; ++I) 172 std::cerr << *I->second << "\n"); 173 DEBUG(std::cerr << "********** MACHINEINSTRS **********\n"); 174 DEBUG( 175 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 176 mbbi != mbbe; ++mbbi) { 177 std::cerr << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 178 for (MachineBasicBlock::iterator mii = mbbi->begin(), 179 mie = mbbi->end(); mii != mie; ++mii) { 180 std::cerr << getInstructionIndex(mii) << '\t'; 181 mii->print(std::cerr, tm_); 182 } 183 }); 184 185 return true; 186} 187 188std::vector<LiveInterval*> LiveIntervals::addIntervalsForSpills( 189 const LiveInterval& li, 190 VirtRegMap& vrm, 191 int slot) 192{ 193 std::vector<LiveInterval*> added; 194 195 assert(li.weight != HUGE_VAL && 196 "attempt to spill already spilled interval!"); 197 198 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " 199 << li << '\n'); 200 201 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 202 203 for (LiveInterval::Ranges::const_iterator 204 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 205 unsigned index = getBaseIndex(i->start); 206 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 207 for (; index != end; index += InstrSlots::NUM) { 208 // skip deleted instructions 209 while (index != end && !getInstructionFromIndex(index)) 210 index += InstrSlots::NUM; 211 if (index == end) break; 212 213 MachineBasicBlock::iterator mi = getInstructionFromIndex(index); 214 215 for_operand: 216 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { 217 MachineOperand& mop = mi->getOperand(i); 218 if (mop.isRegister() && mop.getReg() == li.reg) { 219 if (MachineInstr* fmi = 220 mri_->foldMemoryOperand(mi, i, slot)) { 221 lv_->instructionChanged(mi, fmi); 222 vrm.virtFolded(li.reg, mi, fmi); 223 mi2iMap_.erase(mi); 224 i2miMap_[index/InstrSlots::NUM] = fmi; 225 mi2iMap_[fmi] = index; 226 MachineBasicBlock& mbb = *mi->getParent(); 227 mi = mbb.insert(mbb.erase(mi), fmi); 228 ++numFolded; 229 goto for_operand; 230 } 231 else { 232 // This is tricky. We need to add information in 233 // the interval about the spill code so we have to 234 // use our extra load/store slots. 235 // 236 // If we have a use we are going to have a load so 237 // we start the interval from the load slot 238 // onwards. Otherwise we start from the def slot. 239 unsigned start = (mop.isUse() ? 240 getLoadIndex(index) : 241 getDefIndex(index)); 242 // If we have a def we are going to have a store 243 // right after it so we end the interval after the 244 // use of the next instruction. Otherwise we end 245 // after the use of this instruction. 246 unsigned end = 1 + (mop.isDef() ? 247 getStoreIndex(index) : 248 getUseIndex(index)); 249 250 // create a new register for this spill 251 unsigned nReg = 252 mf_->getSSARegMap()->createVirtualRegister(rc); 253 mi->SetMachineOperandReg(i, nReg); 254 vrm.grow(); 255 vrm.assignVirt2StackSlot(nReg, slot); 256 LiveInterval& nI = getOrCreateInterval(nReg); 257 assert(nI.empty()); 258 // the spill weight is now infinity as it 259 // cannot be spilled again 260 nI.weight = HUGE_VAL; 261 LiveRange LR(start, end, nI.getNextValue()); 262 DEBUG(std::cerr << " +" << LR); 263 nI.addRange(LR); 264 added.push_back(&nI); 265 // update live variables 266 lv_->addVirtualRegisterKilled(nReg, mi); 267 DEBUG(std::cerr << "\t\t\t\tadded new interval: " 268 << nI << '\n'); 269 } 270 } 271 } 272 } 273 } 274 275 return added; 276} 277 278void LiveIntervals::printRegName(unsigned reg) const 279{ 280 if (MRegisterInfo::isPhysicalRegister(reg)) 281 std::cerr << mri_->getName(reg); 282 else 283 std::cerr << "%reg" << reg; 284} 285 286void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb, 287 MachineBasicBlock::iterator mi, 288 LiveInterval& interval) 289{ 290 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 291 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 292 293 // Virtual registers may be defined multiple times (due to phi 294 // elimination and 2-addr elimination). Much of what we do only has to be 295 // done once for the vreg. We use an empty interval to detect the first 296 // time we see a vreg. 297 if (interval.empty()) { 298 // Get the Idx of the defining instructions. 299 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 300 301 unsigned ValNum = interval.getNextValue(); 302 assert(ValNum == 0 && "First value in interval is not 0?"); 303 ValNum = 0; // Clue in the optimizer. 304 305 // Loop over all of the blocks that the vreg is defined in. There are 306 // two cases we have to handle here. The most common case is a vreg 307 // whose lifetime is contained within a basic block. In this case there 308 // will be a single kill, in MBB, which comes after the definition. 309 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 310 // FIXME: what about dead vars? 311 unsigned killIdx; 312 if (vi.Kills[0] != mi) 313 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 314 else 315 killIdx = defIndex+1; 316 317 // If the kill happens after the definition, we have an intra-block 318 // live range. 319 if (killIdx > defIndex) { 320 assert(vi.AliveBlocks.empty() && 321 "Shouldn't be alive across any blocks!"); 322 LiveRange LR(defIndex, killIdx, ValNum); 323 interval.addRange(LR); 324 DEBUG(std::cerr << " +" << LR << "\n"); 325 return; 326 } 327 } 328 329 // The other case we handle is when a virtual register lives to the end 330 // of the defining block, potentially live across some blocks, then is 331 // live into some number of blocks, but gets killed. Start by adding a 332 // range that goes from this definition to the end of the defining block. 333 LiveRange NewLR(defIndex, getInstructionIndex(&mbb->back()) + 334 InstrSlots::NUM, ValNum); 335 DEBUG(std::cerr << " +" << NewLR); 336 interval.addRange(NewLR); 337 338 // Iterate over all of the blocks that the variable is completely 339 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 340 // live interval. 341 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 342 if (vi.AliveBlocks[i]) { 343 MachineBasicBlock* mbb = mf_->getBlockNumbered(i); 344 if (!mbb->empty()) { 345 LiveRange LR(getInstructionIndex(&mbb->front()), 346 getInstructionIndex(&mbb->back())+InstrSlots::NUM, 347 ValNum); 348 interval.addRange(LR); 349 DEBUG(std::cerr << " +" << LR); 350 } 351 } 352 } 353 354 // Finally, this virtual register is live from the start of any killing 355 // block to the 'use' slot of the killing instruction. 356 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 357 MachineInstr *Kill = vi.Kills[i]; 358 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), 359 getUseIndex(getInstructionIndex(Kill))+1, ValNum); 360 interval.addRange(LR); 361 DEBUG(std::cerr << " +" << LR); 362 } 363 364 } else { 365 // If this is the second time we see a virtual register definition, it 366 // must be due to phi elimination or two addr elimination. If this is 367 // the result of two address elimination, then the vreg is the first 368 // operand, and is a def-and-use. 369 if (mi->getOperand(0).isRegister() && 370 mi->getOperand(0).getReg() == interval.reg && 371 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { 372 // If this is a two-address definition, then we have already processed 373 // the live range. The only problem is that we didn't realize there 374 // are actually two values in the live interval. Because of this we 375 // need to take the LiveRegion that defines this register and split it 376 // into two values. 377 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 378 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi)); 379 380 // Delete the initial value, which should be short and continuous, 381 // becuase the 2-addr copy must be in the same MBB as the redef. 382 interval.removeRange(DefIndex, RedefIndex); 383 384 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue()); 385 DEBUG(std::cerr << " replace range with " << LR); 386 interval.addRange(LR); 387 388 // If this redefinition is dead, we need to add a dummy unit live 389 // range covering the def slot. 390 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi), 391 E = lv_->dead_end(mi); KI != E; ++KI) 392 if (KI->second == interval.reg) { 393 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 394 break; 395 } 396 397 DEBUG(std::cerr << "RESULT: " << interval); 398 399 } else { 400 // Otherwise, this must be because of phi elimination. In this case, 401 // the defined value will be live until the end of the basic block it 402 // is defined in. 403 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 404 LiveRange LR(defIndex, 405 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 406 interval.getNextValue()); 407 interval.addRange(LR); 408 DEBUG(std::cerr << " +" << LR); 409 } 410 } 411 412 DEBUG(std::cerr << '\n'); 413} 414 415void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 416 MachineBasicBlock::iterator mi, 417 LiveInterval& interval) 418{ 419 // A physical register cannot be live across basic block, so its 420 // lifetime must end somewhere in its defining basic block. 421 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 422 typedef LiveVariables::killed_iterator KillIter; 423 424 unsigned baseIndex = getInstructionIndex(mi); 425 unsigned start = getDefIndex(baseIndex); 426 unsigned end = start; 427 428 // If it is not used after definition, it is considered dead at 429 // the instruction defining it. Hence its interval is: 430 // [defSlot(def), defSlot(def)+1) 431 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); 432 ki != ke; ++ki) { 433 if (interval.reg == ki->second) { 434 DEBUG(std::cerr << " dead"); 435 end = getDefIndex(start) + 1; 436 goto exit; 437 } 438 } 439 440 // If it is not dead on definition, it must be killed by a 441 // subsequent instruction. Hence its interval is: 442 // [defSlot(def), useSlot(kill)+1) 443 while (true) { 444 ++mi; 445 assert(mi != MBB->end() && "physreg was not killed in defining block!"); 446 baseIndex += InstrSlots::NUM; 447 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); 448 ki != ke; ++ki) { 449 if (interval.reg == ki->second) { 450 DEBUG(std::cerr << " killed"); 451 end = getUseIndex(baseIndex) + 1; 452 goto exit; 453 } 454 } 455 } 456 457exit: 458 assert(start < end && "did not find end of interval?"); 459 LiveRange LR(start, end, interval.getNextValue()); 460 interval.addRange(LR); 461 DEBUG(std::cerr << " +" << LR << '\n'); 462} 463 464void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 465 MachineBasicBlock::iterator MI, 466 unsigned reg) { 467 if (MRegisterInfo::isVirtualRegister(reg)) 468 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); 469 else if (lv_->getAllocatablePhysicalRegisters()[reg]) { 470 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg)); 471 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 472 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS)); 473 } 474} 475 476/// computeIntervals - computes the live intervals for virtual 477/// registers. for some ordering of the machine instructions [1,N] a 478/// live interval is an interval [i, j) where 1 <= i <= j < N for 479/// which a variable is live 480void LiveIntervals::computeIntervals() 481{ 482 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 483 DEBUG(std::cerr << "********** Function: " 484 << ((Value*)mf_->getFunction())->getName() << '\n'); 485 486 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 487 I != E; ++I) { 488 MachineBasicBlock* mbb = I; 489 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); 490 491 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 492 mi != miEnd; ++mi) { 493 const TargetInstrDescriptor& tid = 494 tm_->getInstrInfo()->get(mi->getOpcode()); 495 DEBUG(std::cerr << getInstructionIndex(mi) << "\t"; 496 mi->print(std::cerr, tm_)); 497 498 // handle implicit defs 499 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) 500 handleRegisterDef(mbb, mi, *id); 501 502 // handle explicit defs 503 for (int i = mi->getNumOperands() - 1; i >= 0; --i) { 504 MachineOperand& mop = mi->getOperand(i); 505 // handle register defs - build intervals 506 if (mop.isRegister() && mop.getReg() && mop.isDef()) 507 handleRegisterDef(mbb, mi, mop.getReg()); 508 } 509 } 510 } 511} 512 513void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) { 514 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 515 const TargetInstrInfo &TII = *tm_->getInstrInfo(); 516 517 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); 518 mi != mie; ++mi) { 519 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi); 520 521 // we only join virtual registers with allocatable 522 // physical registers since we do not have liveness information 523 // on not allocatable physical registers 524 unsigned regA, regB; 525 if (TII.isMoveInstr(*mi, regA, regB) && 526 (MRegisterInfo::isVirtualRegister(regA) || 527 lv_->getAllocatablePhysicalRegisters()[regA]) && 528 (MRegisterInfo::isVirtualRegister(regB) || 529 lv_->getAllocatablePhysicalRegisters()[regB])) { 530 531 // Get representative registers. 532 regA = rep(regA); 533 regB = rep(regB); 534 535 // If they are already joined we continue. 536 if (regA == regB) 537 continue; 538 539 // If they are both physical registers, we cannot join them. 540 if (MRegisterInfo::isPhysicalRegister(regA) && 541 MRegisterInfo::isPhysicalRegister(regB)) 542 continue; 543 544 // If they are not of the same register class, we cannot join them. 545 if (differingRegisterClasses(regA, regB)) 546 continue; 547 548 LiveInterval &IntA = getInterval(regA); 549 LiveInterval &IntB = getInterval(regB); 550 assert(IntA.reg == regA && IntB.reg == regB && 551 "Register mapping is horribly broken!"); 552 553 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": "); 554 555 // If two intervals contain a single value and are joined by a copy, it 556 // does not matter if the intervals overlap, they can always be joined. 557 bool TriviallyJoinable = 558 IntA.containsOneValue() && IntB.containsOneValue(); 559 560 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi)); 561 if ((TriviallyJoinable || !IntB.joinable(IntA, MIDefIdx)) && 562 !overlapsAliases(&IntA, &IntB)) { 563 IntB.join(IntA, MIDefIdx); 564 delete r2iMap_[regA]; // Delete the dead interval 565 566 if (!MRegisterInfo::isPhysicalRegister(regA)) { 567 r2iMap_.erase(regA); 568 r2rMap_[regA] = regB; 569 } else { 570 // Otherwise merge the data structures the other way so we don't lose 571 // the physreg information. 572 r2rMap_[regB] = regA; 573 IntB.reg = regA; 574 r2iMap_[regA] = r2iMap_[regB]; 575 r2iMap_.erase(regB); 576 } 577 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); 578 ++numJoins; 579 } else { 580 DEBUG(std::cerr << "Interference!\n"); 581 } 582 } 583 } 584} 585 586namespace { 587 // DepthMBBCompare - Comparison predicate that sort first based on the loop 588 // depth of the basic block (the unsigned), and then on the MBB number. 589 struct DepthMBBCompare { 590 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 591 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 592 if (LHS.first > RHS.first) return true; // Deeper loops first 593 return LHS.first == RHS.first && 594 LHS.second->getNumber() < RHS.second->getNumber(); 595 } 596 }; 597} 598 599void LiveIntervals::joinIntervals() { 600 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 601 602 const LoopInfo &LI = getAnalysis<LoopInfo>(); 603 if (LI.begin() == LI.end()) { 604 // If there are no loops in the function, join intervals in function order. 605 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 606 I != E; ++I) 607 joinIntervalsInMachineBB(I); 608 } else { 609 // Otherwise, join intervals in inner loops before other intervals. 610 // Unfortunately we can't just iterate over loop hierarchy here because 611 // there may be more MBB's than BB's. Collect MBB's for sorting. 612 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 613 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 614 I != E; ++I) 615 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 616 617 // Sort by loop depth. 618 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 619 620 // Finally, join intervals in loop nest order. 621 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 622 joinIntervalsInMachineBB(MBBs[i].second); 623 } 624} 625 626/// Return true if the two specified registers belong to different register 627/// classes. The registers may be either phys or virt regs. 628bool LiveIntervals::differingRegisterClasses(unsigned RegA, 629 unsigned RegB) const { 630 const TargetRegisterClass *RegClass; 631 632 // Get the register classes for the first reg. 633 if (MRegisterInfo::isVirtualRegister(RegA)) 634 RegClass = mf_->getSSARegMap()->getRegClass(RegA); 635 else 636 RegClass = mri_->getRegClass(RegA); 637 638 // Compare against the regclass for the second reg. 639 if (MRegisterInfo::isVirtualRegister(RegB)) 640 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 641 else 642 return RegClass != mri_->getRegClass(RegB); 643} 644 645bool LiveIntervals::overlapsAliases(const LiveInterval *LHS, 646 const LiveInterval *RHS) const { 647 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) { 648 if (!MRegisterInfo::isPhysicalRegister(RHS->reg)) 649 return false; // vreg-vreg merge has no aliases! 650 std::swap(LHS, RHS); 651 } 652 653 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) && 654 MRegisterInfo::isVirtualRegister(RHS->reg) && 655 "first interval must describe a physical register"); 656 657 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS) 658 if (RHS->overlaps(getInterval(*AS))) 659 return true; 660 661 return false; 662} 663 664LiveInterval *LiveIntervals::createInterval(unsigned reg) const { 665 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? HUGE_VAL :0.0F; 666 return new LiveInterval(reg, Weight); 667} 668 669