LiveIntervalAnalysis.cpp revision 30cac02a925c9d56613711b0e77099cb7252bc9b
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37using namespace llvm; 38 39STATISTIC(numIntervals, "Number of original intervals"); 40STATISTIC(numIntervalsAfter, "Number of intervals after coalescing"); 41STATISTIC(numJoins , "Number of interval joins performed"); 42STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); 43STATISTIC(numFolded , "Number of loads/stores folded into instructions"); 44 45namespace { 46 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 47 48 static cl::opt<bool> 49 EnableJoining("join-liveintervals", 50 cl::desc("Coallesce copies (default=true)"), 51 cl::init(true)); 52} 53 54void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 55 AU.addRequired<LiveVariables>(); 56 AU.addPreservedID(PHIEliminationID); 57 AU.addRequiredID(PHIEliminationID); 58 AU.addRequiredID(TwoAddressInstructionPassID); 59 AU.addRequired<LoopInfo>(); 60 MachineFunctionPass::getAnalysisUsage(AU); 61} 62 63void LiveIntervals::releaseMemory() { 64 mi2iMap_.clear(); 65 i2miMap_.clear(); 66 r2iMap_.clear(); 67 r2rMap_.clear(); 68} 69 70 71static bool isZeroLengthInterval(LiveInterval *li) { 72 for (LiveInterval::Ranges::const_iterator 73 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) 74 if (i->end - i->start > LiveIntervals::InstrSlots::NUM) 75 return false; 76 return true; 77} 78 79 80/// runOnMachineFunction - Register allocate the whole function 81/// 82bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 83 mf_ = &fn; 84 tm_ = &fn.getTarget(); 85 mri_ = tm_->getRegisterInfo(); 86 tii_ = tm_->getInstrInfo(); 87 lv_ = &getAnalysis<LiveVariables>(); 88 allocatableRegs_ = mri_->getAllocatableSet(fn); 89 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 90 91 // Number MachineInstrs and MachineBasicBlocks. 92 // Initialize MBB indexes to a sentinal. 93 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U); 94 95 unsigned MIIndex = 0; 96 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); 97 MBB != E; ++MBB) { 98 // Set the MBB2IdxMap entry for this MBB. 99 MBB2IdxMap[MBB->getNumber()] = MIIndex; 100 101 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 102 I != E; ++I) { 103 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second; 104 assert(inserted && "multiple MachineInstr -> index mappings"); 105 i2miMap_.push_back(I); 106 MIIndex += InstrSlots::NUM; 107 } 108 } 109 110 computeIntervals(); 111 112 numIntervals += getNumIntervals(); 113 114 DOUT << "********** INTERVALS **********\n"; 115 for (iterator I = begin(), E = end(); I != E; ++I) { 116 I->second.print(DOUT, mri_); 117 DOUT << "\n"; 118 } 119 120 // Join (coallesce) intervals if requested. 121 if (EnableJoining) joinIntervals(); 122 123 numIntervalsAfter += getNumIntervals(); 124 125 126 // perform a final pass over the instructions and compute spill 127 // weights, coalesce virtual registers and remove identity moves. 128 const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); 129 130 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 131 mbbi != mbbe; ++mbbi) { 132 MachineBasicBlock* mbb = mbbi; 133 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 134 135 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 136 mii != mie; ) { 137 // if the move will be an identity move delete it 138 unsigned srcReg, dstReg, RegRep; 139 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 140 (RegRep = rep(srcReg)) == rep(dstReg)) { 141 // remove from def list 142 LiveInterval &RegInt = getOrCreateInterval(RegRep); 143 MachineOperand *MO = mii->findRegisterDefOperand(dstReg); 144 // If def of this move instruction is dead, remove its live range from 145 // the dstination register's live interval. 146 if (MO->isDead()) { 147 unsigned MoveIdx = getDefIndex(getInstructionIndex(mii)); 148 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx); 149 RegInt.removeRange(MLR->start, MoveIdx+1); 150 if (RegInt.empty()) 151 removeInterval(RegRep); 152 } 153 RemoveMachineInstrFromMaps(mii); 154 mii = mbbi->erase(mii); 155 ++numPeep; 156 } 157 else { 158 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { 159 const MachineOperand &mop = mii->getOperand(i); 160 if (mop.isRegister() && mop.getReg() && 161 MRegisterInfo::isVirtualRegister(mop.getReg())) { 162 // replace register with representative register 163 unsigned reg = rep(mop.getReg()); 164 mii->getOperand(i).setReg(reg); 165 166 LiveInterval &RegInt = getInterval(reg); 167 RegInt.weight += 168 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 169 } 170 } 171 ++mii; 172 } 173 } 174 } 175 176 for (iterator I = begin(), E = end(); I != E; ++I) { 177 LiveInterval &LI = I->second; 178 if (MRegisterInfo::isVirtualRegister(LI.reg)) { 179 // If the live interval length is essentially zero, i.e. in every live 180 // range the use follows def immediately, it doesn't make sense to spill 181 // it and hope it will be easier to allocate for this li. 182 if (isZeroLengthInterval(&LI)) 183 LI.weight = HUGE_VALF; 184 185 // Divide the weight of the interval by its size. This encourages 186 // spilling of intervals that are large and have few uses, and 187 // discourages spilling of small intervals with many uses. 188 unsigned Size = 0; 189 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II) 190 Size += II->end - II->start; 191 192 LI.weight /= Size; 193 } 194 } 195 196 DEBUG(dump()); 197 return true; 198} 199 200/// print - Implement the dump method. 201void LiveIntervals::print(std::ostream &O, const Module* ) const { 202 O << "********** INTERVALS **********\n"; 203 for (const_iterator I = begin(), E = end(); I != E; ++I) { 204 I->second.print(DOUT, mri_); 205 DOUT << "\n"; 206 } 207 208 O << "********** MACHINEINSTRS **********\n"; 209 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 210 mbbi != mbbe; ++mbbi) { 211 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 212 for (MachineBasicBlock::iterator mii = mbbi->begin(), 213 mie = mbbi->end(); mii != mie; ++mii) { 214 O << getInstructionIndex(mii) << '\t' << *mii; 215 } 216 } 217} 218 219/// CreateNewLiveInterval - Create a new live interval with the given live 220/// ranges. The new live interval will have an infinite spill weight. 221LiveInterval& 222LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI, 223 const std::vector<LiveRange> &LRs) { 224 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg); 225 226 // Create a new virtual register for the spill interval. 227 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC); 228 229 // Replace the old virtual registers in the machine operands with the shiny 230 // new one. 231 for (std::vector<LiveRange>::const_iterator 232 I = LRs.begin(), E = LRs.end(); I != E; ++I) { 233 unsigned Index = getBaseIndex(I->start); 234 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM; 235 236 for (; Index != End; Index += InstrSlots::NUM) { 237 // Skip deleted instructions 238 while (Index != End && !getInstructionFromIndex(Index)) 239 Index += InstrSlots::NUM; 240 241 if (Index == End) break; 242 243 MachineInstr *MI = getInstructionFromIndex(Index); 244 245 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) { 246 MachineOperand &MOp = MI->getOperand(J); 247 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg) 248 MOp.setReg(NewVReg); 249 } 250 } 251 } 252 253 LiveInterval &NewLI = getOrCreateInterval(NewVReg); 254 255 // The spill weight is now infinity as it cannot be spilled again 256 NewLI.weight = float(HUGE_VAL); 257 258 for (std::vector<LiveRange>::const_iterator 259 I = LRs.begin(), E = LRs.end(); I != E; ++I) { 260 DOUT << " Adding live range " << *I << " to new interval\n"; 261 NewLI.addRange(*I); 262 } 263 264 DOUT << "Created new live interval " << NewLI << "\n"; 265 return NewLI; 266} 267 268std::vector<LiveInterval*> LiveIntervals:: 269addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 270 // since this is called after the analysis is done we don't know if 271 // LiveVariables is available 272 lv_ = getAnalysisToUpdate<LiveVariables>(); 273 274 std::vector<LiveInterval*> added; 275 276 assert(li.weight != HUGE_VALF && 277 "attempt to spill already spilled interval!"); 278 279 DOUT << "\t\t\t\tadding intervals for spills for interval: "; 280 li.print(DOUT, mri_); 281 DOUT << '\n'; 282 283 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 284 285 for (LiveInterval::Ranges::const_iterator 286 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 287 unsigned index = getBaseIndex(i->start); 288 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 289 for (; index != end; index += InstrSlots::NUM) { 290 // skip deleted instructions 291 while (index != end && !getInstructionFromIndex(index)) 292 index += InstrSlots::NUM; 293 if (index == end) break; 294 295 MachineInstr *MI = getInstructionFromIndex(index); 296 297 RestartInstruction: 298 for (unsigned i = 0; i != MI->getNumOperands(); ++i) { 299 MachineOperand& mop = MI->getOperand(i); 300 if (mop.isRegister() && mop.getReg() == li.reg) { 301 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) { 302 // Attempt to fold the memory reference into the instruction. If we 303 // can do this, we don't need to insert spill code. 304 if (lv_) 305 lv_->instructionChanged(MI, fmi); 306 MachineBasicBlock &MBB = *MI->getParent(); 307 vrm.virtFolded(li.reg, MI, i, fmi); 308 mi2iMap_.erase(MI); 309 i2miMap_[index/InstrSlots::NUM] = fmi; 310 mi2iMap_[fmi] = index; 311 MI = MBB.insert(MBB.erase(MI), fmi); 312 ++numFolded; 313 // Folding the load/store can completely change the instruction in 314 // unpredictable ways, rescan it from the beginning. 315 goto RestartInstruction; 316 } else { 317 // Create a new virtual register for the spill interval. 318 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc); 319 320 // Scan all of the operands of this instruction rewriting operands 321 // to use NewVReg instead of li.reg as appropriate. We do this for 322 // two reasons: 323 // 324 // 1. If the instr reads the same spilled vreg multiple times, we 325 // want to reuse the NewVReg. 326 // 2. If the instr is a two-addr instruction, we are required to 327 // keep the src/dst regs pinned. 328 // 329 // Keep track of whether we replace a use and/or def so that we can 330 // create the spill interval with the appropriate range. 331 mop.setReg(NewVReg); 332 333 bool HasUse = mop.isUse(); 334 bool HasDef = mop.isDef(); 335 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { 336 if (MI->getOperand(j).isReg() && 337 MI->getOperand(j).getReg() == li.reg) { 338 MI->getOperand(j).setReg(NewVReg); 339 HasUse |= MI->getOperand(j).isUse(); 340 HasDef |= MI->getOperand(j).isDef(); 341 } 342 } 343 344 // create a new register for this spill 345 vrm.grow(); 346 vrm.assignVirt2StackSlot(NewVReg, slot); 347 LiveInterval &nI = getOrCreateInterval(NewVReg); 348 assert(nI.empty()); 349 350 // the spill weight is now infinity as it 351 // cannot be spilled again 352 nI.weight = HUGE_VALF; 353 354 if (HasUse) { 355 LiveRange LR(getLoadIndex(index), getUseIndex(index), 356 nI.getNextValue(~0U, 0)); 357 DOUT << " +" << LR; 358 nI.addRange(LR); 359 } 360 if (HasDef) { 361 LiveRange LR(getDefIndex(index), getStoreIndex(index), 362 nI.getNextValue(~0U, 0)); 363 DOUT << " +" << LR; 364 nI.addRange(LR); 365 } 366 367 added.push_back(&nI); 368 369 // update live variables if it is available 370 if (lv_) 371 lv_->addVirtualRegisterKilled(NewVReg, MI); 372 373 DOUT << "\t\t\t\tadded new interval: "; 374 nI.print(DOUT, mri_); 375 DOUT << '\n'; 376 } 377 } 378 } 379 } 380 } 381 382 return added; 383} 384 385void LiveIntervals::printRegName(unsigned reg) const { 386 if (MRegisterInfo::isPhysicalRegister(reg)) 387 cerr << mri_->getName(reg); 388 else 389 cerr << "%reg" << reg; 390} 391 392/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to 393/// two addr elimination. 394static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg, 395 const TargetInstrInfo *TII) { 396 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 397 MachineOperand &MO1 = MI->getOperand(i); 398 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { 399 for (unsigned j = i+1; j < e; ++j) { 400 MachineOperand &MO2 = MI->getOperand(j); 401 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && 402 MI->getInstrDescriptor()-> 403 getOperandConstraint(j, TOI::TIED_TO) == (int)i) 404 return true; 405 } 406 } 407 } 408 return false; 409} 410 411void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 412 MachineBasicBlock::iterator mi, 413 unsigned MIIdx, 414 LiveInterval &interval) { 415 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); 416 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 417 418 // Virtual registers may be defined multiple times (due to phi 419 // elimination and 2-addr elimination). Much of what we do only has to be 420 // done once for the vreg. We use an empty interval to detect the first 421 // time we see a vreg. 422 if (interval.empty()) { 423 // Get the Idx of the defining instructions. 424 unsigned defIndex = getDefIndex(MIIdx); 425 426 unsigned ValNum; 427 unsigned SrcReg, DstReg; 428 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 429 ValNum = interval.getNextValue(~0U, 0); 430 else 431 ValNum = interval.getNextValue(defIndex, SrcReg); 432 433 assert(ValNum == 0 && "First value in interval is not 0?"); 434 ValNum = 0; // Clue in the optimizer. 435 436 // Loop over all of the blocks that the vreg is defined in. There are 437 // two cases we have to handle here. The most common case is a vreg 438 // whose lifetime is contained within a basic block. In this case there 439 // will be a single kill, in MBB, which comes after the definition. 440 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 441 // FIXME: what about dead vars? 442 unsigned killIdx; 443 if (vi.Kills[0] != mi) 444 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 445 else 446 killIdx = defIndex+1; 447 448 // If the kill happens after the definition, we have an intra-block 449 // live range. 450 if (killIdx > defIndex) { 451 assert(vi.AliveBlocks.none() && 452 "Shouldn't be alive across any blocks!"); 453 LiveRange LR(defIndex, killIdx, ValNum); 454 interval.addRange(LR); 455 DOUT << " +" << LR << "\n"; 456 return; 457 } 458 } 459 460 // The other case we handle is when a virtual register lives to the end 461 // of the defining block, potentially live across some blocks, then is 462 // live into some number of blocks, but gets killed. Start by adding a 463 // range that goes from this definition to the end of the defining block. 464 LiveRange NewLR(defIndex, 465 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 466 ValNum); 467 DOUT << " +" << NewLR; 468 interval.addRange(NewLR); 469 470 // Iterate over all of the blocks that the variable is completely 471 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 472 // live interval. 473 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 474 if (vi.AliveBlocks[i]) { 475 MachineBasicBlock *MBB = mf_->getBlockNumbered(i); 476 if (!MBB->empty()) { 477 LiveRange LR(getMBBStartIdx(i), 478 getInstructionIndex(&MBB->back()) + InstrSlots::NUM, 479 ValNum); 480 interval.addRange(LR); 481 DOUT << " +" << LR; 482 } 483 } 484 } 485 486 // Finally, this virtual register is live from the start of any killing 487 // block to the 'use' slot of the killing instruction. 488 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 489 MachineInstr *Kill = vi.Kills[i]; 490 LiveRange LR(getMBBStartIdx(Kill->getParent()), 491 getUseIndex(getInstructionIndex(Kill))+1, 492 ValNum); 493 interval.addRange(LR); 494 DOUT << " +" << LR; 495 } 496 497 } else { 498 // If this is the second time we see a virtual register definition, it 499 // must be due to phi elimination or two addr elimination. If this is 500 // the result of two address elimination, then the vreg is one of the 501 // def-and-use register operand. 502 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) { 503 // If this is a two-address definition, then we have already processed 504 // the live range. The only problem is that we didn't realize there 505 // are actually two values in the live interval. Because of this we 506 // need to take the LiveRegion that defines this register and split it 507 // into two values. 508 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 509 unsigned RedefIndex = getDefIndex(MIIdx); 510 511 // Delete the initial value, which should be short and continuous, 512 // because the 2-addr copy must be in the same MBB as the redef. 513 interval.removeRange(DefIndex, RedefIndex); 514 515 // Two-address vregs should always only be redefined once. This means 516 // that at this point, there should be exactly one value number in it. 517 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!"); 518 519 // The new value number (#1) is defined by the instruction we claimed 520 // defined value #0. 521 unsigned ValNo = interval.getNextValue(0, 0); 522 interval.setValueNumberInfo(1, interval.getValNumInfo(0)); 523 524 // Value#0 is now defined by the 2-addr instruction. 525 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U)); 526 527 // Add the new live interval which replaces the range for the input copy. 528 LiveRange LR(DefIndex, RedefIndex, ValNo); 529 DOUT << " replace range with " << LR; 530 interval.addRange(LR); 531 532 // If this redefinition is dead, we need to add a dummy unit live 533 // range covering the def slot. 534 if (lv_->RegisterDefIsDead(mi, interval.reg)) 535 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 536 537 DOUT << "RESULT: "; 538 interval.print(DOUT, mri_); 539 540 } else { 541 // Otherwise, this must be because of phi elimination. If this is the 542 // first redefinition of the vreg that we have seen, go back and change 543 // the live range in the PHI block to be a different value number. 544 if (interval.containsOneValue()) { 545 assert(vi.Kills.size() == 1 && 546 "PHI elimination vreg should have one kill, the PHI itself!"); 547 548 // Remove the old range that we now know has an incorrect number. 549 MachineInstr *Killer = vi.Kills[0]; 550 unsigned Start = getMBBStartIdx(Killer->getParent()); 551 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 552 DOUT << "Removing [" << Start << "," << End << "] from: "; 553 interval.print(DOUT, mri_); DOUT << "\n"; 554 interval.removeRange(Start, End); 555 DOUT << "RESULT: "; interval.print(DOUT, mri_); 556 557 // Replace the interval with one of a NEW value number. Note that this 558 // value number isn't actually defined by an instruction, weird huh? :) 559 LiveRange LR(Start, End, interval.getNextValue(~0U, 0)); 560 DOUT << " replace range with " << LR; 561 interval.addRange(LR); 562 DOUT << "RESULT: "; interval.print(DOUT, mri_); 563 } 564 565 // In the case of PHI elimination, each variable definition is only 566 // live until the end of the block. We've already taken care of the 567 // rest of the live range. 568 unsigned defIndex = getDefIndex(MIIdx); 569 570 unsigned ValNum; 571 unsigned SrcReg, DstReg; 572 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 573 ValNum = interval.getNextValue(~0U, 0); 574 else 575 ValNum = interval.getNextValue(defIndex, SrcReg); 576 577 LiveRange LR(defIndex, 578 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum); 579 interval.addRange(LR); 580 DOUT << " +" << LR; 581 } 582 } 583 584 DOUT << '\n'; 585} 586 587void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 588 MachineBasicBlock::iterator mi, 589 unsigned MIIdx, 590 LiveInterval &interval, 591 unsigned SrcReg) { 592 // A physical register cannot be live across basic block, so its 593 // lifetime must end somewhere in its defining basic block. 594 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); 595 596 unsigned baseIndex = MIIdx; 597 unsigned start = getDefIndex(baseIndex); 598 unsigned end = start; 599 600 // If it is not used after definition, it is considered dead at 601 // the instruction defining it. Hence its interval is: 602 // [defSlot(def), defSlot(def)+1) 603 if (lv_->RegisterDefIsDead(mi, interval.reg)) { 604 DOUT << " dead"; 605 end = getDefIndex(start) + 1; 606 goto exit; 607 } 608 609 // If it is not dead on definition, it must be killed by a 610 // subsequent instruction. Hence its interval is: 611 // [defSlot(def), useSlot(kill)+1) 612 while (++mi != MBB->end()) { 613 baseIndex += InstrSlots::NUM; 614 if (lv_->KillsRegister(mi, interval.reg)) { 615 DOUT << " killed"; 616 end = getUseIndex(baseIndex) + 1; 617 goto exit; 618 } else if (lv_->ModifiesRegister(mi, interval.reg)) { 619 // Another instruction redefines the register before it is ever read. 620 // Then the register is essentially dead at the instruction that defines 621 // it. Hence its interval is: 622 // [defSlot(def), defSlot(def)+1) 623 DOUT << " dead"; 624 end = getDefIndex(start) + 1; 625 goto exit; 626 } 627 } 628 629 // The only case we should have a dead physreg here without a killing or 630 // instruction where we know it's dead is if it is live-in to the function 631 // and never used. 632 assert(!SrcReg && "physreg was not killed in defining block!"); 633 end = getDefIndex(start) + 1; // It's dead. 634 635exit: 636 assert(start < end && "did not find end of interval?"); 637 638 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U, 639 SrcReg)); 640 interval.addRange(LR); 641 DOUT << " +" << LR << '\n'; 642} 643 644void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 645 MachineBasicBlock::iterator MI, 646 unsigned MIIdx, 647 unsigned reg) { 648 if (MRegisterInfo::isVirtualRegister(reg)) 649 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); 650 else if (allocatableRegs_[reg]) { 651 unsigned SrcReg, DstReg; 652 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) 653 SrcReg = 0; 654 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); 655 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 656 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); 657 } 658} 659 660void LiveIntervals::handleLiveInRegister(MachineBasicBlock *MBB, 661 unsigned MIIdx, 662 LiveInterval &interval) { 663 DOUT << "\t\tlivein register: "; DEBUG(printRegName(interval.reg)); 664 665 // Look for kills, if it reaches a def before it's killed, then it shouldn't 666 // be considered a livein. 667 MachineBasicBlock::iterator mi = MBB->begin(); 668 unsigned baseIndex = MIIdx; 669 unsigned start = baseIndex; 670 unsigned end = start; 671 while (mi != MBB->end()) { 672 if (lv_->KillsRegister(mi, interval.reg)) { 673 DOUT << " killed"; 674 end = getUseIndex(baseIndex) + 1; 675 goto exit; 676 } else if (lv_->ModifiesRegister(mi, interval.reg)) { 677 // Another instruction redefines the register before it is ever read. 678 // Then the register is essentially dead at the instruction that defines 679 // it. Hence its interval is: 680 // [defSlot(def), defSlot(def)+1) 681 DOUT << " dead"; 682 end = getDefIndex(start) + 1; 683 goto exit; 684 } 685 686 baseIndex += InstrSlots::NUM; 687 ++mi; 688 } 689 690exit: 691 assert(start < end && "did not find end of interval?"); 692 693 LiveRange LR(start, end, interval.getNextValue(~0U, 0)); 694 DOUT << " +" << LR << '\n'; 695 interval.addRange(LR); 696} 697 698/// computeIntervals - computes the live intervals for virtual 699/// registers. for some ordering of the machine instructions [1,N] a 700/// live interval is an interval [i, j) where 1 <= i <= j < N for 701/// which a variable is live 702void LiveIntervals::computeIntervals() { 703 DOUT << "********** COMPUTING LIVE INTERVALS **********\n" 704 << "********** Function: " 705 << ((Value*)mf_->getFunction())->getName() << '\n'; 706 // Track the index of the current machine instr. 707 unsigned MIIndex = 0; 708 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); 709 MBBI != E; ++MBBI) { 710 MachineBasicBlock *MBB = MBBI; 711 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; 712 713 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); 714 715 if (MBB->livein_begin() != MBB->livein_end()) { 716 // Create intervals for live-ins to this BB first. 717 for (MachineBasicBlock::const_livein_iterator LI = MBB->livein_begin(), 718 LE = MBB->livein_end(); LI != LE; ++LI) { 719 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI)); 720 for (const unsigned* AS = mri_->getAliasSet(*LI); *AS; ++AS) 721 handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS)); 722 } 723 } 724 725 for (; MI != miEnd; ++MI) { 726 DOUT << MIIndex << "\t" << *MI; 727 728 // Handle defs. 729 for (int i = MI->getNumOperands() - 1; i >= 0; --i) { 730 MachineOperand &MO = MI->getOperand(i); 731 // handle register defs - build intervals 732 if (MO.isRegister() && MO.getReg() && MO.isDef()) 733 handleRegisterDef(MBB, MI, MIIndex, MO.getReg()); 734 } 735 736 MIIndex += InstrSlots::NUM; 737 } 738 } 739} 740 741/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA 742/// being the source and IntB being the dest, thus this defines a value number 743/// in IntB. If the source value number (in IntA) is defined by a copy from B, 744/// see if we can merge these two pieces of B into a single value number, 745/// eliminating a copy. For example: 746/// 747/// A3 = B0 748/// ... 749/// B1 = A3 <- this copy 750/// 751/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 752/// value number to be replaced with B0 (which simplifies the B liveinterval). 753/// 754/// This returns true if an interval was modified. 755/// 756bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, 757 MachineInstr *CopyMI) { 758 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 759 760 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 761 // the example above. 762 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 763 unsigned BValNo = BLR->ValId; 764 765 // Get the location that B is defined at. Two options: either this value has 766 // an unknown definition point or it is defined at CopyIdx. If unknown, we 767 // can't process it. 768 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo); 769 if (BValNoDefIdx == ~0U) return false; 770 assert(BValNoDefIdx == CopyIdx && 771 "Copy doesn't define the value?"); 772 773 // AValNo is the value number in A that defines the copy, A0 in the example. 774 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); 775 unsigned AValNo = AValLR->ValId; 776 777 // If AValNo is defined as a copy from IntB, we can potentially process this. 778 779 // Get the instruction that defines this value number. 780 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo); 781 if (!SrcReg) return false; // Not defined by a copy. 782 783 // If the value number is not defined by a copy instruction, ignore it. 784 785 // If the source register comes from an interval other than IntB, we can't 786 // handle this. 787 if (rep(SrcReg) != IntB.reg) return false; 788 789 // Get the LiveRange in IntB that this value number starts with. 790 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo); 791 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1); 792 793 // Make sure that the end of the live range is inside the same block as 794 // CopyMI. 795 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1); 796 if (!ValLREndInst || 797 ValLREndInst->getParent() != CopyMI->getParent()) return false; 798 799 // Okay, we now know that ValLR ends in the same block that the CopyMI 800 // live-range starts. If there are no intervening live ranges between them in 801 // IntB, we can merge them. 802 if (ValLR+1 != BLR) return false; 803 804 DOUT << "\nExtending: "; IntB.print(DOUT, mri_); 805 806 // We are about to delete CopyMI, so need to remove it as the 'instruction 807 // that defines this value #'. 808 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0)); 809 810 // Okay, we can merge them. We need to insert a new liverange: 811 // [ValLR.end, BLR.begin) of either value number, then we merge the 812 // two value numbers. 813 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; 814 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 815 816 // If the IntB live range is assigned to a physical register, and if that 817 // physreg has aliases, 818 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { 819 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) { 820 LiveInterval &AliasLI = getInterval(*AS); 821 AliasLI.addRange(LiveRange(FillerStart, FillerEnd, 822 AliasLI.getNextValue(~0U, 0))); 823 } 824 } 825 826 // Okay, merge "B1" into the same value number as "B0". 827 if (BValNo != ValLR->ValId) 828 IntB.MergeValueNumberInto(BValNo, ValLR->ValId); 829 DOUT << " result = "; IntB.print(DOUT, mri_); 830 DOUT << "\n"; 831 832 // Finally, delete the copy instruction. 833 RemoveMachineInstrFromMaps(CopyMI); 834 CopyMI->eraseFromParent(); 835 ++numPeep; 836 return true; 837} 838 839/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 840/// which are the src/dst of the copy instruction CopyMI. This returns true 841/// if the copy was successfully coallesced away, or if it is never possible 842/// to coallesce these this copy, due to register constraints. It returns 843/// false if it is not currently possible to coallesce this interval, but 844/// it may be possible if other things get coallesced. 845bool LiveIntervals::JoinCopy(MachineInstr *CopyMI, 846 unsigned SrcReg, unsigned DstReg) { 847 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI; 848 849 // Get representative registers. 850 unsigned repSrcReg = rep(SrcReg); 851 unsigned repDstReg = rep(DstReg); 852 853 // If they are already joined we continue. 854 if (repSrcReg == repDstReg) { 855 DOUT << "\tCopy already coallesced.\n"; 856 return true; // Not coallescable. 857 } 858 859 // If they are both physical registers, we cannot join them. 860 if (MRegisterInfo::isPhysicalRegister(repSrcReg) && 861 MRegisterInfo::isPhysicalRegister(repDstReg)) { 862 DOUT << "\tCan not coallesce physregs.\n"; 863 return true; // Not coallescable. 864 } 865 866 // We only join virtual registers with allocatable physical registers. 867 if (MRegisterInfo::isPhysicalRegister(repSrcReg) && 868 !allocatableRegs_[repSrcReg]) { 869 DOUT << "\tSrc reg is unallocatable physreg.\n"; 870 return true; // Not coallescable. 871 } 872 if (MRegisterInfo::isPhysicalRegister(repDstReg) && 873 !allocatableRegs_[repDstReg]) { 874 DOUT << "\tDst reg is unallocatable physreg.\n"; 875 return true; // Not coallescable. 876 } 877 878 // If they are not of the same register class, we cannot join them. 879 if (differingRegisterClasses(repSrcReg, repDstReg)) { 880 DOUT << "\tSrc/Dest are different register classes.\n"; 881 return true; // Not coallescable. 882 } 883 884 LiveInterval &SrcInt = getInterval(repSrcReg); 885 LiveInterval &DestInt = getInterval(repDstReg); 886 assert(SrcInt.reg == repSrcReg && DestInt.reg == repDstReg && 887 "Register mapping is horribly broken!"); 888 889 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_); 890 DOUT << " and "; DestInt.print(DOUT, mri_); 891 DOUT << ": "; 892 893 // Check if it is necessary to propagate "isDead" property before intervals 894 // are joined. 895 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg); 896 bool isDead = mopd->isDead(); 897 unsigned SrcStart = 0; 898 unsigned SrcEnd = 0; 899 if (isDead) { 900 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 901 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx-1); 902 SrcStart = SrcLR->start; 903 SrcEnd = SrcLR->end; 904 if (hasRegisterUse(repSrcReg, SrcStart, SrcEnd)) 905 isDead = false; 906 } 907 908 // Okay, attempt to join these two intervals. On failure, this returns false. 909 // Otherwise, if one of the intervals being joined is a physreg, this method 910 // always canonicalizes DestInt to be it. The output "SrcInt" will not have 911 // been modified, so we can use this information below to update aliases. 912 if (JoinIntervals(DestInt, SrcInt)) { 913 if (isDead) { 914 // Result of the copy is dead. Propagate this property. 915 if (SrcStart == 0) { 916 // Live-in to the function but dead. Remove it from MBB live-in set. 917 // JoinIntervals may end up swapping the two intervals. 918 LiveInterval &LiveInInt = (repSrcReg == DestInt.reg) ? DestInt:SrcInt; 919 LiveInInt.removeRange(SrcStart, SrcEnd); 920 MachineBasicBlock *MBB = CopyMI->getParent(); 921 MBB->removeLiveIn(SrcReg); 922 } else { 923 MachineInstr *SrcMI = getInstructionFromIndex(SrcStart); 924 if (SrcMI) { 925 // FIXME: SrcMI == NULL means the register is livein to a non-entry 926 // MBB. Remove the range from its live interval? 927 MachineOperand *mops = SrcMI->findRegisterDefOperand(SrcReg); 928 if (mops) 929 // FIXME: mops == NULL means SrcMI defines a subregister? 930 mops->setIsDead(); 931 } 932 } 933 } 934 } else { 935 // Coallescing failed. 936 937 // If we can eliminate the copy without merging the live ranges, do so now. 938 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI)) 939 return true; 940 941 // Otherwise, we are unable to join the intervals. 942 DOUT << "Interference!\n"; 943 return false; 944 } 945 946 bool Swapped = repSrcReg == DestInt.reg; 947 if (Swapped) 948 std::swap(repSrcReg, repDstReg); 949 assert(MRegisterInfo::isVirtualRegister(repSrcReg) && 950 "LiveInterval::join didn't work right!"); 951 952 // If we're about to merge live ranges into a physical register live range, 953 // we have to update any aliased register's live ranges to indicate that they 954 // have clobbered values for this range. 955 if (MRegisterInfo::isPhysicalRegister(repDstReg)) { 956 for (const unsigned *AS = mri_->getAliasSet(repDstReg); *AS; ++AS) 957 getInterval(*AS).MergeInClobberRanges(SrcInt); 958 } 959 960 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_); 961 DOUT << "\n"; 962 963 // If the intervals were swapped by Join, swap them back so that the register 964 // mapping (in the r2i map) is correct. 965 if (Swapped) SrcInt.swap(DestInt); 966 967 // Live range has been lengthened due to colaescing, eliminate the 968 // unnecessary kills at the end of the source live ranges. 969 LiveVariables::VarInfo& vi = lv_->getVarInfo(repSrcReg); 970 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 971 MachineInstr *Kill = vi.Kills[i]; 972 if (Kill == CopyMI || isRemoved(Kill)) 973 continue; 974 if (DestInt.liveAt(getInstructionIndex(Kill) + InstrSlots::NUM)) 975 unsetRegisterKill(Kill, repSrcReg); 976 } 977 978 removeInterval(repSrcReg); 979 r2rMap_[repSrcReg] = repDstReg; 980 981 // Finally, delete the copy instruction. 982 RemoveMachineInstrFromMaps(CopyMI); 983 CopyMI->eraseFromParent(); 984 ++numPeep; 985 ++numJoins; 986 return true; 987} 988 989/// ComputeUltimateVN - Assuming we are going to join two live intervals, 990/// compute what the resultant value numbers for each value in the input two 991/// ranges will be. This is complicated by copies between the two which can 992/// and will commonly cause multiple value numbers to be merged into one. 993/// 994/// VN is the value number that we're trying to resolve. InstDefiningValue 995/// keeps track of the new InstDefiningValue assignment for the result 996/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 997/// whether a value in this or other is a copy from the opposite set. 998/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 999/// already been assigned. 1000/// 1001/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 1002/// contains the value number the copy is from. 1003/// 1004static unsigned ComputeUltimateVN(unsigned VN, 1005 SmallVector<std::pair<unsigned, 1006 unsigned>, 16> &ValueNumberInfo, 1007 SmallVector<int, 16> &ThisFromOther, 1008 SmallVector<int, 16> &OtherFromThis, 1009 SmallVector<int, 16> &ThisValNoAssignments, 1010 SmallVector<int, 16> &OtherValNoAssignments, 1011 LiveInterval &ThisLI, LiveInterval &OtherLI) { 1012 // If the VN has already been computed, just return it. 1013 if (ThisValNoAssignments[VN] >= 0) 1014 return ThisValNoAssignments[VN]; 1015// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); 1016 1017 // If this val is not a copy from the other val, then it must be a new value 1018 // number in the destination. 1019 int OtherValNo = ThisFromOther[VN]; 1020 if (OtherValNo == -1) { 1021 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN)); 1022 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1; 1023 } 1024 1025 // Otherwise, this *is* a copy from the RHS. If the other side has already 1026 // been computed, return it. 1027 if (OtherValNoAssignments[OtherValNo] >= 0) 1028 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo]; 1029 1030 // Mark this value number as currently being computed, then ask what the 1031 // ultimate value # of the other value is. 1032 ThisValNoAssignments[VN] = -2; 1033 unsigned UltimateVN = 1034 ComputeUltimateVN(OtherValNo, ValueNumberInfo, 1035 OtherFromThis, ThisFromOther, 1036 OtherValNoAssignments, ThisValNoAssignments, 1037 OtherLI, ThisLI); 1038 return ThisValNoAssignments[VN] = UltimateVN; 1039} 1040 1041static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) { 1042 return std::find(V.begin(), V.end(), Val) != V.end(); 1043} 1044 1045/// SimpleJoin - Attempt to joint the specified interval into this one. The 1046/// caller of this method must guarantee that the RHS only contains a single 1047/// value number and that the RHS is not defined by a copy from this 1048/// interval. This returns false if the intervals are not joinable, or it 1049/// joins them and returns true. 1050bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { 1051 assert(RHS.containsOneValue()); 1052 1053 // Some number (potentially more than one) value numbers in the current 1054 // interval may be defined as copies from the RHS. Scan the overlapping 1055 // portions of the LHS and RHS, keeping track of this and looking for 1056 // overlapping live ranges that are NOT defined as copies. If these exist, we 1057 // cannot coallesce. 1058 1059 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); 1060 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); 1061 1062 if (LHSIt->start < RHSIt->start) { 1063 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); 1064 if (LHSIt != LHS.begin()) --LHSIt; 1065 } else if (RHSIt->start < LHSIt->start) { 1066 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); 1067 if (RHSIt != RHS.begin()) --RHSIt; 1068 } 1069 1070 SmallVector<unsigned, 8> EliminatedLHSVals; 1071 1072 while (1) { 1073 // Determine if these live intervals overlap. 1074 bool Overlaps = false; 1075 if (LHSIt->start <= RHSIt->start) 1076 Overlaps = LHSIt->end > RHSIt->start; 1077 else 1078 Overlaps = RHSIt->end > LHSIt->start; 1079 1080 // If the live intervals overlap, there are two interesting cases: if the 1081 // LHS interval is defined by a copy from the RHS, it's ok and we record 1082 // that the LHS value # is the same as the RHS. If it's not, then we cannot 1083 // coallesce these live ranges and we bail out. 1084 if (Overlaps) { 1085 // If we haven't already recorded that this value # is safe, check it. 1086 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) { 1087 // Copy from the RHS? 1088 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId); 1089 if (rep(SrcReg) != RHS.reg) 1090 return false; // Nope, bail out. 1091 1092 EliminatedLHSVals.push_back(LHSIt->ValId); 1093 } 1094 1095 // We know this entire LHS live range is okay, so skip it now. 1096 if (++LHSIt == LHSEnd) break; 1097 continue; 1098 } 1099 1100 if (LHSIt->end < RHSIt->end) { 1101 if (++LHSIt == LHSEnd) break; 1102 } else { 1103 // One interesting case to check here. It's possible that we have 1104 // something like "X3 = Y" which defines a new value number in the LHS, 1105 // and is the last use of this liverange of the RHS. In this case, we 1106 // want to notice this copy (so that it gets coallesced away) even though 1107 // the live ranges don't actually overlap. 1108 if (LHSIt->start == RHSIt->end) { 1109 if (InVector(LHSIt->ValId, EliminatedLHSVals)) { 1110 // We already know that this value number is going to be merged in 1111 // if coallescing succeeds. Just skip the liverange. 1112 if (++LHSIt == LHSEnd) break; 1113 } else { 1114 // Otherwise, if this is a copy from the RHS, mark it as being merged 1115 // in. 1116 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) { 1117 EliminatedLHSVals.push_back(LHSIt->ValId); 1118 1119 // We know this entire LHS live range is okay, so skip it now. 1120 if (++LHSIt == LHSEnd) break; 1121 } 1122 } 1123 } 1124 1125 if (++RHSIt == RHSEnd) break; 1126 } 1127 } 1128 1129 // If we got here, we know that the coallescing will be successful and that 1130 // the value numbers in EliminatedLHSVals will all be merged together. Since 1131 // the most common case is that EliminatedLHSVals has a single number, we 1132 // optimize for it: if there is more than one value, we merge them all into 1133 // the lowest numbered one, then handle the interval as if we were merging 1134 // with one value number. 1135 unsigned LHSValNo; 1136 if (EliminatedLHSVals.size() > 1) { 1137 // Loop through all the equal value numbers merging them into the smallest 1138 // one. 1139 unsigned Smallest = EliminatedLHSVals[0]; 1140 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { 1141 if (EliminatedLHSVals[i] < Smallest) { 1142 // Merge the current notion of the smallest into the smaller one. 1143 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); 1144 Smallest = EliminatedLHSVals[i]; 1145 } else { 1146 // Merge into the smallest. 1147 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); 1148 } 1149 } 1150 LHSValNo = Smallest; 1151 } else { 1152 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); 1153 LHSValNo = EliminatedLHSVals[0]; 1154 } 1155 1156 // Okay, now that there is a single LHS value number that we're merging the 1157 // RHS into, update the value number info for the LHS to indicate that the 1158 // value number is defined where the RHS value number was. 1159 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0)); 1160 1161 // Okay, the final step is to loop over the RHS live intervals, adding them to 1162 // the LHS. 1163 LHS.MergeRangesInAsValue(RHS, LHSValNo); 1164 LHS.weight += RHS.weight; 1165 1166 return true; 1167} 1168 1169/// JoinIntervals - Attempt to join these two intervals. On failure, this 1170/// returns false. Otherwise, if one of the intervals being joined is a 1171/// physreg, this method always canonicalizes LHS to be it. The output 1172/// "RHS" will not have been modified, so we can use this information 1173/// below to update aliases. 1174bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) { 1175 // Compute the final value assignment, assuming that the live ranges can be 1176 // coallesced. 1177 SmallVector<int, 16> LHSValNoAssignments; 1178 SmallVector<int, 16> RHSValNoAssignments; 1179 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo; 1180 1181 // Compute ultimate value numbers for the LHS and RHS values. 1182 if (RHS.containsOneValue()) { 1183 // Copies from a liveinterval with a single value are simple to handle and 1184 // very common, handle the special case here. This is important, because 1185 // often RHS is small and LHS is large (e.g. a physreg). 1186 1187 // Find out if the RHS is defined as a copy from some value in the LHS. 1188 int RHSValID = -1; 1189 std::pair<unsigned,unsigned> RHSValNoInfo; 1190 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0); 1191 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { 1192 // If RHS is not defined as a copy from the LHS, we can use simpler and 1193 // faster checks to see if the live ranges are coallescable. This joiner 1194 // can't swap the LHS/RHS intervals though. 1195 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { 1196 return SimpleJoin(LHS, RHS); 1197 } else { 1198 RHSValNoInfo = RHS.getValNumInfo(0); 1199 } 1200 } else { 1201 // It was defined as a copy from the LHS, find out what value # it is. 1202 unsigned ValInst = RHS.getInstForValNum(0); 1203 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1204 RHSValNoInfo = LHS.getValNumInfo(RHSValID); 1205 } 1206 1207 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1208 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1209 ValueNumberInfo.resize(LHS.getNumValNums()); 1210 1211 // Okay, *all* of the values in LHS that are defined as a copy from RHS 1212 // should now get updated. 1213 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1214 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) { 1215 if (rep(LHSSrcReg) != RHS.reg) { 1216 // If this is not a copy from the RHS, its value number will be 1217 // unmodified by the coallescing. 1218 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1219 LHSValNoAssignments[VN] = VN; 1220 } else if (RHSValID == -1) { 1221 // Otherwise, it is a copy from the RHS, and we don't already have a 1222 // value# for it. Keep the current value number, but remember it. 1223 LHSValNoAssignments[VN] = RHSValID = VN; 1224 ValueNumberInfo[VN] = RHSValNoInfo; 1225 } else { 1226 // Otherwise, use the specified value #. 1227 LHSValNoAssignments[VN] = RHSValID; 1228 if (VN != (unsigned)RHSValID) 1229 ValueNumberInfo[VN].first = ~1U; 1230 else 1231 ValueNumberInfo[VN] = RHSValNoInfo; 1232 } 1233 } else { 1234 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1235 LHSValNoAssignments[VN] = VN; 1236 } 1237 } 1238 1239 assert(RHSValID != -1 && "Didn't find value #?"); 1240 RHSValNoAssignments[0] = RHSValID; 1241 1242 } else { 1243 // Loop over the value numbers of the LHS, seeing if any are defined from 1244 // the RHS. 1245 SmallVector<int, 16> LHSValsDefinedFromRHS; 1246 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1); 1247 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1248 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN); 1249 if (ValSrcReg == 0) // Src not defined by a copy? 1250 continue; 1251 1252 // DstReg is known to be a register in the LHS interval. If the src is 1253 // from the RHS interval, we can use its value #. 1254 if (rep(ValSrcReg) != RHS.reg) 1255 continue; 1256 1257 // Figure out the value # from the RHS. 1258 unsigned ValInst = LHS.getInstForValNum(VN); 1259 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId; 1260 } 1261 1262 // Loop over the value numbers of the RHS, seeing if any are defined from 1263 // the LHS. 1264 SmallVector<int, 16> RHSValsDefinedFromLHS; 1265 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1); 1266 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1267 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN); 1268 if (ValSrcReg == 0) // Src not defined by a copy? 1269 continue; 1270 1271 // DstReg is known to be a register in the RHS interval. If the src is 1272 // from the LHS interval, we can use its value #. 1273 if (rep(ValSrcReg) != LHS.reg) 1274 continue; 1275 1276 // Figure out the value # from the LHS. 1277 unsigned ValInst = RHS.getInstForValNum(VN); 1278 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1279 } 1280 1281 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1282 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1283 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1284 1285 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1286 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U) 1287 continue; 1288 ComputeUltimateVN(VN, ValueNumberInfo, 1289 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1290 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS); 1291 } 1292 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1293 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U) 1294 continue; 1295 // If this value number isn't a copy from the LHS, it's a new number. 1296 if (RHSValsDefinedFromLHS[VN] == -1) { 1297 ValueNumberInfo.push_back(RHS.getValNumInfo(VN)); 1298 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1; 1299 continue; 1300 } 1301 1302 ComputeUltimateVN(VN, ValueNumberInfo, 1303 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1304 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS); 1305 } 1306 } 1307 1308 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1309 // interval lists to see if these intervals are coallescable. 1310 LiveInterval::const_iterator I = LHS.begin(); 1311 LiveInterval::const_iterator IE = LHS.end(); 1312 LiveInterval::const_iterator J = RHS.begin(); 1313 LiveInterval::const_iterator JE = RHS.end(); 1314 1315 // Skip ahead until the first place of potential sharing. 1316 if (I->start < J->start) { 1317 I = std::upper_bound(I, IE, J->start); 1318 if (I != LHS.begin()) --I; 1319 } else if (J->start < I->start) { 1320 J = std::upper_bound(J, JE, I->start); 1321 if (J != RHS.begin()) --J; 1322 } 1323 1324 while (1) { 1325 // Determine if these two live ranges overlap. 1326 bool Overlaps; 1327 if (I->start < J->start) { 1328 Overlaps = I->end > J->start; 1329 } else { 1330 Overlaps = J->end > I->start; 1331 } 1332 1333 // If so, check value # info to determine if they are really different. 1334 if (Overlaps) { 1335 // If the live range overlap will map to the same value number in the 1336 // result liverange, we can still coallesce them. If not, we can't. 1337 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId]) 1338 return false; 1339 } 1340 1341 if (I->end < J->end) { 1342 ++I; 1343 if (I == IE) break; 1344 } else { 1345 ++J; 1346 if (J == JE) break; 1347 } 1348 } 1349 1350 // If we get here, we know that we can coallesce the live ranges. Ask the 1351 // intervals to coallesce themselves now. 1352 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], 1353 ValueNumberInfo); 1354 return true; 1355} 1356 1357 1358namespace { 1359 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1360 // depth of the basic block (the unsigned), and then on the MBB number. 1361 struct DepthMBBCompare { 1362 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1363 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1364 if (LHS.first > RHS.first) return true; // Deeper loops first 1365 return LHS.first == RHS.first && 1366 LHS.second->getNumber() < RHS.second->getNumber(); 1367 } 1368 }; 1369} 1370 1371 1372void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB, 1373 std::vector<CopyRec> &TryAgain) { 1374 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; 1375 1376 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1377 MII != E;) { 1378 MachineInstr *Inst = MII++; 1379 1380 // If this isn't a copy, we can't join intervals. 1381 unsigned SrcReg, DstReg; 1382 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; 1383 1384 if (!JoinCopy(Inst, SrcReg, DstReg)) 1385 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg)); 1386 } 1387} 1388 1389 1390void LiveIntervals::joinIntervals() { 1391 DOUT << "********** JOINING INTERVALS ***********\n"; 1392 1393 std::vector<CopyRec> TryAgainList; 1394 1395 const LoopInfo &LI = getAnalysis<LoopInfo>(); 1396 if (LI.begin() == LI.end()) { 1397 // If there are no loops in the function, join intervals in function order. 1398 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1399 I != E; ++I) 1400 CopyCoallesceInMBB(I, TryAgainList); 1401 } else { 1402 // Otherwise, join intervals in inner loops before other intervals. 1403 // Unfortunately we can't just iterate over loop hierarchy here because 1404 // there may be more MBB's than BB's. Collect MBB's for sorting. 1405 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1406 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1407 I != E; ++I) 1408 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 1409 1410 // Sort by loop depth. 1411 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1412 1413 // Finally, join intervals in loop nest order. 1414 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1415 CopyCoallesceInMBB(MBBs[i].second, TryAgainList); 1416 } 1417 1418 // Joining intervals can allow other intervals to be joined. Iteratively join 1419 // until we make no progress. 1420 bool ProgressMade = true; 1421 while (ProgressMade) { 1422 ProgressMade = false; 1423 1424 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1425 CopyRec &TheCopy = TryAgainList[i]; 1426 if (TheCopy.MI && 1427 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) { 1428 TheCopy.MI = 0; // Mark this one as done. 1429 ProgressMade = true; 1430 } 1431 } 1432 } 1433 1434 DOUT << "*** Register mapping ***\n"; 1435 for (int i = 0, e = r2rMap_.size(); i != e; ++i) 1436 if (r2rMap_[i]) { 1437 DOUT << " reg " << i << " -> "; 1438 DEBUG(printRegName(r2rMap_[i])); 1439 DOUT << "\n"; 1440 } 1441} 1442 1443/// Return true if the two specified registers belong to different register 1444/// classes. The registers may be either phys or virt regs. 1445bool LiveIntervals::differingRegisterClasses(unsigned RegA, 1446 unsigned RegB) const { 1447 1448 // Get the register classes for the first reg. 1449 if (MRegisterInfo::isPhysicalRegister(RegA)) { 1450 assert(MRegisterInfo::isVirtualRegister(RegB) && 1451 "Shouldn't consider two physregs!"); 1452 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 1453 } 1454 1455 // Compare against the regclass for the second reg. 1456 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 1457 if (MRegisterInfo::isVirtualRegister(RegB)) 1458 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 1459 else 1460 return !RegClass->contains(RegB); 1461} 1462 1463/// hasRegisterUse - Returns true if there is any use of the specific 1464/// reg between indexes Start and End. 1465bool 1466LiveIntervals::hasRegisterUse(unsigned Reg, unsigned Start, unsigned End) { 1467 for (unsigned Index = Start+InstrSlots::NUM; Index < End; 1468 Index += InstrSlots::NUM) { 1469 // Skip deleted instructions 1470 while (Index < End && !getInstructionFromIndex(Index)) 1471 Index += InstrSlots::NUM; 1472 if (Index >= End) break; 1473 1474 MachineInstr *MI = getInstructionFromIndex(Index); 1475 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1476 MachineOperand &MO = MI->getOperand(i); 1477 if (MO.isReg() && MO.isUse() && MO.getReg() && 1478 mri_->regsOverlap(rep(MO.getReg()), Reg)) 1479 return true; 1480 } 1481 } 1482 1483 return false; 1484} 1485 1486/// unsetRegisterKill - Unset IsKill property of all uses of specific register 1487/// of the specific instruction. 1488void LiveIntervals::unsetRegisterKill(MachineInstr *MI, unsigned Reg) { 1489 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1490 MachineOperand &MO = MI->getOperand(i); 1491 if (MO.isReg() && MO.isUse() && MO.isKill() && MO.getReg() && 1492 mri_->regsOverlap(rep(MO.getReg()), Reg)) 1493 MO.unsetIsKill(); 1494 } 1495} 1496 1497LiveInterval LiveIntervals::createInterval(unsigned reg) { 1498 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 1499 HUGE_VALF : 0.0F; 1500 return LiveInterval(reg, Weight); 1501} 1502