LiveIntervalAnalysis.cpp revision 38135af219c48a8626d6af34a92e7e8bb957c81f
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37using namespace llvm; 38 39namespace { 40 RegisterAnalysis<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 41 42 Statistic<> numIntervals 43 ("liveintervals", "Number of original intervals"); 44 45 Statistic<> numIntervalsAfter 46 ("liveintervals", "Number of intervals after coalescing"); 47 48 Statistic<> numJoins 49 ("liveintervals", "Number of interval joins performed"); 50 51 Statistic<> numPeep 52 ("liveintervals", "Number of identity moves eliminated after coalescing"); 53 54 Statistic<> numFolded 55 ("liveintervals", "Number of loads/stores folded into instructions"); 56 57 cl::opt<bool> 58 EnableJoining("join-liveintervals", 59 cl::desc("Join compatible live intervals"), 60 cl::init(true)); 61}; 62 63void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const 64{ 65 AU.addPreserved<LiveVariables>(); 66 AU.addRequired<LiveVariables>(); 67 AU.addPreservedID(PHIEliminationID); 68 AU.addRequiredID(PHIEliminationID); 69 AU.addRequiredID(TwoAddressInstructionPassID); 70 AU.addRequired<LoopInfo>(); 71 MachineFunctionPass::getAnalysisUsage(AU); 72} 73 74void LiveIntervals::releaseMemory() 75{ 76 mi2iMap_.clear(); 77 i2miMap_.clear(); 78 r2iMap_.clear(); 79 r2rMap_.clear(); 80} 81 82 83/// runOnMachineFunction - Register allocate the whole function 84/// 85bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 86 mf_ = &fn; 87 tm_ = &fn.getTarget(); 88 mri_ = tm_->getRegisterInfo(); 89 tii_ = tm_->getInstrInfo(); 90 lv_ = &getAnalysis<LiveVariables>(); 91 allocatableRegs_ = mri_->getAllocatableSet(fn); 92 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 93 94 // If this function has any live ins, insert a dummy instruction at the 95 // beginning of the function that we will pretend "defines" the values. This 96 // is to make the interval analysis simpler by providing a number. 97 if (fn.livein_begin() != fn.livein_end()) { 98 unsigned FirstLiveIn = fn.livein_begin()->first; 99 100 // Find a reg class that contains this live in. 101 const TargetRegisterClass *RC = 0; 102 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), 103 E = mri_->regclass_end(); RCI != E; ++RCI) 104 if ((*RCI)->contains(FirstLiveIn)) { 105 RC = *RCI; 106 break; 107 } 108 109 MachineInstr *OldFirstMI = fn.begin()->begin(); 110 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), 111 FirstLiveIn, FirstLiveIn, RC); 112 assert(OldFirstMI != fn.begin()->begin() && 113 "copyRetToReg didn't insert anything!"); 114 } 115 116 // number MachineInstrs 117 unsigned miIndex = 0; 118 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); 119 mbb != mbbEnd; ++mbb) 120 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 121 mi != miEnd; ++mi) { 122 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; 123 assert(inserted && "multiple MachineInstr -> index mappings"); 124 i2miMap_.push_back(mi); 125 miIndex += InstrSlots::NUM; 126 } 127 128 // Note intervals due to live-in values. 129 if (fn.livein_begin() != fn.livein_end()) { 130 MachineBasicBlock *Entry = fn.begin(); 131 for (MachineFunction::livein_iterator I = fn.livein_begin(), 132 E = fn.livein_end(); I != E; ++I) { 133 handlePhysicalRegisterDef(Entry, Entry->begin(), 134 getOrCreateInterval(I->first), 0, 0); 135 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) 136 handlePhysicalRegisterDef(Entry, Entry->begin(), 137 getOrCreateInterval(*AS), 0, 0); 138 } 139 } 140 141 computeIntervals(); 142 143 numIntervals += getNumIntervals(); 144 145 DEBUG(std::cerr << "********** INTERVALS **********\n"; 146 for (iterator I = begin(), E = end(); I != E; ++I) { 147 I->second.print(std::cerr, mri_); 148 std::cerr << "\n"; 149 }); 150 151 // join intervals if requested 152 if (EnableJoining) joinIntervals(); 153 154 numIntervalsAfter += getNumIntervals(); 155 156 // perform a final pass over the instructions and compute spill 157 // weights, coalesce virtual registers and remove identity moves 158 const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); 159 160 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 161 mbbi != mbbe; ++mbbi) { 162 MachineBasicBlock* mbb = mbbi; 163 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 164 165 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 166 mii != mie; ) { 167 // if the move will be an identity move delete it 168 unsigned srcReg, dstReg, RegRep; 169 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 170 (RegRep = rep(srcReg)) == rep(dstReg)) { 171 // remove from def list 172 LiveInterval &interval = getOrCreateInterval(RegRep); 173 // remove index -> MachineInstr and 174 // MachineInstr -> index mappings 175 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii); 176 if (mi2i != mi2iMap_.end()) { 177 i2miMap_[mi2i->second/InstrSlots::NUM] = 0; 178 mi2iMap_.erase(mi2i); 179 } 180 mii = mbbi->erase(mii); 181 ++numPeep; 182 } 183 else { 184 for (unsigned i = 0; i < mii->getNumOperands(); ++i) { 185 const MachineOperand& mop = mii->getOperand(i); 186 if (mop.isRegister() && mop.getReg() && 187 MRegisterInfo::isVirtualRegister(mop.getReg())) { 188 // replace register with representative register 189 unsigned reg = rep(mop.getReg()); 190 mii->SetMachineOperandReg(i, reg); 191 192 LiveInterval &RegInt = getInterval(reg); 193 RegInt.weight += 194 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 195 } 196 } 197 ++mii; 198 } 199 } 200 } 201 202 DEBUG(dump()); 203 return true; 204} 205 206/// print - Implement the dump method. 207void LiveIntervals::print(std::ostream &O, const Module* ) const { 208 O << "********** INTERVALS **********\n"; 209 for (const_iterator I = begin(), E = end(); I != E; ++I) 210 O << " " << I->second << "\n"; 211 212 O << "********** MACHINEINSTRS **********\n"; 213 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 214 mbbi != mbbe; ++mbbi) { 215 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 216 for (MachineBasicBlock::iterator mii = mbbi->begin(), 217 mie = mbbi->end(); mii != mie; ++mii) { 218 O << getInstructionIndex(mii) << '\t' << *mii; 219 } 220 } 221} 222 223std::vector<LiveInterval*> LiveIntervals:: 224addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 225 // since this is called after the analysis is done we don't know if 226 // LiveVariables is available 227 lv_ = getAnalysisToUpdate<LiveVariables>(); 228 229 std::vector<LiveInterval*> added; 230 231 assert(li.weight != HUGE_VAL && 232 "attempt to spill already spilled interval!"); 233 234 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: " 235 << li << '\n'); 236 237 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 238 239 for (LiveInterval::Ranges::const_iterator 240 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 241 unsigned index = getBaseIndex(i->start); 242 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 243 for (; index != end; index += InstrSlots::NUM) { 244 // skip deleted instructions 245 while (index != end && !getInstructionFromIndex(index)) 246 index += InstrSlots::NUM; 247 if (index == end) break; 248 249 MachineBasicBlock::iterator mi = getInstructionFromIndex(index); 250 251 for_operand: 252 for (unsigned i = 0; i != mi->getNumOperands(); ++i) { 253 MachineOperand& mop = mi->getOperand(i); 254 if (mop.isRegister() && mop.getReg() == li.reg) { 255 // First thing, attempt to fold the memory reference into the 256 // instruction. If we can do this, we don't need to insert spill 257 // code. 258 if (MachineInstr* fmi = mri_->foldMemoryOperand(mi, i, slot)) { 259 if (lv_) 260 lv_->instructionChanged(mi, fmi); 261 vrm.virtFolded(li.reg, mi, i, fmi); 262 mi2iMap_.erase(mi); 263 i2miMap_[index/InstrSlots::NUM] = fmi; 264 mi2iMap_[fmi] = index; 265 MachineBasicBlock &MBB = *mi->getParent(); 266 mi = MBB.insert(MBB.erase(mi), fmi); 267 ++numFolded; 268 269 // Folding the load/store can completely change the instruction in 270 // unpredictable ways, rescan it from the beginning. 271 goto for_operand; 272 } else { 273 // This is tricky. We need to add information in the interval about 274 // the spill code so we have to use our extra load/store slots. 275 // 276 // If we have a use we are going to have a load so we start the 277 // interval from the load slot onwards. Otherwise we start from the 278 // def slot. 279 unsigned start = (mop.isUse() ? 280 getLoadIndex(index) : 281 getDefIndex(index)); 282 // If we have a def we are going to have a store right after it so 283 // we end the interval after the use of the next 284 // instruction. Otherwise we end after the use of this instruction. 285 unsigned end = 1 + (mop.isDef() ? 286 getStoreIndex(index) : 287 getUseIndex(index)); 288 289 // create a new register for this spill 290 unsigned nReg = mf_->getSSARegMap()->createVirtualRegister(rc); 291 mi->SetMachineOperandReg(i, nReg); 292 vrm.grow(); 293 vrm.assignVirt2StackSlot(nReg, slot); 294 LiveInterval& nI = getOrCreateInterval(nReg); 295 assert(nI.empty()); 296 297 // the spill weight is now infinity as it 298 // cannot be spilled again 299 nI.weight = float(HUGE_VAL); 300 LiveRange LR(start, end, nI.getNextValue()); 301 DEBUG(std::cerr << " +" << LR); 302 nI.addRange(LR); 303 added.push_back(&nI); 304 305 // update live variables if it is available 306 if (lv_) 307 lv_->addVirtualRegisterKilled(nReg, mi); 308 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n'); 309 } 310 } 311 } 312 } 313 } 314 315 return added; 316} 317 318void LiveIntervals::printRegName(unsigned reg) const 319{ 320 if (MRegisterInfo::isPhysicalRegister(reg)) 321 std::cerr << mri_->getName(reg); 322 else 323 std::cerr << "%reg" << reg; 324} 325 326void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb, 327 MachineBasicBlock::iterator mi, 328 LiveInterval& interval) 329{ 330 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 331 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 332 333 // Virtual registers may be defined multiple times (due to phi 334 // elimination and 2-addr elimination). Much of what we do only has to be 335 // done once for the vreg. We use an empty interval to detect the first 336 // time we see a vreg. 337 if (interval.empty()) { 338 // Get the Idx of the defining instructions. 339 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 340 341 unsigned ValNum = interval.getNextValue(); 342 assert(ValNum == 0 && "First value in interval is not 0?"); 343 ValNum = 0; // Clue in the optimizer. 344 345 // Loop over all of the blocks that the vreg is defined in. There are 346 // two cases we have to handle here. The most common case is a vreg 347 // whose lifetime is contained within a basic block. In this case there 348 // will be a single kill, in MBB, which comes after the definition. 349 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 350 // FIXME: what about dead vars? 351 unsigned killIdx; 352 if (vi.Kills[0] != mi) 353 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 354 else 355 killIdx = defIndex+1; 356 357 // If the kill happens after the definition, we have an intra-block 358 // live range. 359 if (killIdx > defIndex) { 360 assert(vi.AliveBlocks.empty() && 361 "Shouldn't be alive across any blocks!"); 362 LiveRange LR(defIndex, killIdx, ValNum); 363 interval.addRange(LR); 364 DEBUG(std::cerr << " +" << LR << "\n"); 365 return; 366 } 367 } 368 369 // The other case we handle is when a virtual register lives to the end 370 // of the defining block, potentially live across some blocks, then is 371 // live into some number of blocks, but gets killed. Start by adding a 372 // range that goes from this definition to the end of the defining block. 373 LiveRange NewLR(defIndex, 374 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 375 ValNum); 376 DEBUG(std::cerr << " +" << NewLR); 377 interval.addRange(NewLR); 378 379 // Iterate over all of the blocks that the variable is completely 380 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 381 // live interval. 382 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 383 if (vi.AliveBlocks[i]) { 384 MachineBasicBlock* mbb = mf_->getBlockNumbered(i); 385 if (!mbb->empty()) { 386 LiveRange LR(getInstructionIndex(&mbb->front()), 387 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 388 ValNum); 389 interval.addRange(LR); 390 DEBUG(std::cerr << " +" << LR); 391 } 392 } 393 } 394 395 // Finally, this virtual register is live from the start of any killing 396 // block to the 'use' slot of the killing instruction. 397 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 398 MachineInstr *Kill = vi.Kills[i]; 399 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), 400 getUseIndex(getInstructionIndex(Kill))+1, 401 ValNum); 402 interval.addRange(LR); 403 DEBUG(std::cerr << " +" << LR); 404 } 405 406 } else { 407 // If this is the second time we see a virtual register definition, it 408 // must be due to phi elimination or two addr elimination. If this is 409 // the result of two address elimination, then the vreg is the first 410 // operand, and is a def-and-use. 411 if (mi->getOperand(0).isRegister() && 412 mi->getOperand(0).getReg() == interval.reg && 413 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { 414 // If this is a two-address definition, then we have already processed 415 // the live range. The only problem is that we didn't realize there 416 // are actually two values in the live interval. Because of this we 417 // need to take the LiveRegion that defines this register and split it 418 // into two values. 419 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 420 unsigned RedefIndex = getDefIndex(getInstructionIndex(mi)); 421 422 // Delete the initial value, which should be short and continuous, 423 // becuase the 2-addr copy must be in the same MBB as the redef. 424 interval.removeRange(DefIndex, RedefIndex); 425 426 LiveRange LR(DefIndex, RedefIndex, interval.getNextValue()); 427 DEBUG(std::cerr << " replace range with " << LR); 428 interval.addRange(LR); 429 430 // If this redefinition is dead, we need to add a dummy unit live 431 // range covering the def slot. 432 for (LiveVariables::killed_iterator KI = lv_->dead_begin(mi), 433 E = lv_->dead_end(mi); KI != E; ++KI) 434 if (KI->second == interval.reg) { 435 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 436 break; 437 } 438 439 DEBUG(std::cerr << "RESULT: " << interval); 440 441 } else { 442 // Otherwise, this must be because of phi elimination. If this is the 443 // first redefinition of the vreg that we have seen, go back and change 444 // the live range in the PHI block to be a different value number. 445 if (interval.containsOneValue()) { 446 assert(vi.Kills.size() == 1 && 447 "PHI elimination vreg should have one kill, the PHI itself!"); 448 449 // Remove the old range that we now know has an incorrect number. 450 MachineInstr *Killer = vi.Kills[0]; 451 unsigned Start = getInstructionIndex(Killer->getParent()->begin()); 452 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 453 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: " 454 << interval << "\n"); 455 interval.removeRange(Start, End); 456 DEBUG(std::cerr << "RESULT: " << interval); 457 458 // Replace the interval with one of a NEW value number. 459 LiveRange LR(Start, End, interval.getNextValue()); 460 DEBUG(std::cerr << " replace range with " << LR); 461 interval.addRange(LR); 462 DEBUG(std::cerr << "RESULT: " << interval); 463 } 464 465 // In the case of PHI elimination, each variable definition is only 466 // live until the end of the block. We've already taken care of the 467 // rest of the live range. 468 unsigned defIndex = getDefIndex(getInstructionIndex(mi)); 469 LiveRange LR(defIndex, 470 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 471 interval.getNextValue()); 472 interval.addRange(LR); 473 DEBUG(std::cerr << " +" << LR); 474 } 475 } 476 477 DEBUG(std::cerr << '\n'); 478} 479 480void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 481 MachineBasicBlock::iterator mi, 482 LiveInterval& interval, 483 unsigned SrcReg, unsigned DestReg) 484{ 485 // A physical register cannot be live across basic block, so its 486 // lifetime must end somewhere in its defining basic block. 487 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 488 typedef LiveVariables::killed_iterator KillIter; 489 490 unsigned baseIndex = getInstructionIndex(mi); 491 unsigned start = getDefIndex(baseIndex); 492 unsigned end = start; 493 494 // If it is not used after definition, it is considered dead at 495 // the instruction defining it. Hence its interval is: 496 // [defSlot(def), defSlot(def)+1) 497 for (KillIter ki = lv_->dead_begin(mi), ke = lv_->dead_end(mi); 498 ki != ke; ++ki) { 499 if (interval.reg == ki->second) { 500 DEBUG(std::cerr << " dead"); 501 end = getDefIndex(start) + 1; 502 goto exit; 503 } 504 } 505 506 // If it is not dead on definition, it must be killed by a 507 // subsequent instruction. Hence its interval is: 508 // [defSlot(def), useSlot(kill)+1) 509 while (true) { 510 ++mi; 511 assert(mi != MBB->end() && "physreg was not killed in defining block!"); 512 baseIndex += InstrSlots::NUM; 513 for (KillIter ki = lv_->killed_begin(mi), ke = lv_->killed_end(mi); 514 ki != ke; ++ki) { 515 if (interval.reg == ki->second) { 516 DEBUG(std::cerr << " killed"); 517 end = getUseIndex(baseIndex) + 1; 518 goto exit; 519 } 520 } 521 } 522 523exit: 524 assert(start < end && "did not find end of interval?"); 525 526 // Finally, if this is defining a new range for the physical register, and if 527 // that physreg is just a copy from a vreg, and if THAT vreg was a copy from 528 // the physreg, then the new fragment has the same value as the one copied 529 // into the vreg. 530 if (interval.reg == DestReg && !interval.empty() && 531 MRegisterInfo::isVirtualRegister(SrcReg)) { 532 533 // Get the live interval for the vreg, see if it is defined by a copy. 534 LiveInterval &SrcInterval = getOrCreateInterval(SrcReg); 535 536 if (SrcInterval.containsOneValue()) { 537 assert(!SrcInterval.empty() && "Can't contain a value and be empty!"); 538 539 // Get the first index of the first range. Though the interval may have 540 // multiple liveranges in it, we only check the first. 541 unsigned StartIdx = SrcInterval.begin()->start; 542 MachineInstr *SrcDefMI = getInstructionFromIndex(StartIdx); 543 544 // Check to see if the vreg was defined by a copy instruction, and that 545 // the source was this physreg. 546 unsigned VRegSrcSrc, VRegSrcDest; 547 if (tii_->isMoveInstr(*SrcDefMI, VRegSrcSrc, VRegSrcDest) && 548 SrcReg == VRegSrcDest && VRegSrcSrc == DestReg) { 549 // Okay, now we know that the vreg was defined by a copy from this 550 // physreg. Find the value number being copied and use it as the value 551 // for this range. 552 const LiveRange *DefRange = interval.getLiveRangeContaining(StartIdx-1); 553 if (DefRange) { 554 LiveRange LR(start, end, DefRange->ValId); 555 interval.addRange(LR); 556 DEBUG(std::cerr << " +" << LR << '\n'); 557 return; 558 } 559 } 560 } 561 } 562 563 564 LiveRange LR(start, end, interval.getNextValue()); 565 interval.addRange(LR); 566 DEBUG(std::cerr << " +" << LR << '\n'); 567} 568 569void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 570 MachineBasicBlock::iterator MI, 571 unsigned reg) { 572 if (MRegisterInfo::isVirtualRegister(reg)) 573 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg)); 574 else if (allocatableRegs_[reg]) { 575 unsigned SrcReg = 0, DestReg = 0; 576 bool IsMove = tii_->isMoveInstr(*MI, SrcReg, DestReg); 577 578 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg), 579 SrcReg, DestReg); 580 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 581 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS), 582 SrcReg, DestReg); 583 } 584} 585 586/// computeIntervals - computes the live intervals for virtual 587/// registers. for some ordering of the machine instructions [1,N] a 588/// live interval is an interval [i, j) where 1 <= i <= j < N for 589/// which a variable is live 590void LiveIntervals::computeIntervals() 591{ 592 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 593 DEBUG(std::cerr << "********** Function: " 594 << ((Value*)mf_->getFunction())->getName() << '\n'); 595 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); 596 597 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 598 I != E; ++I) { 599 MachineBasicBlock* mbb = I; 600 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); 601 602 MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 603 if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; } 604 for (; mi != miEnd; ++mi) { 605 const TargetInstrDescriptor& tid = 606 tm_->getInstrInfo()->get(mi->getOpcode()); 607 DEBUG(std::cerr << getInstructionIndex(mi) << "\t" << *mi); 608 609 // handle implicit defs 610 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) 611 handleRegisterDef(mbb, mi, *id); 612 613 // handle explicit defs 614 for (int i = mi->getNumOperands() - 1; i >= 0; --i) { 615 MachineOperand& mop = mi->getOperand(i); 616 // handle register defs - build intervals 617 if (mop.isRegister() && mop.getReg() && mop.isDef()) 618 handleRegisterDef(mbb, mi, mop.getReg()); 619 } 620 } 621 } 622} 623 624void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) { 625 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 626 627 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end(); 628 mi != mie; ++mi) { 629 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi); 630 631 // we only join virtual registers with allocatable 632 // physical registers since we do not have liveness information 633 // on not allocatable physical registers 634 unsigned regA, regB; 635 if (tii_->isMoveInstr(*mi, regA, regB) && 636 (MRegisterInfo::isVirtualRegister(regA) || allocatableRegs_[regA]) && 637 (MRegisterInfo::isVirtualRegister(regB) || allocatableRegs_[regB])) { 638 639 // Get representative registers. 640 regA = rep(regA); 641 regB = rep(regB); 642 643 // If they are already joined we continue. 644 if (regA == regB) 645 continue; 646 647 // If they are both physical registers, we cannot join them. 648 if (MRegisterInfo::isPhysicalRegister(regA) && 649 MRegisterInfo::isPhysicalRegister(regB)) 650 continue; 651 652 // If they are not of the same register class, we cannot join them. 653 if (differingRegisterClasses(regA, regB)) 654 continue; 655 656 LiveInterval &IntA = getInterval(regA); 657 LiveInterval &IntB = getInterval(regB); 658 assert(IntA.reg == regA && IntB.reg == regB && 659 "Register mapping is horribly broken!"); 660 661 DEBUG(std::cerr << "\t\tInspecting " << IntA << " and " << IntB << ": "); 662 663 // If two intervals contain a single value and are joined by a copy, it 664 // does not matter if the intervals overlap, they can always be joined. 665 bool TriviallyJoinable = 666 IntA.containsOneValue() && IntB.containsOneValue(); 667 668 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi)); 669 if ((TriviallyJoinable || IntB.joinable(IntA, MIDefIdx)) && 670 !overlapsAliases(&IntA, &IntB)) { 671 IntB.join(IntA, MIDefIdx); 672 673 if (!MRegisterInfo::isPhysicalRegister(regA)) { 674 r2iMap_.erase(regA); 675 r2rMap_[regA] = regB; 676 } else { 677 // Otherwise merge the data structures the other way so we don't lose 678 // the physreg information. 679 r2rMap_[regB] = regA; 680 IntB.reg = regA; 681 IntA.swap(IntB); 682 r2iMap_.erase(regB); 683 } 684 DEBUG(std::cerr << "Joined. Result = " << IntB << "\n"); 685 ++numJoins; 686 } else { 687 DEBUG(std::cerr << "Interference!\n"); 688 } 689 } 690 } 691} 692 693namespace { 694 // DepthMBBCompare - Comparison predicate that sort first based on the loop 695 // depth of the basic block (the unsigned), and then on the MBB number. 696 struct DepthMBBCompare { 697 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 698 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 699 if (LHS.first > RHS.first) return true; // Deeper loops first 700 return LHS.first == RHS.first && 701 LHS.second->getNumber() < RHS.second->getNumber(); 702 } 703 }; 704} 705 706void LiveIntervals::joinIntervals() { 707 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 708 709 const LoopInfo &LI = getAnalysis<LoopInfo>(); 710 if (LI.begin() == LI.end()) { 711 // If there are no loops in the function, join intervals in function order. 712 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 713 I != E; ++I) 714 joinIntervalsInMachineBB(I); 715 } else { 716 // Otherwise, join intervals in inner loops before other intervals. 717 // Unfortunately we can't just iterate over loop hierarchy here because 718 // there may be more MBB's than BB's. Collect MBB's for sorting. 719 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 720 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 721 I != E; ++I) 722 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 723 724 // Sort by loop depth. 725 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 726 727 // Finally, join intervals in loop nest order. 728 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 729 joinIntervalsInMachineBB(MBBs[i].second); 730 } 731 732 DEBUG(std::cerr << "*** Register mapping ***\n"); 733 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) 734 if (r2rMap_[i]) 735 std::cerr << " reg " << i << " -> reg " << r2rMap_[i] << "\n"); 736} 737 738/// Return true if the two specified registers belong to different register 739/// classes. The registers may be either phys or virt regs. 740bool LiveIntervals::differingRegisterClasses(unsigned RegA, 741 unsigned RegB) const { 742 743 // Get the register classes for the first reg. 744 if (MRegisterInfo::isPhysicalRegister(RegA)) { 745 assert(MRegisterInfo::isVirtualRegister(RegB) && 746 "Shouldn't consider two physregs!"); 747 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 748 } 749 750 // Compare against the regclass for the second reg. 751 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 752 if (MRegisterInfo::isVirtualRegister(RegB)) 753 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 754 else 755 return !RegClass->contains(RegB); 756} 757 758bool LiveIntervals::overlapsAliases(const LiveInterval *LHS, 759 const LiveInterval *RHS) const { 760 if (!MRegisterInfo::isPhysicalRegister(LHS->reg)) { 761 if (!MRegisterInfo::isPhysicalRegister(RHS->reg)) 762 return false; // vreg-vreg merge has no aliases! 763 std::swap(LHS, RHS); 764 } 765 766 assert(MRegisterInfo::isPhysicalRegister(LHS->reg) && 767 MRegisterInfo::isVirtualRegister(RHS->reg) && 768 "first interval must describe a physical register"); 769 770 for (const unsigned *AS = mri_->getAliasSet(LHS->reg); *AS; ++AS) 771 if (RHS->overlaps(getInterval(*AS))) 772 return true; 773 774 return false; 775} 776 777LiveInterval LiveIntervals::createInterval(unsigned reg) { 778 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 779 (float)HUGE_VAL :0.0F; 780 return LiveInterval(reg, Weight); 781} 782