LiveIntervalAnalysis.cpp revision 428b92eb83b457b71d29d1d4b7900d36a0ce9a53
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37#include <iostream> 38using namespace llvm; 39 40namespace { 41 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 42 43 static Statistic<> numIntervals 44 ("liveintervals", "Number of original intervals"); 45 46 static Statistic<> numIntervalsAfter 47 ("liveintervals", "Number of intervals after coalescing"); 48 49 static Statistic<> numJoins 50 ("liveintervals", "Number of interval joins performed"); 51 52 static Statistic<> numPeep 53 ("liveintervals", "Number of identity moves eliminated after coalescing"); 54 55 static Statistic<> numFolded 56 ("liveintervals", "Number of loads/stores folded into instructions"); 57 58 static cl::opt<bool> 59 EnableJoining("join-liveintervals", 60 cl::desc("Coallesce copies (default=true)"), 61 cl::init(true)); 62} 63 64void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 65 AU.addRequired<LiveVariables>(); 66 AU.addPreservedID(PHIEliminationID); 67 AU.addRequiredID(PHIEliminationID); 68 AU.addRequiredID(TwoAddressInstructionPassID); 69 AU.addRequired<LoopInfo>(); 70 MachineFunctionPass::getAnalysisUsage(AU); 71} 72 73void LiveIntervals::releaseMemory() { 74 mi2iMap_.clear(); 75 i2miMap_.clear(); 76 r2iMap_.clear(); 77 r2rMap_.clear(); 78} 79 80 81static bool isZeroLengthInterval(LiveInterval *li) { 82 for (LiveInterval::Ranges::const_iterator 83 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) 84 if (i->end - i->start > LiveIntervals::InstrSlots::NUM) 85 return false; 86 return true; 87} 88 89 90/// runOnMachineFunction - Register allocate the whole function 91/// 92bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 93 mf_ = &fn; 94 tm_ = &fn.getTarget(); 95 mri_ = tm_->getRegisterInfo(); 96 tii_ = tm_->getInstrInfo(); 97 lv_ = &getAnalysis<LiveVariables>(); 98 allocatableRegs_ = mri_->getAllocatableSet(fn); 99 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 100 101 // If this function has any live ins, insert a dummy instruction at the 102 // beginning of the function that we will pretend "defines" the values. This 103 // is to make the interval analysis simpler by providing a number. 104 if (fn.livein_begin() != fn.livein_end()) { 105 unsigned FirstLiveIn = fn.livein_begin()->first; 106 107 // Find a reg class that contains this live in. 108 const TargetRegisterClass *RC = 0; 109 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), 110 E = mri_->regclass_end(); RCI != E; ++RCI) 111 if ((*RCI)->contains(FirstLiveIn)) { 112 RC = *RCI; 113 break; 114 } 115 116 MachineInstr *OldFirstMI = fn.begin()->begin(); 117 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), 118 FirstLiveIn, FirstLiveIn, RC); 119 assert(OldFirstMI != fn.begin()->begin() && 120 "copyRetToReg didn't insert anything!"); 121 } 122 123 // Number MachineInstrs and MachineBasicBlocks. 124 // Initialize MBB indexes to a sentinal. 125 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U); 126 127 unsigned MIIndex = 0; 128 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); 129 MBB != E; ++MBB) { 130 // Set the MBB2IdxMap entry for this MBB. 131 MBB2IdxMap[MBB->getNumber()] = MIIndex; 132 133 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 134 I != E; ++I) { 135 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second; 136 assert(inserted && "multiple MachineInstr -> index mappings"); 137 i2miMap_.push_back(I); 138 MIIndex += InstrSlots::NUM; 139 } 140 } 141 142 // Note intervals due to live-in values. 143 if (fn.livein_begin() != fn.livein_end()) { 144 MachineBasicBlock *Entry = fn.begin(); 145 for (MachineFunction::livein_iterator I = fn.livein_begin(), 146 E = fn.livein_end(); I != E; ++I) { 147 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 148 getOrCreateInterval(I->first), 0); 149 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) 150 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 151 getOrCreateInterval(*AS), 0); 152 } 153 } 154 155 computeIntervals(); 156 157 numIntervals += getNumIntervals(); 158 159 DEBUG(std::cerr << "********** INTERVALS **********\n"; 160 for (iterator I = begin(), E = end(); I != E; ++I) { 161 I->second.print(std::cerr, mri_); 162 std::cerr << "\n"; 163 }); 164 165 // Join (coallesce) intervals if requested. 166 if (EnableJoining) joinIntervals(); 167 168 numIntervalsAfter += getNumIntervals(); 169 170 171 // perform a final pass over the instructions and compute spill 172 // weights, coalesce virtual registers and remove identity moves. 173 const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); 174 175 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 176 mbbi != mbbe; ++mbbi) { 177 MachineBasicBlock* mbb = mbbi; 178 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 179 180 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 181 mii != mie; ) { 182 // if the move will be an identity move delete it 183 unsigned srcReg, dstReg, RegRep; 184 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 185 (RegRep = rep(srcReg)) == rep(dstReg)) { 186 // remove from def list 187 LiveInterval &interval = getOrCreateInterval(RegRep); 188 RemoveMachineInstrFromMaps(mii); 189 mii = mbbi->erase(mii); 190 ++numPeep; 191 } 192 else { 193 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { 194 const MachineOperand &mop = mii->getOperand(i); 195 if (mop.isRegister() && mop.getReg() && 196 MRegisterInfo::isVirtualRegister(mop.getReg())) { 197 // replace register with representative register 198 unsigned reg = rep(mop.getReg()); 199 mii->getOperand(i).setReg(reg); 200 201 LiveInterval &RegInt = getInterval(reg); 202 RegInt.weight += 203 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 204 } 205 } 206 ++mii; 207 } 208 } 209 } 210 211 for (iterator I = begin(), E = end(); I != E; ++I) { 212 LiveInterval &li = I->second; 213 if (MRegisterInfo::isVirtualRegister(li.reg)) { 214 // If the live interval length is essentially zero, i.e. in every live 215 // range the use follows def immediately, it doesn't make sense to spill 216 // it and hope it will be easier to allocate for this li. 217 if (isZeroLengthInterval(&li)) 218 li.weight = float(HUGE_VAL); 219 } 220 } 221 222 DEBUG(dump()); 223 return true; 224} 225 226/// print - Implement the dump method. 227void LiveIntervals::print(std::ostream &O, const Module* ) const { 228 O << "********** INTERVALS **********\n"; 229 for (const_iterator I = begin(), E = end(); I != E; ++I) { 230 I->second.print(std::cerr, mri_); 231 std::cerr << "\n"; 232 } 233 234 O << "********** MACHINEINSTRS **********\n"; 235 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 236 mbbi != mbbe; ++mbbi) { 237 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 238 for (MachineBasicBlock::iterator mii = mbbi->begin(), 239 mie = mbbi->end(); mii != mie; ++mii) { 240 O << getInstructionIndex(mii) << '\t' << *mii; 241 } 242 } 243} 244 245std::vector<LiveInterval*> LiveIntervals:: 246addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 247 // since this is called after the analysis is done we don't know if 248 // LiveVariables is available 249 lv_ = getAnalysisToUpdate<LiveVariables>(); 250 251 std::vector<LiveInterval*> added; 252 253 assert(li.weight != HUGE_VAL && 254 "attempt to spill already spilled interval!"); 255 256 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "; 257 li.print(std::cerr, mri_); std::cerr << '\n'); 258 259 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 260 261 for (LiveInterval::Ranges::const_iterator 262 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 263 unsigned index = getBaseIndex(i->start); 264 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 265 for (; index != end; index += InstrSlots::NUM) { 266 // skip deleted instructions 267 while (index != end && !getInstructionFromIndex(index)) 268 index += InstrSlots::NUM; 269 if (index == end) break; 270 271 MachineInstr *MI = getInstructionFromIndex(index); 272 273 RestartInstruction: 274 for (unsigned i = 0; i != MI->getNumOperands(); ++i) { 275 MachineOperand& mop = MI->getOperand(i); 276 if (mop.isRegister() && mop.getReg() == li.reg) { 277 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) { 278 // Attempt to fold the memory reference into the instruction. If we 279 // can do this, we don't need to insert spill code. 280 if (lv_) 281 lv_->instructionChanged(MI, fmi); 282 MachineBasicBlock &MBB = *MI->getParent(); 283 vrm.virtFolded(li.reg, MI, i, fmi); 284 mi2iMap_.erase(MI); 285 i2miMap_[index/InstrSlots::NUM] = fmi; 286 mi2iMap_[fmi] = index; 287 MI = MBB.insert(MBB.erase(MI), fmi); 288 ++numFolded; 289 // Folding the load/store can completely change the instruction in 290 // unpredictable ways, rescan it from the beginning. 291 goto RestartInstruction; 292 } else { 293 // Create a new virtual register for the spill interval. 294 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc); 295 296 // Scan all of the operands of this instruction rewriting operands 297 // to use NewVReg instead of li.reg as appropriate. We do this for 298 // two reasons: 299 // 300 // 1. If the instr reads the same spilled vreg multiple times, we 301 // want to reuse the NewVReg. 302 // 2. If the instr is a two-addr instruction, we are required to 303 // keep the src/dst regs pinned. 304 // 305 // Keep track of whether we replace a use and/or def so that we can 306 // create the spill interval with the appropriate range. 307 mop.setReg(NewVReg); 308 309 bool HasUse = mop.isUse(); 310 bool HasDef = mop.isDef(); 311 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { 312 if (MI->getOperand(j).isReg() && 313 MI->getOperand(j).getReg() == li.reg) { 314 MI->getOperand(j).setReg(NewVReg); 315 HasUse |= MI->getOperand(j).isUse(); 316 HasDef |= MI->getOperand(j).isDef(); 317 } 318 } 319 320 // create a new register for this spill 321 vrm.grow(); 322 vrm.assignVirt2StackSlot(NewVReg, slot); 323 LiveInterval &nI = getOrCreateInterval(NewVReg); 324 assert(nI.empty()); 325 326 // the spill weight is now infinity as it 327 // cannot be spilled again 328 nI.weight = float(HUGE_VAL); 329 330 if (HasUse) { 331 LiveRange LR(getLoadIndex(index), getUseIndex(index), 332 nI.getNextValue(~0U, 0)); 333 DEBUG(std::cerr << " +" << LR); 334 nI.addRange(LR); 335 } 336 if (HasDef) { 337 LiveRange LR(getDefIndex(index), getStoreIndex(index), 338 nI.getNextValue(~0U, 0)); 339 DEBUG(std::cerr << " +" << LR); 340 nI.addRange(LR); 341 } 342 343 added.push_back(&nI); 344 345 // update live variables if it is available 346 if (lv_) 347 lv_->addVirtualRegisterKilled(NewVReg, MI); 348 349 DEBUG(std::cerr << "\t\t\t\tadded new interval: "; 350 nI.print(std::cerr, mri_); std::cerr << '\n'); 351 } 352 } 353 } 354 } 355 } 356 357 return added; 358} 359 360void LiveIntervals::printRegName(unsigned reg) const { 361 if (MRegisterInfo::isPhysicalRegister(reg)) 362 std::cerr << mri_->getName(reg); 363 else 364 std::cerr << "%reg" << reg; 365} 366 367void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 368 MachineBasicBlock::iterator mi, 369 unsigned MIIdx, 370 LiveInterval &interval) { 371 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 372 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 373 374 // Virtual registers may be defined multiple times (due to phi 375 // elimination and 2-addr elimination). Much of what we do only has to be 376 // done once for the vreg. We use an empty interval to detect the first 377 // time we see a vreg. 378 if (interval.empty()) { 379 // Get the Idx of the defining instructions. 380 unsigned defIndex = getDefIndex(MIIdx); 381 382 unsigned ValNum; 383 unsigned SrcReg, DstReg; 384 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 385 ValNum = interval.getNextValue(~0U, 0); 386 else 387 ValNum = interval.getNextValue(defIndex, SrcReg); 388 389 assert(ValNum == 0 && "First value in interval is not 0?"); 390 ValNum = 0; // Clue in the optimizer. 391 392 // Loop over all of the blocks that the vreg is defined in. There are 393 // two cases we have to handle here. The most common case is a vreg 394 // whose lifetime is contained within a basic block. In this case there 395 // will be a single kill, in MBB, which comes after the definition. 396 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 397 // FIXME: what about dead vars? 398 unsigned killIdx; 399 if (vi.Kills[0] != mi) 400 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 401 else 402 killIdx = defIndex+1; 403 404 // If the kill happens after the definition, we have an intra-block 405 // live range. 406 if (killIdx > defIndex) { 407 assert(vi.AliveBlocks.empty() && 408 "Shouldn't be alive across any blocks!"); 409 LiveRange LR(defIndex, killIdx, ValNum); 410 interval.addRange(LR); 411 DEBUG(std::cerr << " +" << LR << "\n"); 412 return; 413 } 414 } 415 416 // The other case we handle is when a virtual register lives to the end 417 // of the defining block, potentially live across some blocks, then is 418 // live into some number of blocks, but gets killed. Start by adding a 419 // range that goes from this definition to the end of the defining block. 420 LiveRange NewLR(defIndex, 421 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 422 ValNum); 423 DEBUG(std::cerr << " +" << NewLR); 424 interval.addRange(NewLR); 425 426 // Iterate over all of the blocks that the variable is completely 427 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 428 // live interval. 429 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 430 if (vi.AliveBlocks[i]) { 431 MachineBasicBlock *MBB = mf_->getBlockNumbered(i); 432 if (!MBB->empty()) { 433 LiveRange LR(getMBBStartIdx(i), 434 getInstructionIndex(&MBB->back()) + InstrSlots::NUM, 435 ValNum); 436 interval.addRange(LR); 437 DEBUG(std::cerr << " +" << LR); 438 } 439 } 440 } 441 442 // Finally, this virtual register is live from the start of any killing 443 // block to the 'use' slot of the killing instruction. 444 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 445 MachineInstr *Kill = vi.Kills[i]; 446 LiveRange LR(getMBBStartIdx(Kill->getParent()), 447 getUseIndex(getInstructionIndex(Kill))+1, 448 ValNum); 449 interval.addRange(LR); 450 DEBUG(std::cerr << " +" << LR); 451 } 452 453 } else { 454 // If this is the second time we see a virtual register definition, it 455 // must be due to phi elimination or two addr elimination. If this is 456 // the result of two address elimination, then the vreg is the first 457 // operand, and is a def-and-use. 458 if (mi->getOperand(0).isRegister() && 459 mi->getOperand(0).getReg() == interval.reg && 460 mi->getNumOperands() > 1 && mi->getOperand(1).isRegister() && 461 mi->getOperand(1).getReg() == interval.reg && 462 mi->getOperand(0).isDef() && mi->getOperand(1).isUse()) { 463 // If this is a two-address definition, then we have already processed 464 // the live range. The only problem is that we didn't realize there 465 // are actually two values in the live interval. Because of this we 466 // need to take the LiveRegion that defines this register and split it 467 // into two values. 468 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 469 unsigned RedefIndex = getDefIndex(MIIdx); 470 471 // Delete the initial value, which should be short and continuous, 472 // because the 2-addr copy must be in the same MBB as the redef. 473 interval.removeRange(DefIndex, RedefIndex); 474 475 // Two-address vregs should always only be redefined once. This means 476 // that at this point, there should be exactly one value number in it. 477 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!"); 478 479 // The new value number (#1) is defined by the instruction we claimed 480 // defined value #0. 481 unsigned ValNo = interval.getNextValue(0, 0); 482 interval.setValueNumberInfo(1, interval.getValNumInfo(0)); 483 484 // Value#0 is now defined by the 2-addr instruction. 485 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U)); 486 487 // Add the new live interval which replaces the range for the input copy. 488 LiveRange LR(DefIndex, RedefIndex, ValNo); 489 DEBUG(std::cerr << " replace range with " << LR); 490 interval.addRange(LR); 491 492 // If this redefinition is dead, we need to add a dummy unit live 493 // range covering the def slot. 494 if (lv_->RegisterDefIsDead(mi, interval.reg)) 495 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 496 497 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 498 499 } else { 500 // Otherwise, this must be because of phi elimination. If this is the 501 // first redefinition of the vreg that we have seen, go back and change 502 // the live range in the PHI block to be a different value number. 503 if (interval.containsOneValue()) { 504 assert(vi.Kills.size() == 1 && 505 "PHI elimination vreg should have one kill, the PHI itself!"); 506 507 // Remove the old range that we now know has an incorrect number. 508 MachineInstr *Killer = vi.Kills[0]; 509 unsigned Start = getMBBStartIdx(Killer->getParent()); 510 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 511 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "; 512 interval.print(std::cerr, mri_); std::cerr << "\n"); 513 interval.removeRange(Start, End); 514 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 515 516 // Replace the interval with one of a NEW value number. Note that this 517 // value number isn't actually defined by an instruction, weird huh? :) 518 LiveRange LR(Start, End, interval.getNextValue(~0U, 0)); 519 DEBUG(std::cerr << " replace range with " << LR); 520 interval.addRange(LR); 521 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 522 } 523 524 // In the case of PHI elimination, each variable definition is only 525 // live until the end of the block. We've already taken care of the 526 // rest of the live range. 527 unsigned defIndex = getDefIndex(MIIdx); 528 529 unsigned ValNum; 530 unsigned SrcReg, DstReg; 531 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 532 ValNum = interval.getNextValue(~0U, 0); 533 else 534 ValNum = interval.getNextValue(defIndex, SrcReg); 535 536 LiveRange LR(defIndex, 537 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum); 538 interval.addRange(LR); 539 DEBUG(std::cerr << " +" << LR); 540 } 541 } 542 543 DEBUG(std::cerr << '\n'); 544} 545 546void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 547 MachineBasicBlock::iterator mi, 548 unsigned MIIdx, 549 LiveInterval &interval, 550 unsigned SrcReg) { 551 // A physical register cannot be live across basic block, so its 552 // lifetime must end somewhere in its defining basic block. 553 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 554 typedef LiveVariables::killed_iterator KillIter; 555 556 unsigned baseIndex = MIIdx; 557 unsigned start = getDefIndex(baseIndex); 558 unsigned end = start; 559 560 // If it is not used after definition, it is considered dead at 561 // the instruction defining it. Hence its interval is: 562 // [defSlot(def), defSlot(def)+1) 563 if (lv_->RegisterDefIsDead(mi, interval.reg)) { 564 DEBUG(std::cerr << " dead"); 565 end = getDefIndex(start) + 1; 566 goto exit; 567 } 568 569 // If it is not dead on definition, it must be killed by a 570 // subsequent instruction. Hence its interval is: 571 // [defSlot(def), useSlot(kill)+1) 572 while (++mi != MBB->end()) { 573 baseIndex += InstrSlots::NUM; 574 if (lv_->KillsRegister(mi, interval.reg)) { 575 DEBUG(std::cerr << " killed"); 576 end = getUseIndex(baseIndex) + 1; 577 goto exit; 578 } 579 } 580 581 // The only case we should have a dead physreg here without a killing or 582 // instruction where we know it's dead is if it is live-in to the function 583 // and never used. 584 assert(!SrcReg && "physreg was not killed in defining block!"); 585 end = getDefIndex(start) + 1; // It's dead. 586 587exit: 588 assert(start < end && "did not find end of interval?"); 589 590 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U, 591 SrcReg)); 592 interval.addRange(LR); 593 DEBUG(std::cerr << " +" << LR << '\n'); 594} 595 596void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 597 MachineBasicBlock::iterator MI, 598 unsigned MIIdx, 599 unsigned reg) { 600 if (MRegisterInfo::isVirtualRegister(reg)) 601 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); 602 else if (allocatableRegs_[reg]) { 603 unsigned SrcReg, DstReg; 604 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) 605 SrcReg = 0; 606 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); 607 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 608 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); 609 } 610} 611 612/// computeIntervals - computes the live intervals for virtual 613/// registers. for some ordering of the machine instructions [1,N] a 614/// live interval is an interval [i, j) where 1 <= i <= j < N for 615/// which a variable is live 616void LiveIntervals::computeIntervals() { 617 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 618 DEBUG(std::cerr << "********** Function: " 619 << ((Value*)mf_->getFunction())->getName() << '\n'); 620 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); 621 622 // Track the index of the current machine instr. 623 unsigned MIIndex = 0; 624 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); 625 MBBI != E; ++MBBI) { 626 MachineBasicBlock *MBB = MBBI; 627 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 628 629 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); 630 if (IgnoreFirstInstr) { 631 ++MI; 632 IgnoreFirstInstr = false; 633 MIIndex += InstrSlots::NUM; 634 } 635 636 for (; MI != miEnd; ++MI) { 637 const TargetInstrDescriptor &TID = tii_->get(MI->getOpcode()); 638 DEBUG(std::cerr << MIIndex << "\t" << *MI); 639 640 // Handle implicit defs. 641 if (TID.ImplicitDefs) { 642 for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) 643 handleRegisterDef(MBB, MI, MIIndex, *ImpDef); 644 } 645 646 // Handle explicit defs. 647 for (int i = MI->getNumOperands() - 1; i >= 0; --i) { 648 MachineOperand &MO = MI->getOperand(i); 649 // handle register defs - build intervals 650 if (MO.isRegister() && MO.getReg() && MO.isDef()) 651 handleRegisterDef(MBB, MI, MIIndex, MO.getReg()); 652 } 653 654 MIIndex += InstrSlots::NUM; 655 } 656 } 657} 658 659/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA 660/// being the source and IntB being the dest, thus this defines a value number 661/// in IntB. If the source value number (in IntA) is defined by a copy from B, 662/// see if we can merge these two pieces of B into a single value number, 663/// eliminating a copy. For example: 664/// 665/// A3 = B0 666/// ... 667/// B1 = A3 <- this copy 668/// 669/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 670/// value number to be replaced with B0 (which simplifies the B liveinterval). 671/// 672/// This returns true if an interval was modified. 673/// 674bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, 675 MachineInstr *CopyMI) { 676 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 677 678 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 679 // the example above. 680 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 681 unsigned BValNo = BLR->ValId; 682 683 // Get the location that B is defined at. Two options: either this value has 684 // an unknown definition point or it is defined at CopyIdx. If unknown, we 685 // can't process it. 686 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo); 687 if (BValNoDefIdx == ~0U) return false; 688 assert(BValNoDefIdx == CopyIdx && 689 "Copy doesn't define the value?"); 690 691 // AValNo is the value number in A that defines the copy, A0 in the example. 692 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); 693 unsigned AValNo = AValLR->ValId; 694 695 // If AValNo is defined as a copy from IntB, we can potentially process this. 696 697 // Get the instruction that defines this value number. 698 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo); 699 if (!SrcReg) return false; // Not defined by a copy. 700 701 // If the value number is not defined by a copy instruction, ignore it. 702 703 // If the source register comes from an interval other than IntB, we can't 704 // handle this. 705 if (rep(SrcReg) != IntB.reg) return false; 706 707 // Get the LiveRange in IntB that this value number starts with. 708 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo); 709 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1); 710 711 // Make sure that the end of the live range is inside the same block as 712 // CopyMI. 713 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1); 714 if (!ValLREndInst || 715 ValLREndInst->getParent() != CopyMI->getParent()) return false; 716 717 // Okay, we now know that ValLR ends in the same block that the CopyMI 718 // live-range starts. If there are no intervening live ranges between them in 719 // IntB, we can merge them. 720 if (ValLR+1 != BLR) return false; 721 722 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_)); 723 724 // We are about to delete CopyMI, so need to remove it as the 'instruction 725 // that defines this value #'. 726 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0)); 727 728 // Okay, we can merge them. We need to insert a new liverange: 729 // [ValLR.end, BLR.begin) of either value number, then we merge the 730 // two value numbers. 731 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; 732 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 733 734 // If the IntB live range is assigned to a physical register, and if that 735 // physreg has aliases, 736 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { 737 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) { 738 LiveInterval &AliasLI = getInterval(*AS); 739 AliasLI.addRange(LiveRange(FillerStart, FillerEnd, 740 AliasLI.getNextValue(~0U, 0))); 741 } 742 } 743 744 // Okay, merge "B1" into the same value number as "B0". 745 if (BValNo != ValLR->ValId) 746 IntB.MergeValueNumberInto(BValNo, ValLR->ValId); 747 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_); 748 std::cerr << "\n"); 749 750 // Finally, delete the copy instruction. 751 RemoveMachineInstrFromMaps(CopyMI); 752 CopyMI->eraseFromParent(); 753 ++numPeep; 754 return true; 755} 756 757 758/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 759/// which are the src/dst of the copy instruction CopyMI. This returns true 760/// if the copy was successfully coallesced away, or if it is never possible 761/// to coallesce these this copy, due to register constraints. It returns 762/// false if it is not currently possible to coallesce this interval, but 763/// it may be possible if other things get coallesced. 764bool LiveIntervals::JoinCopy(MachineInstr *CopyMI, 765 unsigned SrcReg, unsigned DstReg) { 766 767 768 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI); 769 770 // Get representative registers. 771 SrcReg = rep(SrcReg); 772 DstReg = rep(DstReg); 773 774 // If they are already joined we continue. 775 if (SrcReg == DstReg) { 776 DEBUG(std::cerr << "\tCopy already coallesced.\n"); 777 return true; // Not coallescable. 778 } 779 780 // If they are both physical registers, we cannot join them. 781 if (MRegisterInfo::isPhysicalRegister(SrcReg) && 782 MRegisterInfo::isPhysicalRegister(DstReg)) { 783 DEBUG(std::cerr << "\tCan not coallesce physregs.\n"); 784 return true; // Not coallescable. 785 } 786 787 // We only join virtual registers with allocatable physical registers. 788 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){ 789 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n"); 790 return true; // Not coallescable. 791 } 792 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){ 793 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n"); 794 return true; // Not coallescable. 795 } 796 797 // If they are not of the same register class, we cannot join them. 798 if (differingRegisterClasses(SrcReg, DstReg)) { 799 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n"); 800 return true; // Not coallescable. 801 } 802 803 LiveInterval &SrcInt = getInterval(SrcReg); 804 LiveInterval &DestInt = getInterval(DstReg); 805 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg && 806 "Register mapping is horribly broken!"); 807 808 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_); 809 std::cerr << " and "; DestInt.print(std::cerr, mri_); 810 std::cerr << ": "); 811 812 // Okay, attempt to join these two intervals. On failure, this returns false. 813 // Otherwise, if one of the intervals being joined is a physreg, this method 814 // always canonicalizes DestInt to be it. The output "SrcInt" will not have 815 // been modified, so we can use this information below to update aliases. 816 if (!JoinIntervals(DestInt, SrcInt)) { 817 // Coallescing failed. 818 819 // If we can eliminate the copy without merging the live ranges, do so now. 820 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI)) 821 return true; 822 823 // Otherwise, we are unable to join the intervals. 824 DEBUG(std::cerr << "Interference!\n"); 825 return false; 826 } 827 828 bool Swapped = SrcReg == DestInt.reg; 829 if (Swapped) 830 std::swap(SrcReg, DstReg); 831 assert(MRegisterInfo::isVirtualRegister(SrcReg) && 832 "LiveInterval::join didn't work right!"); 833 834 // If we're about to merge live ranges into a physical register live range, 835 // we have to update any aliased register's live ranges to indicate that they 836 // have clobbered values for this range. 837 if (MRegisterInfo::isPhysicalRegister(DstReg)) { 838 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS) 839 getInterval(*AS).MergeInClobberRanges(SrcInt); 840 } 841 842 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_); 843 std::cerr << "\n"); 844 845 // If the intervals were swapped by Join, swap them back so that the register 846 // mapping (in the r2i map) is correct. 847 if (Swapped) SrcInt.swap(DestInt); 848 r2iMap_.erase(SrcReg); 849 r2rMap_[SrcReg] = DstReg; 850 851 // Finally, delete the copy instruction. 852 RemoveMachineInstrFromMaps(CopyMI); 853 CopyMI->eraseFromParent(); 854 ++numPeep; 855 ++numJoins; 856 return true; 857} 858 859/// ComputeUltimateVN - Assuming we are going to join two live intervals, 860/// compute what the resultant value numbers for each value in the input two 861/// ranges will be. This is complicated by copies between the two which can 862/// and will commonly cause multiple value numbers to be merged into one. 863/// 864/// VN is the value number that we're trying to resolve. InstDefiningValue 865/// keeps track of the new InstDefiningValue assignment for the result 866/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 867/// whether a value in this or other is a copy from the opposite set. 868/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 869/// already been assigned. 870/// 871/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 872/// contains the value number the copy is from. 873/// 874static unsigned ComputeUltimateVN(unsigned VN, 875 SmallVector<std::pair<unsigned, 876 unsigned>, 16> &ValueNumberInfo, 877 SmallVector<int, 16> &ThisFromOther, 878 SmallVector<int, 16> &OtherFromThis, 879 SmallVector<int, 16> &ThisValNoAssignments, 880 SmallVector<int, 16> &OtherValNoAssignments, 881 LiveInterval &ThisLI, LiveInterval &OtherLI) { 882 // If the VN has already been computed, just return it. 883 if (ThisValNoAssignments[VN] >= 0) 884 return ThisValNoAssignments[VN]; 885// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); 886 887 // If this val is not a copy from the other val, then it must be a new value 888 // number in the destination. 889 int OtherValNo = ThisFromOther[VN]; 890 if (OtherValNo == -1) { 891 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN)); 892 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1; 893 } 894 895 // Otherwise, this *is* a copy from the RHS. If the other side has already 896 // been computed, return it. 897 if (OtherValNoAssignments[OtherValNo] >= 0) 898 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo]; 899 900 // Mark this value number as currently being computed, then ask what the 901 // ultimate value # of the other value is. 902 ThisValNoAssignments[VN] = -2; 903 unsigned UltimateVN = 904 ComputeUltimateVN(OtherValNo, ValueNumberInfo, 905 OtherFromThis, ThisFromOther, 906 OtherValNoAssignments, ThisValNoAssignments, 907 OtherLI, ThisLI); 908 return ThisValNoAssignments[VN] = UltimateVN; 909} 910 911static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) { 912 return std::find(V.begin(), V.end(), Val) != V.end(); 913} 914 915/// SimpleJoin - Attempt to joint the specified interval into this one. The 916/// caller of this method must guarantee that the RHS only contains a single 917/// value number and that the RHS is not defined by a copy from this 918/// interval. This returns false if the intervals are not joinable, or it 919/// joins them and returns true. 920bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { 921 assert(RHS.containsOneValue()); 922 923 // Some number (potentially more than one) value numbers in the current 924 // interval may be defined as copies from the RHS. Scan the overlapping 925 // portions of the LHS and RHS, keeping track of this and looking for 926 // overlapping live ranges that are NOT defined as copies. If these exist, we 927 // cannot coallesce. 928 929 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); 930 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); 931 932 if (LHSIt->start < RHSIt->start) { 933 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); 934 if (LHSIt != LHS.begin()) --LHSIt; 935 } else if (RHSIt->start < LHSIt->start) { 936 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); 937 if (RHSIt != RHS.begin()) --RHSIt; 938 } 939 940 SmallVector<unsigned, 8> EliminatedLHSVals; 941 942 while (1) { 943 // Determine if these live intervals overlap. 944 bool Overlaps = false; 945 if (LHSIt->start <= RHSIt->start) 946 Overlaps = LHSIt->end > RHSIt->start; 947 else 948 Overlaps = RHSIt->end > LHSIt->start; 949 950 // If the live intervals overlap, there are two interesting cases: if the 951 // LHS interval is defined by a copy from the RHS, it's ok and we record 952 // that the LHS value # is the same as the RHS. If it's not, then we cannot 953 // coallesce these live ranges and we bail out. 954 if (Overlaps) { 955 // If we haven't already recorded that this value # is safe, check it. 956 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) { 957 // Copy from the RHS? 958 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId); 959 if (rep(SrcReg) != RHS.reg) 960 return false; // Nope, bail out. 961 962 EliminatedLHSVals.push_back(LHSIt->ValId); 963 } 964 965 // We know this entire LHS live range is okay, so skip it now. 966 if (++LHSIt == LHSEnd) break; 967 continue; 968 } 969 970 if (LHSIt->end < RHSIt->end) { 971 if (++LHSIt == LHSEnd) break; 972 } else { 973 // One interesting case to check here. It's possible that we have 974 // something like "X3 = Y" which defines a new value number in the LHS, 975 // and is the last use of this liverange of the RHS. In this case, we 976 // want to notice this copy (so that it gets coallesced away) even though 977 // the live ranges don't actually overlap. 978 if (LHSIt->start == RHSIt->end) { 979 if (InVector(LHSIt->ValId, EliminatedLHSVals)) { 980 // We already know that this value number is going to be merged in 981 // if coallescing succeeds. Just skip the liverange. 982 if (++LHSIt == LHSEnd) break; 983 } else { 984 // Otherwise, if this is a copy from the RHS, mark it as being merged 985 // in. 986 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) { 987 EliminatedLHSVals.push_back(LHSIt->ValId); 988 989 // We know this entire LHS live range is okay, so skip it now. 990 if (++LHSIt == LHSEnd) break; 991 } 992 } 993 } 994 995 if (++RHSIt == RHSEnd) break; 996 } 997 } 998 999 // If we got here, we know that the coallescing will be successful and that 1000 // the value numbers in EliminatedLHSVals will all be merged together. Since 1001 // the most common case is that EliminatedLHSVals has a single number, we 1002 // optimize for it: if there is more than one value, we merge them all into 1003 // the lowest numbered one, then handle the interval as if we were merging 1004 // with one value number. 1005 unsigned LHSValNo; 1006 if (EliminatedLHSVals.size() > 1) { 1007 // Loop through all the equal value numbers merging them into the smallest 1008 // one. 1009 unsigned Smallest = EliminatedLHSVals[0]; 1010 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { 1011 if (EliminatedLHSVals[i] < Smallest) { 1012 // Merge the current notion of the smallest into the smaller one. 1013 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); 1014 Smallest = EliminatedLHSVals[i]; 1015 } else { 1016 // Merge into the smallest. 1017 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); 1018 } 1019 } 1020 LHSValNo = Smallest; 1021 } else { 1022 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); 1023 LHSValNo = EliminatedLHSVals[0]; 1024 } 1025 1026 // Okay, now that there is a single LHS value number that we're merging the 1027 // RHS into, update the value number info for the LHS to indicate that the 1028 // value number is defined where the RHS value number was. 1029 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0)); 1030 1031 // Okay, the final step is to loop over the RHS live intervals, adding them to 1032 // the LHS. 1033 LHS.MergeRangesInAsValue(RHS, LHSValNo); 1034 LHS.weight += RHS.weight; 1035 1036 return true; 1037} 1038 1039/// JoinIntervals - Attempt to join these two intervals. On failure, this 1040/// returns false. Otherwise, if one of the intervals being joined is a 1041/// physreg, this method always canonicalizes LHS to be it. The output 1042/// "RHS" will not have been modified, so we can use this information 1043/// below to update aliases. 1044bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) { 1045 // Compute the final value assignment, assuming that the live ranges can be 1046 // coallesced. 1047 SmallVector<int, 16> LHSValNoAssignments; 1048 SmallVector<int, 16> RHSValNoAssignments; 1049 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo; 1050 1051 // Compute ultimate value numbers for the LHS and RHS values. 1052 if (RHS.containsOneValue()) { 1053 // Copies from a liveinterval with a single value are simple to handle and 1054 // very common, handle the special case here. This is important, because 1055 // often RHS is small and LHS is large (e.g. a physreg). 1056 1057 // Find out if the RHS is defined as a copy from some value in the LHS. 1058 int RHSValID = -1; 1059 std::pair<unsigned,unsigned> RHSValNoInfo; 1060 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0); 1061 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { 1062 // If RHS is not defined as a copy from the LHS, we can use simpler and 1063 // faster checks to see if the live ranges are coallescable. This joiner 1064 // can't swap the LHS/RHS intervals though. 1065 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { 1066 return SimpleJoin(LHS, RHS); 1067 } else { 1068 RHSValNoInfo = RHS.getValNumInfo(0); 1069 } 1070 } else { 1071 // It was defined as a copy from the LHS, find out what value # it is. 1072 unsigned ValInst = RHS.getInstForValNum(0); 1073 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1074 RHSValNoInfo = LHS.getValNumInfo(RHSValID); 1075 } 1076 1077 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1078 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1079 ValueNumberInfo.resize(LHS.getNumValNums()); 1080 1081 // Okay, *all* of the values in LHS that are defined as a copy from RHS 1082 // should now get updated. 1083 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1084 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) { 1085 if (rep(LHSSrcReg) != RHS.reg) { 1086 // If this is not a copy from the RHS, its value number will be 1087 // unmodified by the coallescing. 1088 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1089 LHSValNoAssignments[VN] = VN; 1090 } else if (RHSValID == -1) { 1091 // Otherwise, it is a copy from the RHS, and we don't already have a 1092 // value# for it. Keep the current value number, but remember it. 1093 LHSValNoAssignments[VN] = RHSValID = VN; 1094 ValueNumberInfo[VN] = RHSValNoInfo; 1095 } else { 1096 // Otherwise, use the specified value #. 1097 LHSValNoAssignments[VN] = RHSValID; 1098 if (VN != (unsigned)RHSValID) 1099 ValueNumberInfo[VN].first = ~1U; 1100 else 1101 ValueNumberInfo[VN] = RHSValNoInfo; 1102 } 1103 } else { 1104 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1105 LHSValNoAssignments[VN] = VN; 1106 } 1107 } 1108 1109 assert(RHSValID != -1 && "Didn't find value #?"); 1110 RHSValNoAssignments[0] = RHSValID; 1111 1112 } else { 1113 // Loop over the value numbers of the LHS, seeing if any are defined from 1114 // the RHS. 1115 SmallVector<int, 16> LHSValsDefinedFromRHS; 1116 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1); 1117 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1118 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN); 1119 if (ValSrcReg == 0) // Src not defined by a copy? 1120 continue; 1121 1122 // DstReg is known to be a register in the LHS interval. If the src is 1123 // from the RHS interval, we can use its value #. 1124 if (rep(ValSrcReg) != RHS.reg) 1125 continue; 1126 1127 // Figure out the value # from the RHS. 1128 unsigned ValInst = LHS.getInstForValNum(VN); 1129 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId; 1130 } 1131 1132 // Loop over the value numbers of the RHS, seeing if any are defined from 1133 // the LHS. 1134 SmallVector<int, 16> RHSValsDefinedFromLHS; 1135 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1); 1136 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1137 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN); 1138 if (ValSrcReg == 0) // Src not defined by a copy? 1139 continue; 1140 1141 // DstReg is known to be a register in the RHS interval. If the src is 1142 // from the LHS interval, we can use its value #. 1143 if (rep(ValSrcReg) != LHS.reg) 1144 continue; 1145 1146 // Figure out the value # from the LHS. 1147 unsigned ValInst = RHS.getInstForValNum(VN); 1148 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1149 } 1150 1151 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1152 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1153 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1154 1155 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1156 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U) 1157 continue; 1158 ComputeUltimateVN(VN, ValueNumberInfo, 1159 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1160 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS); 1161 } 1162 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1163 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U) 1164 continue; 1165 // If this value number isn't a copy from the LHS, it's a new number. 1166 if (RHSValsDefinedFromLHS[VN] == -1) { 1167 ValueNumberInfo.push_back(RHS.getValNumInfo(VN)); 1168 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1; 1169 continue; 1170 } 1171 1172 ComputeUltimateVN(VN, ValueNumberInfo, 1173 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1174 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS); 1175 } 1176 } 1177 1178 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1179 // interval lists to see if these intervals are coallescable. 1180 LiveInterval::const_iterator I = LHS.begin(); 1181 LiveInterval::const_iterator IE = LHS.end(); 1182 LiveInterval::const_iterator J = RHS.begin(); 1183 LiveInterval::const_iterator JE = RHS.end(); 1184 1185 // Skip ahead until the first place of potential sharing. 1186 if (I->start < J->start) { 1187 I = std::upper_bound(I, IE, J->start); 1188 if (I != LHS.begin()) --I; 1189 } else if (J->start < I->start) { 1190 J = std::upper_bound(J, JE, I->start); 1191 if (J != RHS.begin()) --J; 1192 } 1193 1194 while (1) { 1195 // Determine if these two live ranges overlap. 1196 bool Overlaps; 1197 if (I->start < J->start) { 1198 Overlaps = I->end > J->start; 1199 } else { 1200 Overlaps = J->end > I->start; 1201 } 1202 1203 // If so, check value # info to determine if they are really different. 1204 if (Overlaps) { 1205 // If the live range overlap will map to the same value number in the 1206 // result liverange, we can still coallesce them. If not, we can't. 1207 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId]) 1208 return false; 1209 } 1210 1211 if (I->end < J->end) { 1212 ++I; 1213 if (I == IE) break; 1214 } else { 1215 ++J; 1216 if (J == JE) break; 1217 } 1218 } 1219 1220 // If we get here, we know that we can coallesce the live ranges. Ask the 1221 // intervals to coallesce themselves now. 1222 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], 1223 ValueNumberInfo); 1224 return true; 1225} 1226 1227 1228namespace { 1229 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1230 // depth of the basic block (the unsigned), and then on the MBB number. 1231 struct DepthMBBCompare { 1232 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1233 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1234 if (LHS.first > RHS.first) return true; // Deeper loops first 1235 return LHS.first == RHS.first && 1236 LHS.second->getNumber() < RHS.second->getNumber(); 1237 } 1238 }; 1239} 1240 1241 1242void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB, 1243 std::vector<CopyRec> &TryAgain) { 1244 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 1245 1246 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1247 MII != E;) { 1248 MachineInstr *Inst = MII++; 1249 1250 // If this isn't a copy, we can't join intervals. 1251 unsigned SrcReg, DstReg; 1252 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; 1253 1254 if (!JoinCopy(Inst, SrcReg, DstReg)) 1255 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg)); 1256 } 1257} 1258 1259 1260void LiveIntervals::joinIntervals() { 1261 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 1262 1263 std::vector<CopyRec> TryAgainList; 1264 1265 const LoopInfo &LI = getAnalysis<LoopInfo>(); 1266 if (LI.begin() == LI.end()) { 1267 // If there are no loops in the function, join intervals in function order. 1268 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1269 I != E; ++I) 1270 CopyCoallesceInMBB(I, TryAgainList); 1271 } else { 1272 // Otherwise, join intervals in inner loops before other intervals. 1273 // Unfortunately we can't just iterate over loop hierarchy here because 1274 // there may be more MBB's than BB's. Collect MBB's for sorting. 1275 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1276 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1277 I != E; ++I) 1278 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 1279 1280 // Sort by loop depth. 1281 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1282 1283 // Finally, join intervals in loop nest order. 1284 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1285 CopyCoallesceInMBB(MBBs[i].second, TryAgainList); 1286 } 1287 1288 // Joining intervals can allow other intervals to be joined. Iteratively join 1289 // until we make no progress. 1290 bool ProgressMade = true; 1291 while (ProgressMade) { 1292 ProgressMade = false; 1293 1294 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1295 CopyRec &TheCopy = TryAgainList[i]; 1296 if (TheCopy.MI && 1297 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) { 1298 TheCopy.MI = 0; // Mark this one as done. 1299 ProgressMade = true; 1300 } 1301 } 1302 } 1303 1304 DEBUG(std::cerr << "*** Register mapping ***\n"); 1305 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) 1306 if (r2rMap_[i]) { 1307 std::cerr << " reg " << i << " -> "; 1308 printRegName(r2rMap_[i]); 1309 std::cerr << "\n"; 1310 }); 1311} 1312 1313/// Return true if the two specified registers belong to different register 1314/// classes. The registers may be either phys or virt regs. 1315bool LiveIntervals::differingRegisterClasses(unsigned RegA, 1316 unsigned RegB) const { 1317 1318 // Get the register classes for the first reg. 1319 if (MRegisterInfo::isPhysicalRegister(RegA)) { 1320 assert(MRegisterInfo::isVirtualRegister(RegB) && 1321 "Shouldn't consider two physregs!"); 1322 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 1323 } 1324 1325 // Compare against the regclass for the second reg. 1326 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 1327 if (MRegisterInfo::isVirtualRegister(RegB)) 1328 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 1329 else 1330 return !RegClass->contains(RegB); 1331} 1332 1333LiveInterval LiveIntervals::createInterval(unsigned reg) { 1334 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 1335 (float)HUGE_VAL : 0.0F; 1336 return LiveInterval(reg, Weight); 1337} 1338