LiveIntervalAnalysis.cpp revision 5277e4304e9559c13aa42b1d056e828f8f75ff08
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37#include <iostream> 38using namespace llvm; 39 40namespace { 41 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 42 43 static Statistic<> numIntervals 44 ("liveintervals", "Number of original intervals"); 45 46 static Statistic<> numIntervalsAfter 47 ("liveintervals", "Number of intervals after coalescing"); 48 49 static Statistic<> numJoins 50 ("liveintervals", "Number of interval joins performed"); 51 52 static Statistic<> numPeep 53 ("liveintervals", "Number of identity moves eliminated after coalescing"); 54 55 static Statistic<> numFolded 56 ("liveintervals", "Number of loads/stores folded into instructions"); 57 58 static cl::opt<bool> 59 EnableJoining("join-liveintervals", 60 cl::desc("Join compatible live intervals"), 61 cl::init(true)); 62} 63 64void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 65 AU.addRequired<LiveVariables>(); 66 AU.addPreservedID(PHIEliminationID); 67 AU.addRequiredID(PHIEliminationID); 68 AU.addRequiredID(TwoAddressInstructionPassID); 69 AU.addRequired<LoopInfo>(); 70 MachineFunctionPass::getAnalysisUsage(AU); 71} 72 73void LiveIntervals::releaseMemory() { 74 mi2iMap_.clear(); 75 i2miMap_.clear(); 76 r2iMap_.clear(); 77 r2rMap_.clear(); 78} 79 80 81static bool isZeroLengthInterval(LiveInterval *li) { 82 for (LiveInterval::Ranges::const_iterator 83 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) 84 if (i->end - i->start > LiveIntervals::InstrSlots::NUM) 85 return false; 86 return true; 87} 88 89 90/// runOnMachineFunction - Register allocate the whole function 91/// 92bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 93 mf_ = &fn; 94 tm_ = &fn.getTarget(); 95 mri_ = tm_->getRegisterInfo(); 96 tii_ = tm_->getInstrInfo(); 97 lv_ = &getAnalysis<LiveVariables>(); 98 allocatableRegs_ = mri_->getAllocatableSet(fn); 99 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 100 101 // If this function has any live ins, insert a dummy instruction at the 102 // beginning of the function that we will pretend "defines" the values. This 103 // is to make the interval analysis simpler by providing a number. 104 if (fn.livein_begin() != fn.livein_end()) { 105 unsigned FirstLiveIn = fn.livein_begin()->first; 106 107 // Find a reg class that contains this live in. 108 const TargetRegisterClass *RC = 0; 109 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), 110 E = mri_->regclass_end(); RCI != E; ++RCI) 111 if ((*RCI)->contains(FirstLiveIn)) { 112 RC = *RCI; 113 break; 114 } 115 116 MachineInstr *OldFirstMI = fn.begin()->begin(); 117 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), 118 FirstLiveIn, FirstLiveIn, RC); 119 assert(OldFirstMI != fn.begin()->begin() && 120 "copyRetToReg didn't insert anything!"); 121 } 122 123 // number MachineInstrs 124 unsigned miIndex = 0; 125 for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end(); 126 mbb != mbbEnd; ++mbb) 127 for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 128 mi != miEnd; ++mi) { 129 bool inserted = mi2iMap_.insert(std::make_pair(mi, miIndex)).second; 130 assert(inserted && "multiple MachineInstr -> index mappings"); 131 i2miMap_.push_back(mi); 132 miIndex += InstrSlots::NUM; 133 } 134 135 // Note intervals due to live-in values. 136 if (fn.livein_begin() != fn.livein_end()) { 137 MachineBasicBlock *Entry = fn.begin(); 138 for (MachineFunction::livein_iterator I = fn.livein_begin(), 139 E = fn.livein_end(); I != E; ++I) { 140 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 141 getOrCreateInterval(I->first), 0); 142 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) 143 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 144 getOrCreateInterval(*AS), 0); 145 } 146 } 147 148 computeIntervals(); 149 150 numIntervals += getNumIntervals(); 151 152 DEBUG(std::cerr << "********** INTERVALS **********\n"; 153 for (iterator I = begin(), E = end(); I != E; ++I) { 154 I->second.print(std::cerr, mri_); 155 std::cerr << "\n"; 156 }); 157 158 // join intervals if requested 159 if (EnableJoining) joinIntervals(); 160 161 numIntervalsAfter += getNumIntervals(); 162 163 // perform a final pass over the instructions and compute spill 164 // weights, coalesce virtual registers and remove identity moves. 165 const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); 166 167 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 168 mbbi != mbbe; ++mbbi) { 169 MachineBasicBlock* mbb = mbbi; 170 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 171 172 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 173 mii != mie; ) { 174 // if the move will be an identity move delete it 175 unsigned srcReg, dstReg, RegRep; 176 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 177 (RegRep = rep(srcReg)) == rep(dstReg)) { 178 // remove from def list 179 LiveInterval &interval = getOrCreateInterval(RegRep); 180 RemoveMachineInstrFromMaps(mii); 181 mii = mbbi->erase(mii); 182 ++numPeep; 183 } 184 else { 185 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { 186 const MachineOperand &mop = mii->getOperand(i); 187 if (mop.isRegister() && mop.getReg() && 188 MRegisterInfo::isVirtualRegister(mop.getReg())) { 189 // replace register with representative register 190 unsigned reg = rep(mop.getReg()); 191 mii->getOperand(i).setReg(reg); 192 193 LiveInterval &RegInt = getInterval(reg); 194 RegInt.weight += 195 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 196 } 197 } 198 ++mii; 199 } 200 } 201 } 202 203 for (iterator I = begin(), E = end(); I != E; ++I) { 204 LiveInterval &li = I->second; 205 if (MRegisterInfo::isVirtualRegister(li.reg)) { 206 // If the live interval length is essentially zero, i.e. in every live 207 // range the use follows def immediately, it doesn't make sense to spill 208 // it and hope it will be easier to allocate for this li. 209 if (isZeroLengthInterval(&li)) 210 li.weight = float(HUGE_VAL); 211 } 212 } 213 214 DEBUG(dump()); 215 return true; 216} 217 218/// print - Implement the dump method. 219void LiveIntervals::print(std::ostream &O, const Module* ) const { 220 O << "********** INTERVALS **********\n"; 221 for (const_iterator I = begin(), E = end(); I != E; ++I) { 222 I->second.print(std::cerr, mri_); 223 std::cerr << "\n"; 224 } 225 226 O << "********** MACHINEINSTRS **********\n"; 227 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 228 mbbi != mbbe; ++mbbi) { 229 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 230 for (MachineBasicBlock::iterator mii = mbbi->begin(), 231 mie = mbbi->end(); mii != mie; ++mii) { 232 O << getInstructionIndex(mii) << '\t' << *mii; 233 } 234 } 235} 236 237std::vector<LiveInterval*> LiveIntervals:: 238addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 239 // since this is called after the analysis is done we don't know if 240 // LiveVariables is available 241 lv_ = getAnalysisToUpdate<LiveVariables>(); 242 243 std::vector<LiveInterval*> added; 244 245 assert(li.weight != HUGE_VAL && 246 "attempt to spill already spilled interval!"); 247 248 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "; 249 li.print(std::cerr, mri_); std::cerr << '\n'); 250 251 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 252 253 for (LiveInterval::Ranges::const_iterator 254 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 255 unsigned index = getBaseIndex(i->start); 256 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 257 for (; index != end; index += InstrSlots::NUM) { 258 // skip deleted instructions 259 while (index != end && !getInstructionFromIndex(index)) 260 index += InstrSlots::NUM; 261 if (index == end) break; 262 263 MachineInstr *MI = getInstructionFromIndex(index); 264 265 // NewRegLiveIn - This instruction might have multiple uses of the spilled 266 // register. In this case, for the first use, keep track of the new vreg 267 // that we reload it into. If we see a second use, reuse this vreg 268 // instead of creating live ranges for two reloads. 269 unsigned NewRegLiveIn = 0; 270 271 for_operand: 272 for (unsigned i = 0; i != MI->getNumOperands(); ++i) { 273 MachineOperand& mop = MI->getOperand(i); 274 if (mop.isRegister() && mop.getReg() == li.reg) { 275 if (NewRegLiveIn && mop.isUse()) { 276 // We already emitted a reload of this value, reuse it for 277 // subsequent operands. 278 MI->getOperand(i).setReg(NewRegLiveIn); 279 DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn 280 << " for operand #" << i << '\n'); 281 } else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) { 282 // Attempt to fold the memory reference into the instruction. If we 283 // can do this, we don't need to insert spill code. 284 if (lv_) 285 lv_->instructionChanged(MI, fmi); 286 MachineBasicBlock &MBB = *MI->getParent(); 287 vrm.virtFolded(li.reg, MI, i, fmi); 288 mi2iMap_.erase(MI); 289 i2miMap_[index/InstrSlots::NUM] = fmi; 290 mi2iMap_[fmi] = index; 291 MI = MBB.insert(MBB.erase(MI), fmi); 292 ++numFolded; 293 // Folding the load/store can completely change the instruction in 294 // unpredictable ways, rescan it from the beginning. 295 goto for_operand; 296 } else { 297 // This is tricky. We need to add information in the interval about 298 // the spill code so we have to use our extra load/store slots. 299 // 300 // If we have a use we are going to have a load so we start the 301 // interval from the load slot onwards. Otherwise we start from the 302 // def slot. 303 unsigned start = (mop.isUse() ? 304 getLoadIndex(index) : 305 getDefIndex(index)); 306 // If we have a def we are going to have a store right after it so 307 // we end the interval after the use of the next 308 // instruction. Otherwise we end after the use of this instruction. 309 unsigned end = 1 + (mop.isDef() ? 310 getStoreIndex(index) : 311 getUseIndex(index)); 312 313 // create a new register for this spill 314 NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc); 315 MI->getOperand(i).setReg(NewRegLiveIn); 316 vrm.grow(); 317 vrm.assignVirt2StackSlot(NewRegLiveIn, slot); 318 LiveInterval& nI = getOrCreateInterval(NewRegLiveIn); 319 assert(nI.empty()); 320 321 // the spill weight is now infinity as it 322 // cannot be spilled again 323 nI.weight = float(HUGE_VAL); 324 LiveRange LR(start, end, nI.getNextValue(~0U, 0)); 325 DEBUG(std::cerr << " +" << LR); 326 nI.addRange(LR); 327 added.push_back(&nI); 328 329 // update live variables if it is available 330 if (lv_) 331 lv_->addVirtualRegisterKilled(NewRegLiveIn, MI); 332 333 // If this is a live in, reuse it for subsequent live-ins. If it's 334 // a def, we can't do this. 335 if (!mop.isUse()) NewRegLiveIn = 0; 336 337 DEBUG(std::cerr << "\t\t\t\tadded new interval: "; 338 nI.print(std::cerr, mri_); std::cerr << '\n'); 339 } 340 } 341 } 342 } 343 } 344 345 return added; 346} 347 348void LiveIntervals::printRegName(unsigned reg) const { 349 if (MRegisterInfo::isPhysicalRegister(reg)) 350 std::cerr << mri_->getName(reg); 351 else 352 std::cerr << "%reg" << reg; 353} 354 355void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 356 MachineBasicBlock::iterator mi, 357 unsigned MIIdx, 358 LiveInterval &interval) { 359 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 360 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 361 362 // Virtual registers may be defined multiple times (due to phi 363 // elimination and 2-addr elimination). Much of what we do only has to be 364 // done once for the vreg. We use an empty interval to detect the first 365 // time we see a vreg. 366 if (interval.empty()) { 367 // Get the Idx of the defining instructions. 368 unsigned defIndex = getDefIndex(MIIdx); 369 370 unsigned ValNum; 371 unsigned SrcReg, DstReg; 372 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 373 ValNum = interval.getNextValue(~0U, 0); 374 else 375 ValNum = interval.getNextValue(defIndex, SrcReg); 376 377 assert(ValNum == 0 && "First value in interval is not 0?"); 378 ValNum = 0; // Clue in the optimizer. 379 380 // Loop over all of the blocks that the vreg is defined in. There are 381 // two cases we have to handle here. The most common case is a vreg 382 // whose lifetime is contained within a basic block. In this case there 383 // will be a single kill, in MBB, which comes after the definition. 384 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 385 // FIXME: what about dead vars? 386 unsigned killIdx; 387 if (vi.Kills[0] != mi) 388 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 389 else 390 killIdx = defIndex+1; 391 392 // If the kill happens after the definition, we have an intra-block 393 // live range. 394 if (killIdx > defIndex) { 395 assert(vi.AliveBlocks.empty() && 396 "Shouldn't be alive across any blocks!"); 397 LiveRange LR(defIndex, killIdx, ValNum); 398 interval.addRange(LR); 399 DEBUG(std::cerr << " +" << LR << "\n"); 400 return; 401 } 402 } 403 404 // The other case we handle is when a virtual register lives to the end 405 // of the defining block, potentially live across some blocks, then is 406 // live into some number of blocks, but gets killed. Start by adding a 407 // range that goes from this definition to the end of the defining block. 408 LiveRange NewLR(defIndex, 409 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 410 ValNum); 411 DEBUG(std::cerr << " +" << NewLR); 412 interval.addRange(NewLR); 413 414 // Iterate over all of the blocks that the variable is completely 415 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 416 // live interval. 417 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 418 if (vi.AliveBlocks[i]) { 419 MachineBasicBlock* mbb = mf_->getBlockNumbered(i); 420 if (!mbb->empty()) { 421 LiveRange LR(getInstructionIndex(&mbb->front()), 422 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 423 ValNum); 424 interval.addRange(LR); 425 DEBUG(std::cerr << " +" << LR); 426 } 427 } 428 } 429 430 // Finally, this virtual register is live from the start of any killing 431 // block to the 'use' slot of the killing instruction. 432 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 433 MachineInstr *Kill = vi.Kills[i]; 434 LiveRange LR(getInstructionIndex(Kill->getParent()->begin()), 435 getUseIndex(getInstructionIndex(Kill))+1, 436 ValNum); 437 interval.addRange(LR); 438 DEBUG(std::cerr << " +" << LR); 439 } 440 441 } else { 442 // If this is the second time we see a virtual register definition, it 443 // must be due to phi elimination or two addr elimination. If this is 444 // the result of two address elimination, then the vreg is the first 445 // operand, and is a def-and-use. 446 if (mi->getOperand(0).isRegister() && 447 mi->getOperand(0).getReg() == interval.reg && 448 mi->getOperand(0).isDef() && mi->getOperand(0).isUse()) { 449 // If this is a two-address definition, then we have already processed 450 // the live range. The only problem is that we didn't realize there 451 // are actually two values in the live interval. Because of this we 452 // need to take the LiveRegion that defines this register and split it 453 // into two values. 454 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 455 unsigned RedefIndex = getDefIndex(MIIdx); 456 457 // Delete the initial value, which should be short and continuous, 458 // because the 2-addr copy must be in the same MBB as the redef. 459 interval.removeRange(DefIndex, RedefIndex); 460 461 // Two-address vregs should always only be redefined once. This means 462 // that at this point, there should be exactly one value number in it. 463 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!"); 464 465 // The new value number (#1) is defined by the instruction we claimed 466 // defined value #0. 467 unsigned ValNo = interval.getNextValue(0, 0); 468 interval.setValueNumberInfo(1, interval.getValNumInfo(0)); 469 470 // Value#0 is now defined by the 2-addr instruction. 471 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U)); 472 473 // Add the new live interval which replaces the range for the input copy. 474 LiveRange LR(DefIndex, RedefIndex, ValNo); 475 DEBUG(std::cerr << " replace range with " << LR); 476 interval.addRange(LR); 477 478 // If this redefinition is dead, we need to add a dummy unit live 479 // range covering the def slot. 480 if (lv_->RegisterDefIsDead(mi, interval.reg)) 481 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 482 483 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 484 485 } else { 486 // Otherwise, this must be because of phi elimination. If this is the 487 // first redefinition of the vreg that we have seen, go back and change 488 // the live range in the PHI block to be a different value number. 489 if (interval.containsOneValue()) { 490 assert(vi.Kills.size() == 1 && 491 "PHI elimination vreg should have one kill, the PHI itself!"); 492 493 // Remove the old range that we now know has an incorrect number. 494 MachineInstr *Killer = vi.Kills[0]; 495 unsigned Start = getInstructionIndex(Killer->getParent()->begin()); 496 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 497 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "; 498 interval.print(std::cerr, mri_); std::cerr << "\n"); 499 interval.removeRange(Start, End); 500 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 501 502 // Replace the interval with one of a NEW value number. Note that this 503 // value number isn't actually defined by an instruction, weird huh? :) 504 LiveRange LR(Start, End, interval.getNextValue(~0U, 0)); 505 DEBUG(std::cerr << " replace range with " << LR); 506 interval.addRange(LR); 507 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_)); 508 } 509 510 // In the case of PHI elimination, each variable definition is only 511 // live until the end of the block. We've already taken care of the 512 // rest of the live range. 513 unsigned defIndex = getDefIndex(MIIdx); 514 515 unsigned ValNum; 516 unsigned SrcReg, DstReg; 517 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 518 ValNum = interval.getNextValue(~0U, 0); 519 else 520 ValNum = interval.getNextValue(defIndex, SrcReg); 521 522 LiveRange LR(defIndex, 523 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum); 524 interval.addRange(LR); 525 DEBUG(std::cerr << " +" << LR); 526 } 527 } 528 529 DEBUG(std::cerr << '\n'); 530} 531 532void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 533 MachineBasicBlock::iterator mi, 534 unsigned MIIdx, 535 LiveInterval &interval, 536 unsigned SrcReg) { 537 // A physical register cannot be live across basic block, so its 538 // lifetime must end somewhere in its defining basic block. 539 DEBUG(std::cerr << "\t\tregister: "; printRegName(interval.reg)); 540 typedef LiveVariables::killed_iterator KillIter; 541 542 unsigned baseIndex = MIIdx; 543 unsigned start = getDefIndex(baseIndex); 544 unsigned end = start; 545 546 // If it is not used after definition, it is considered dead at 547 // the instruction defining it. Hence its interval is: 548 // [defSlot(def), defSlot(def)+1) 549 if (lv_->RegisterDefIsDead(mi, interval.reg)) { 550 DEBUG(std::cerr << " dead"); 551 end = getDefIndex(start) + 1; 552 goto exit; 553 } 554 555 // If it is not dead on definition, it must be killed by a 556 // subsequent instruction. Hence its interval is: 557 // [defSlot(def), useSlot(kill)+1) 558 while (++mi != MBB->end()) { 559 baseIndex += InstrSlots::NUM; 560 if (lv_->KillsRegister(mi, interval.reg)) { 561 DEBUG(std::cerr << " killed"); 562 end = getUseIndex(baseIndex) + 1; 563 goto exit; 564 } 565 } 566 567 // The only case we should have a dead physreg here without a killing or 568 // instruction where we know it's dead is if it is live-in to the function 569 // and never used. 570 assert(!SrcReg && "physreg was not killed in defining block!"); 571 end = getDefIndex(start) + 1; // It's dead. 572 573exit: 574 assert(start < end && "did not find end of interval?"); 575 576 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U, 577 SrcReg)); 578 interval.addRange(LR); 579 DEBUG(std::cerr << " +" << LR << '\n'); 580} 581 582void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 583 MachineBasicBlock::iterator MI, 584 unsigned MIIdx, 585 unsigned reg) { 586 if (MRegisterInfo::isVirtualRegister(reg)) 587 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); 588 else if (allocatableRegs_[reg]) { 589 unsigned SrcReg, DstReg; 590 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) 591 SrcReg = 0; 592 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); 593 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 594 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); 595 } 596} 597 598/// computeIntervals - computes the live intervals for virtual 599/// registers. for some ordering of the machine instructions [1,N] a 600/// live interval is an interval [i, j) where 1 <= i <= j < N for 601/// which a variable is live 602void LiveIntervals::computeIntervals() { 603 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n"); 604 DEBUG(std::cerr << "********** Function: " 605 << ((Value*)mf_->getFunction())->getName() << '\n'); 606 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); 607 608 // Track the index of the current machine instr. 609 unsigned MIIndex = 0; 610 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 611 I != E; ++I) { 612 MachineBasicBlock* mbb = I; 613 DEBUG(std::cerr << ((Value*)mbb->getBasicBlock())->getName() << ":\n"); 614 615 MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); 616 if (IgnoreFirstInstr) { ++mi; IgnoreFirstInstr = false; } 617 for (; mi != miEnd; ++mi) { 618 const TargetInstrDescriptor& tid = 619 tm_->getInstrInfo()->get(mi->getOpcode()); 620 DEBUG(std::cerr << MIIndex << "\t" << *mi); 621 622 // FIXME: Why is this needed? 623 MIIndex = getInstructionIndex(mi); 624 625 // handle implicit defs 626 if (tid.ImplicitDefs) { 627 for (const unsigned* id = tid.ImplicitDefs; *id; ++id) 628 handleRegisterDef(mbb, mi, MIIndex, *id); 629 } 630 631 // handle explicit defs 632 for (int i = mi->getNumOperands() - 1; i >= 0; --i) { 633 MachineOperand& mop = mi->getOperand(i); 634 // handle register defs - build intervals 635 if (mop.isRegister() && mop.getReg() && mop.isDef()) 636 handleRegisterDef(mbb, mi, MIIndex, mop.getReg()); 637 } 638 639 MIIndex += InstrSlots::NUM; 640 } 641 } 642} 643 644/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA 645/// being the source and IntB being the dest, thus this defines a value number 646/// in IntB. If the source value number (in IntA) is defined by a copy from B, 647/// see if we can merge these two pieces of B into a single value number, 648/// eliminating a copy. For example: 649/// 650/// A3 = B0 651/// ... 652/// B1 = A3 <- this copy 653/// 654/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 655/// value number to be replaced with B0 (which simplifies the B liveinterval). 656/// 657/// This returns true if an interval was modified. 658/// 659bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, 660 MachineInstr *CopyMI) { 661 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 662 663 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 664 // the example above. 665 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 666 unsigned BValNo = BLR->ValId; 667 668 // Get the location that B is defined at. Two options: either this value has 669 // an unknown definition point or it is defined at CopyIdx. If unknown, we 670 // can't process it. 671 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo); 672 if (BValNoDefIdx == ~0U) return false; 673 assert(BValNoDefIdx == CopyIdx && 674 "Copy doesn't define the value?"); 675 676 // AValNo is the value number in A that defines the copy, A0 in the example. 677 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); 678 unsigned AValNo = AValLR->ValId; 679 680 // If AValNo is defined as a copy from IntB, we can potentially process this. 681 682 // Get the instruction that defines this value number. 683 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo); 684 if (!SrcReg) return false; // Not defined by a copy. 685 686 // If the value number is not defined by a copy instruction, ignore it. 687 688 // If the source register comes from an interval other than IntB, we can't 689 // handle this. 690 if (rep(SrcReg) != IntB.reg) return false; 691 692 // Get the LiveRange in IntB that this value number starts with. 693 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo); 694 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1); 695 696 // Make sure that the end of the live range is inside the same block as 697 // CopyMI. 698 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1); 699 if (!ValLREndInst || 700 ValLREndInst->getParent() != CopyMI->getParent()) return false; 701 702 // Okay, we now know that ValLR ends in the same block that the CopyMI 703 // live-range starts. If there are no intervening live ranges between them in 704 // IntB, we can merge them. 705 if (ValLR+1 != BLR) return false; 706 707 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_)); 708 709 // We are about to delete CopyMI, so need to remove it as the 'instruction 710 // that defines this value #'. 711 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0)); 712 713 // Okay, we can merge them. We need to insert a new liverange: 714 // [ValLR.end, BLR.begin) of either value number, then we merge the 715 // two value numbers. 716 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; 717 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 718 719 // If the IntB live range is assigned to a physical register, and if that 720 // physreg has aliases, 721 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { 722 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) { 723 LiveInterval &AliasLI = getInterval(*AS); 724 AliasLI.addRange(LiveRange(FillerStart, FillerEnd, 725 AliasLI.getNextValue(~0U, 0))); 726 } 727 } 728 729 // Okay, merge "B1" into the same value number as "B0". 730 if (BValNo != ValLR->ValId) 731 IntB.MergeValueNumberInto(BValNo, ValLR->ValId); 732 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_); 733 std::cerr << "\n"); 734 735 // Finally, delete the copy instruction. 736 RemoveMachineInstrFromMaps(CopyMI); 737 CopyMI->eraseFromParent(); 738 ++numPeep; 739 return true; 740} 741 742 743/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 744/// which are the src/dst of the copy instruction CopyMI. This returns true 745/// if the copy was successfully coallesced away, or if it is never possible 746/// to coallesce these this copy, due to register constraints. It returns 747/// false if it is not currently possible to coallesce this interval, but 748/// it may be possible if other things get coallesced. 749bool LiveIntervals::JoinCopy(MachineInstr *CopyMI, 750 unsigned SrcReg, unsigned DstReg) { 751 752 753 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI); 754 755 // Get representative registers. 756 SrcReg = rep(SrcReg); 757 DstReg = rep(DstReg); 758 759 // If they are already joined we continue. 760 if (SrcReg == DstReg) { 761 DEBUG(std::cerr << "\tCopy already coallesced.\n"); 762 return true; // Not coallescable. 763 } 764 765 // If they are both physical registers, we cannot join them. 766 if (MRegisterInfo::isPhysicalRegister(SrcReg) && 767 MRegisterInfo::isPhysicalRegister(DstReg)) { 768 DEBUG(std::cerr << "\tCan not coallesce physregs.\n"); 769 return true; // Not coallescable. 770 } 771 772 // We only join virtual registers with allocatable physical registers. 773 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){ 774 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n"); 775 return true; // Not coallescable. 776 } 777 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){ 778 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n"); 779 return true; // Not coallescable. 780 } 781 782 // If they are not of the same register class, we cannot join them. 783 if (differingRegisterClasses(SrcReg, DstReg)) { 784 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n"); 785 return true; // Not coallescable. 786 } 787 788 LiveInterval &SrcInt = getInterval(SrcReg); 789 LiveInterval &DestInt = getInterval(DstReg); 790 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg && 791 "Register mapping is horribly broken!"); 792 793 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_); 794 std::cerr << " and "; DestInt.print(std::cerr, mri_); 795 std::cerr << ": "); 796 797 // Okay, attempt to join these two intervals. On failure, this returns false. 798 // Otherwise, if one of the intervals being joined is a physreg, this method 799 // always canonicalizes DestInt to be it. The output "SrcInt" will not have 800 // been modified, so we can use this information below to update aliases. 801 if (!JoinIntervals(DestInt, SrcInt)) { 802 // Coallescing failed. 803 804 // If we can eliminate the copy without merging the live ranges, do so now. 805 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI)) 806 return true; 807 808 // Otherwise, we are unable to join the intervals. 809 DEBUG(std::cerr << "Interference!\n"); 810 return false; 811 } 812 813 bool Swapped = SrcReg == DestInt.reg; 814 if (Swapped) 815 std::swap(SrcReg, DstReg); 816 assert(MRegisterInfo::isVirtualRegister(SrcReg) && 817 "LiveInterval::join didn't work right!"); 818 819 // If we're about to merge live ranges into a physical register live range, 820 // we have to update any aliased register's live ranges to indicate that they 821 // have clobbered values for this range. 822 if (MRegisterInfo::isPhysicalRegister(DstReg)) { 823 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS) 824 getInterval(*AS).MergeInClobberRanges(SrcInt); 825 } 826 827 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_); 828 std::cerr << "\n"); 829 830 // If the intervals were swapped by Join, swap them back so that the register 831 // mapping (in the r2i map) is correct. 832 if (Swapped) SrcInt.swap(DestInt); 833 r2iMap_.erase(SrcReg); 834 r2rMap_[SrcReg] = DstReg; 835 836 // Finally, delete the copy instruction. 837 RemoveMachineInstrFromMaps(CopyMI); 838 CopyMI->eraseFromParent(); 839 ++numPeep; 840 ++numJoins; 841 return true; 842} 843 844/// ComputeUltimateVN - Assuming we are going to join two live intervals, 845/// compute what the resultant value numbers for each value in the input two 846/// ranges will be. This is complicated by copies between the two which can 847/// and will commonly cause multiple value numbers to be merged into one. 848/// 849/// VN is the value number that we're trying to resolve. InstDefiningValue 850/// keeps track of the new InstDefiningValue assignment for the result 851/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 852/// whether a value in this or other is a copy from the opposite set. 853/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 854/// already been assigned. 855/// 856/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 857/// contains the value number the copy is from. 858/// 859static unsigned ComputeUltimateVN(unsigned VN, 860 SmallVector<std::pair<unsigned, 861 unsigned>, 16> &ValueNumberInfo, 862 SmallVector<int, 16> &ThisFromOther, 863 SmallVector<int, 16> &OtherFromThis, 864 SmallVector<int, 16> &ThisValNoAssignments, 865 SmallVector<int, 16> &OtherValNoAssignments, 866 LiveInterval &ThisLI, LiveInterval &OtherLI) { 867 // If the VN has already been computed, just return it. 868 if (ThisValNoAssignments[VN] >= 0) 869 return ThisValNoAssignments[VN]; 870// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); 871 872 // If this val is not a copy from the other val, then it must be a new value 873 // number in the destination. 874 int OtherValNo = ThisFromOther[VN]; 875 if (OtherValNo == -1) { 876 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN)); 877 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1; 878 } 879 880 // Otherwise, this *is* a copy from the RHS. If the other side has already 881 // been computed, return it. 882 if (OtherValNoAssignments[OtherValNo] >= 0) 883 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo]; 884 885 // Mark this value number as currently being computed, then ask what the 886 // ultimate value # of the other value is. 887 ThisValNoAssignments[VN] = -2; 888 unsigned UltimateVN = 889 ComputeUltimateVN(OtherValNo, ValueNumberInfo, 890 OtherFromThis, ThisFromOther, 891 OtherValNoAssignments, ThisValNoAssignments, 892 OtherLI, ThisLI); 893 return ThisValNoAssignments[VN] = UltimateVN; 894} 895 896static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) { 897 return std::find(V.begin(), V.end(), Val) != V.end(); 898} 899 900/// SimpleJoin - Attempt to joint the specified interval into this one. The 901/// caller of this method must guarantee that the RHS only contains a single 902/// value number and that the RHS is not defined by a copy from this 903/// interval. This returns false if the intervals are not joinable, or it 904/// joins them and returns true. 905bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { 906 assert(RHS.containsOneValue()); 907 908 // Some number (potentially more than one) value numbers in the current 909 // interval may be defined as copies from the RHS. Scan the overlapping 910 // portions of the LHS and RHS, keeping track of this and looking for 911 // overlapping live ranges that are NOT defined as copies. If these exist, we 912 // cannot coallesce. 913 914 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); 915 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); 916 917 if (LHSIt->start < RHSIt->start) { 918 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); 919 if (LHSIt != LHS.begin()) --LHSIt; 920 } else if (RHSIt->start < LHSIt->start) { 921 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); 922 if (RHSIt != RHS.begin()) --RHSIt; 923 } 924 925 SmallVector<unsigned, 8> EliminatedLHSVals; 926 927 while (1) { 928 // Determine if these live intervals overlap. 929 bool Overlaps = false; 930 if (LHSIt->start <= RHSIt->start) 931 Overlaps = LHSIt->end > RHSIt->start; 932 else 933 Overlaps = RHSIt->end > LHSIt->start; 934 935 // If the live intervals overlap, there are two interesting cases: if the 936 // LHS interval is defined by a copy from the RHS, it's ok and we record 937 // that the LHS value # is the same as the RHS. If it's not, then we cannot 938 // coallesce these live ranges and we bail out. 939 if (Overlaps) { 940 // If we haven't already recorded that this value # is safe, check it. 941 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) { 942 // Copy from the RHS? 943 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId); 944 if (rep(SrcReg) != RHS.reg) 945 return false; // Nope, bail out. 946 947 EliminatedLHSVals.push_back(LHSIt->ValId); 948 } 949 950 // We know this entire LHS live range is okay, so skip it now. 951 if (++LHSIt == LHSEnd) break; 952 continue; 953 } 954 955 if (LHSIt->end < RHSIt->end) { 956 if (++LHSIt == LHSEnd) break; 957 } else { 958 // One interesting case to check here. It's possible that we have 959 // something like "X3 = Y" which defines a new value number in the LHS, 960 // and is the last use of this liverange of the RHS. In this case, we 961 // want to notice this copy (so that it gets coallesced away) even though 962 // the live ranges don't actually overlap. 963 if (LHSIt->start == RHSIt->end) { 964 if (InVector(LHSIt->ValId, EliminatedLHSVals)) { 965 // We already know that this value number is going to be merged in 966 // if coallescing succeeds. Just skip the liverange. 967 if (++LHSIt == LHSEnd) break; 968 } else { 969 // Otherwise, if this is a copy from the RHS, mark it as being merged 970 // in. 971 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) { 972 EliminatedLHSVals.push_back(LHSIt->ValId); 973 974 // We know this entire LHS live range is okay, so skip it now. 975 if (++LHSIt == LHSEnd) break; 976 } 977 } 978 } 979 980 if (++RHSIt == RHSEnd) break; 981 } 982 } 983 984 // If we got here, we know that the coallescing will be successful and that 985 // the value numbers in EliminatedLHSVals will all be merged together. Since 986 // the most common case is that EliminatedLHSVals has a single number, we 987 // optimize for it: if there is more than one value, we merge them all into 988 // the lowest numbered one, then handle the interval as if we were merging 989 // with one value number. 990 unsigned LHSValNo; 991 if (EliminatedLHSVals.size() > 1) { 992 // Loop through all the equal value numbers merging them into the smallest 993 // one. 994 unsigned Smallest = EliminatedLHSVals[0]; 995 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { 996 if (EliminatedLHSVals[i] < Smallest) { 997 // Merge the current notion of the smallest into the smaller one. 998 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); 999 Smallest = EliminatedLHSVals[i]; 1000 } else { 1001 // Merge into the smallest. 1002 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); 1003 } 1004 } 1005 LHSValNo = Smallest; 1006 } else { 1007 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); 1008 LHSValNo = EliminatedLHSVals[0]; 1009 } 1010 1011 // Okay, now that there is a single LHS value number that we're merging the 1012 // RHS into, update the value number info for the LHS to indicate that the 1013 // value number is defined where the RHS value number was. 1014 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0)); 1015 1016 // Okay, the final step is to loop over the RHS live intervals, adding them to 1017 // the LHS. 1018 LHS.MergeRangesInAsValue(RHS, LHSValNo); 1019 LHS.weight += RHS.weight; 1020 1021 return true; 1022} 1023 1024/// JoinIntervals - Attempt to join these two intervals. On failure, this 1025/// returns false. Otherwise, if one of the intervals being joined is a 1026/// physreg, this method always canonicalizes LHS to be it. The output 1027/// "RHS" will not have been modified, so we can use this information 1028/// below to update aliases. 1029bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) { 1030 // Compute the final value assignment, assuming that the live ranges can be 1031 // coallesced. 1032 SmallVector<int, 16> LHSValNoAssignments; 1033 SmallVector<int, 16> RHSValNoAssignments; 1034 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo; 1035 1036 // Compute ultimate value numbers for the LHS and RHS values. 1037 if (RHS.containsOneValue()) { 1038 // Copies from a liveinterval with a single value are simple to handle and 1039 // very common, handle the special case here. This is important, because 1040 // often RHS is small and LHS is large (e.g. a physreg). 1041 1042 // Find out if the RHS is defined as a copy from some value in the LHS. 1043 int RHSValID = -1; 1044 std::pair<unsigned,unsigned> RHSValNoInfo; 1045 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0); 1046 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { 1047 // If RHS is not defined as a copy from the LHS, we can use simpler and 1048 // faster checks to see if the live ranges are coallescable. This joiner 1049 // can't swap the LHS/RHS intervals though. 1050 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { 1051 return SimpleJoin(LHS, RHS); 1052 } else { 1053 RHSValNoInfo = RHS.getValNumInfo(0); 1054 } 1055 } else { 1056 // It was defined as a copy from the LHS, find out what value # it is. 1057 unsigned ValInst = RHS.getInstForValNum(0); 1058 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1059 RHSValNoInfo = LHS.getValNumInfo(RHSValID); 1060 } 1061 1062 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1063 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1064 ValueNumberInfo.resize(LHS.getNumValNums()); 1065 1066 // Okay, *all* of the values in LHS that are defined as a copy from RHS 1067 // should now get updated. 1068 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1069 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) { 1070 if (rep(LHSSrcReg) != RHS.reg) { 1071 // If this is not a copy from the RHS, its value number will be 1072 // unmodified by the coallescing. 1073 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1074 LHSValNoAssignments[VN] = VN; 1075 } else if (RHSValID == -1) { 1076 // Otherwise, it is a copy from the RHS, and we don't already have a 1077 // value# for it. Keep the current value number, but remember it. 1078 LHSValNoAssignments[VN] = RHSValID = VN; 1079 ValueNumberInfo[VN] = RHSValNoInfo; 1080 } else { 1081 // Otherwise, use the specified value #. 1082 LHSValNoAssignments[VN] = RHSValID; 1083 if (VN != (unsigned)RHSValID) 1084 ValueNumberInfo[VN].first = ~1U; 1085 else 1086 ValueNumberInfo[VN] = RHSValNoInfo; 1087 } 1088 } else { 1089 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1090 LHSValNoAssignments[VN] = VN; 1091 } 1092 } 1093 1094 assert(RHSValID != -1 && "Didn't find value #?"); 1095 RHSValNoAssignments[0] = RHSValID; 1096 1097 } else { 1098 // Loop over the value numbers of the LHS, seeing if any are defined from 1099 // the RHS. 1100 SmallVector<int, 16> LHSValsDefinedFromRHS; 1101 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1); 1102 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1103 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN); 1104 if (ValSrcReg == 0) // Src not defined by a copy? 1105 continue; 1106 1107 // DstReg is known to be a register in the LHS interval. If the src is 1108 // from the RHS interval, we can use its value #. 1109 if (rep(ValSrcReg) != RHS.reg) 1110 continue; 1111 1112 // Figure out the value # from the RHS. 1113 unsigned ValInst = LHS.getInstForValNum(VN); 1114 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId; 1115 } 1116 1117 // Loop over the value numbers of the RHS, seeing if any are defined from 1118 // the LHS. 1119 SmallVector<int, 16> RHSValsDefinedFromLHS; 1120 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1); 1121 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1122 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN); 1123 if (ValSrcReg == 0) // Src not defined by a copy? 1124 continue; 1125 1126 // DstReg is known to be a register in the RHS interval. If the src is 1127 // from the LHS interval, we can use its value #. 1128 if (rep(ValSrcReg) != LHS.reg) 1129 continue; 1130 1131 // Figure out the value # from the LHS. 1132 unsigned ValInst = RHS.getInstForValNum(VN); 1133 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1134 } 1135 1136 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1137 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1138 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1139 1140 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1141 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U) 1142 continue; 1143 ComputeUltimateVN(VN, ValueNumberInfo, 1144 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1145 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS); 1146 } 1147 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1148 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U) 1149 continue; 1150 // If this value number isn't a copy from the LHS, it's a new number. 1151 if (RHSValsDefinedFromLHS[VN] == -1) { 1152 ValueNumberInfo.push_back(RHS.getValNumInfo(VN)); 1153 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1; 1154 continue; 1155 } 1156 1157 ComputeUltimateVN(VN, ValueNumberInfo, 1158 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1159 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS); 1160 } 1161 } 1162 1163 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1164 // interval lists to see if these intervals are coallescable. 1165 LiveInterval::const_iterator I = LHS.begin(); 1166 LiveInterval::const_iterator IE = LHS.end(); 1167 LiveInterval::const_iterator J = RHS.begin(); 1168 LiveInterval::const_iterator JE = RHS.end(); 1169 1170 // Skip ahead until the first place of potential sharing. 1171 if (I->start < J->start) { 1172 I = std::upper_bound(I, IE, J->start); 1173 if (I != LHS.begin()) --I; 1174 } else if (J->start < I->start) { 1175 J = std::upper_bound(J, JE, I->start); 1176 if (J != RHS.begin()) --J; 1177 } 1178 1179 while (1) { 1180 // Determine if these two live ranges overlap. 1181 bool Overlaps; 1182 if (I->start < J->start) { 1183 Overlaps = I->end > J->start; 1184 } else { 1185 Overlaps = J->end > I->start; 1186 } 1187 1188 // If so, check value # info to determine if they are really different. 1189 if (Overlaps) { 1190 // If the live range overlap will map to the same value number in the 1191 // result liverange, we can still coallesce them. If not, we can't. 1192 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId]) 1193 return false; 1194 } 1195 1196 if (I->end < J->end) { 1197 ++I; 1198 if (I == IE) break; 1199 } else { 1200 ++J; 1201 if (J == JE) break; 1202 } 1203 } 1204 1205 // If we get here, we know that we can coallesce the live ranges. Ask the 1206 // intervals to coallesce themselves now. 1207 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], 1208 ValueNumberInfo); 1209 return true; 1210} 1211 1212 1213namespace { 1214 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1215 // depth of the basic block (the unsigned), and then on the MBB number. 1216 struct DepthMBBCompare { 1217 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1218 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1219 if (LHS.first > RHS.first) return true; // Deeper loops first 1220 return LHS.first == RHS.first && 1221 LHS.second->getNumber() < RHS.second->getNumber(); 1222 } 1223 }; 1224} 1225 1226 1227void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB, 1228 std::vector<CopyRec> &TryAgain) { 1229 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n"); 1230 1231 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1232 MII != E;) { 1233 MachineInstr *Inst = MII++; 1234 1235 // If this isn't a copy, we can't join intervals. 1236 unsigned SrcReg, DstReg; 1237 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; 1238 1239 if (!JoinCopy(Inst, SrcReg, DstReg)) 1240 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg)); 1241 } 1242} 1243 1244 1245void LiveIntervals::joinIntervals() { 1246 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); 1247 1248 std::vector<CopyRec> TryAgainList; 1249 1250 const LoopInfo &LI = getAnalysis<LoopInfo>(); 1251 if (LI.begin() == LI.end()) { 1252 // If there are no loops in the function, join intervals in function order. 1253 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1254 I != E; ++I) 1255 CopyCoallesceInMBB(I, TryAgainList); 1256 } else { 1257 // Otherwise, join intervals in inner loops before other intervals. 1258 // Unfortunately we can't just iterate over loop hierarchy here because 1259 // there may be more MBB's than BB's. Collect MBB's for sorting. 1260 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1261 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1262 I != E; ++I) 1263 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 1264 1265 // Sort by loop depth. 1266 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1267 1268 // Finally, join intervals in loop nest order. 1269 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1270 CopyCoallesceInMBB(MBBs[i].second, TryAgainList); 1271 } 1272 1273 // Joining intervals can allow other intervals to be joined. Iteratively join 1274 // until we make no progress. 1275 bool ProgressMade = true; 1276 while (ProgressMade) { 1277 ProgressMade = false; 1278 1279 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1280 CopyRec &TheCopy = TryAgainList[i]; 1281 if (TheCopy.MI && 1282 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) { 1283 TheCopy.MI = 0; // Mark this one as done. 1284 ProgressMade = true; 1285 } 1286 } 1287 } 1288 1289 DEBUG(std::cerr << "*** Register mapping ***\n"); 1290 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i) 1291 if (r2rMap_[i]) { 1292 std::cerr << " reg " << i << " -> "; 1293 printRegName(r2rMap_[i]); 1294 std::cerr << "\n"; 1295 }); 1296} 1297 1298/// Return true if the two specified registers belong to different register 1299/// classes. The registers may be either phys or virt regs. 1300bool LiveIntervals::differingRegisterClasses(unsigned RegA, 1301 unsigned RegB) const { 1302 1303 // Get the register classes for the first reg. 1304 if (MRegisterInfo::isPhysicalRegister(RegA)) { 1305 assert(MRegisterInfo::isVirtualRegister(RegB) && 1306 "Shouldn't consider two physregs!"); 1307 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 1308 } 1309 1310 // Compare against the regclass for the second reg. 1311 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 1312 if (MRegisterInfo::isVirtualRegister(RegB)) 1313 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 1314 else 1315 return !RegClass->contains(RegB); 1316} 1317 1318LiveInterval LiveIntervals::createInterval(unsigned reg) { 1319 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 1320 (float)HUGE_VAL : 0.0F; 1321 return LiveInterval(reg, Weight); 1322} 1323