LiveIntervalAnalysis.cpp revision 97af751deb9b26fd42fbcee082da9ccc4ded5b45
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36#include <cmath> 37using namespace llvm; 38 39namespace { 40 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 41 42 static Statistic<> numIntervals 43 ("liveintervals", "Number of original intervals"); 44 45 static Statistic<> numIntervalsAfter 46 ("liveintervals", "Number of intervals after coalescing"); 47 48 static Statistic<> numJoins 49 ("liveintervals", "Number of interval joins performed"); 50 51 static Statistic<> numPeep 52 ("liveintervals", "Number of identity moves eliminated after coalescing"); 53 54 static Statistic<> numFolded 55 ("liveintervals", "Number of loads/stores folded into instructions"); 56 57 static cl::opt<bool> 58 EnableJoining("join-liveintervals", 59 cl::desc("Coallesce copies (default=true)"), 60 cl::init(true)); 61} 62 63void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 64 AU.addRequired<LiveVariables>(); 65 AU.addPreservedID(PHIEliminationID); 66 AU.addRequiredID(PHIEliminationID); 67 AU.addRequiredID(TwoAddressInstructionPassID); 68 AU.addRequired<LoopInfo>(); 69 MachineFunctionPass::getAnalysisUsage(AU); 70} 71 72void LiveIntervals::releaseMemory() { 73 mi2iMap_.clear(); 74 i2miMap_.clear(); 75 r2iMap_.clear(); 76 r2rMap_.clear(); 77} 78 79 80static bool isZeroLengthInterval(LiveInterval *li) { 81 for (LiveInterval::Ranges::const_iterator 82 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) 83 if (i->end - i->start > LiveIntervals::InstrSlots::NUM) 84 return false; 85 return true; 86} 87 88 89/// runOnMachineFunction - Register allocate the whole function 90/// 91bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 92 mf_ = &fn; 93 tm_ = &fn.getTarget(); 94 mri_ = tm_->getRegisterInfo(); 95 tii_ = tm_->getInstrInfo(); 96 lv_ = &getAnalysis<LiveVariables>(); 97 allocatableRegs_ = mri_->getAllocatableSet(fn); 98 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 99 100 // If this function has any live ins, insert a dummy instruction at the 101 // beginning of the function that we will pretend "defines" the values. This 102 // is to make the interval analysis simpler by providing a number. 103 if (fn.livein_begin() != fn.livein_end()) { 104 unsigned FirstLiveIn = fn.livein_begin()->first; 105 106 // Find a reg class that contains this live in. 107 const TargetRegisterClass *RC = 0; 108 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), 109 E = mri_->regclass_end(); RCI != E; ++RCI) 110 if ((*RCI)->contains(FirstLiveIn)) { 111 RC = *RCI; 112 break; 113 } 114 115 MachineInstr *OldFirstMI = fn.begin()->begin(); 116 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), 117 FirstLiveIn, FirstLiveIn, RC); 118 assert(OldFirstMI != fn.begin()->begin() && 119 "copyRetToReg didn't insert anything!"); 120 } 121 122 // Number MachineInstrs and MachineBasicBlocks. 123 // Initialize MBB indexes to a sentinal. 124 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U); 125 126 unsigned MIIndex = 0; 127 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); 128 MBB != E; ++MBB) { 129 // Set the MBB2IdxMap entry for this MBB. 130 MBB2IdxMap[MBB->getNumber()] = MIIndex; 131 132 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 133 I != E; ++I) { 134 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second; 135 assert(inserted && "multiple MachineInstr -> index mappings"); 136 i2miMap_.push_back(I); 137 MIIndex += InstrSlots::NUM; 138 } 139 } 140 141 // Note intervals due to live-in values. 142 if (fn.livein_begin() != fn.livein_end()) { 143 MachineBasicBlock *Entry = fn.begin(); 144 for (MachineFunction::livein_iterator I = fn.livein_begin(), 145 E = fn.livein_end(); I != E; ++I) { 146 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 147 getOrCreateInterval(I->first), 0); 148 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) 149 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 150 getOrCreateInterval(*AS), 0); 151 } 152 } 153 154 computeIntervals(); 155 156 numIntervals += getNumIntervals(); 157 158 DOUT << "********** INTERVALS **********\n"; 159 for (iterator I = begin(), E = end(); I != E; ++I) { 160 I->second.print(DOUT, mri_); 161 DOUT << "\n"; 162 } 163 164 // Join (coallesce) intervals if requested. 165 if (EnableJoining) joinIntervals(); 166 167 numIntervalsAfter += getNumIntervals(); 168 169 170 // perform a final pass over the instructions and compute spill 171 // weights, coalesce virtual registers and remove identity moves. 172 const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); 173 174 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 175 mbbi != mbbe; ++mbbi) { 176 MachineBasicBlock* mbb = mbbi; 177 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 178 179 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 180 mii != mie; ) { 181 // if the move will be an identity move delete it 182 unsigned srcReg, dstReg, RegRep; 183 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 184 (RegRep = rep(srcReg)) == rep(dstReg)) { 185 // remove from def list 186 getOrCreateInterval(RegRep); 187 RemoveMachineInstrFromMaps(mii); 188 mii = mbbi->erase(mii); 189 ++numPeep; 190 } 191 else { 192 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { 193 const MachineOperand &mop = mii->getOperand(i); 194 if (mop.isRegister() && mop.getReg() && 195 MRegisterInfo::isVirtualRegister(mop.getReg())) { 196 // replace register with representative register 197 unsigned reg = rep(mop.getReg()); 198 mii->getOperand(i).setReg(reg); 199 200 LiveInterval &RegInt = getInterval(reg); 201 RegInt.weight += 202 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 203 } 204 } 205 ++mii; 206 } 207 } 208 } 209 210 211 for (iterator I = begin(), E = end(); I != E; ++I) { 212 LiveInterval &LI = I->second; 213 if (MRegisterInfo::isVirtualRegister(LI.reg)) { 214 // If the live interval length is essentially zero, i.e. in every live 215 // range the use follows def immediately, it doesn't make sense to spill 216 // it and hope it will be easier to allocate for this li. 217 if (isZeroLengthInterval(&LI)) 218 LI.weight = HUGE_VALF; 219 220 // Divide the weight of the interval by its size. This encourages 221 // spilling of intervals that are large and have few uses, and 222 // discourages spilling of small intervals with many uses. 223 unsigned Size = 0; 224 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II) 225 Size += II->end - II->start; 226 227 LI.weight /= Size; 228 } 229 } 230 231 DEBUG(dump()); 232 return true; 233} 234 235/// print - Implement the dump method. 236void LiveIntervals::print(std::ostream &O, const Module* ) const { 237 O << "********** INTERVALS **********\n"; 238 for (const_iterator I = begin(), E = end(); I != E; ++I) { 239 I->second.print(DOUT, mri_); 240 DOUT << "\n"; 241 } 242 243 O << "********** MACHINEINSTRS **********\n"; 244 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 245 mbbi != mbbe; ++mbbi) { 246 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 247 for (MachineBasicBlock::iterator mii = mbbi->begin(), 248 mie = mbbi->end(); mii != mie; ++mii) { 249 O << getInstructionIndex(mii) << '\t' << *mii; 250 } 251 } 252} 253 254/// CreateNewLiveInterval - Create a new live interval with the given live 255/// ranges. The new live interval will have an infinite spill weight. 256LiveInterval& 257LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI, 258 const std::vector<LiveRange> &LRs) { 259 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg); 260 261 // Create a new virtual register for the spill interval. 262 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC); 263 264 // Replace the old virtual registers in the machine operands with the shiny 265 // new one. 266 for (std::vector<LiveRange>::const_iterator 267 I = LRs.begin(), E = LRs.end(); I != E; ++I) { 268 unsigned Index = getBaseIndex(I->start); 269 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM; 270 271 for (; Index != End; Index += InstrSlots::NUM) { 272 // Skip deleted instructions 273 while (Index != End && !getInstructionFromIndex(Index)) 274 Index += InstrSlots::NUM; 275 276 if (Index == End) break; 277 278 MachineInstr *MI = getInstructionFromIndex(Index); 279 280 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) { 281 MachineOperand &MOp = MI->getOperand(J); 282 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg) 283 MOp.setReg(NewVReg); 284 } 285 } 286 } 287 288 LiveInterval &NewLI = getOrCreateInterval(NewVReg); 289 290 // The spill weight is now infinity as it cannot be spilled again 291 NewLI.weight = float(HUGE_VAL); 292 293 for (std::vector<LiveRange>::const_iterator 294 I = LRs.begin(), E = LRs.end(); I != E; ++I) { 295 DOUT << " Adding live range " << *I << " to new interval\n"; 296 NewLI.addRange(*I); 297 } 298 299 DOUT << "Created new live interval " << NewLI << "\n"; 300 return NewLI; 301} 302 303std::vector<LiveInterval*> LiveIntervals:: 304addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 305 // since this is called after the analysis is done we don't know if 306 // LiveVariables is available 307 lv_ = getAnalysisToUpdate<LiveVariables>(); 308 309 std::vector<LiveInterval*> added; 310 311 assert(li.weight != HUGE_VALF && 312 "attempt to spill already spilled interval!"); 313 314 DOUT << "\t\t\t\tadding intervals for spills for interval: "; 315 li.print(DOUT, mri_); 316 DOUT << '\n'; 317 318 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 319 320 for (LiveInterval::Ranges::const_iterator 321 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 322 unsigned index = getBaseIndex(i->start); 323 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 324 for (; index != end; index += InstrSlots::NUM) { 325 // skip deleted instructions 326 while (index != end && !getInstructionFromIndex(index)) 327 index += InstrSlots::NUM; 328 if (index == end) break; 329 330 MachineInstr *MI = getInstructionFromIndex(index); 331 332 RestartInstruction: 333 for (unsigned i = 0; i != MI->getNumOperands(); ++i) { 334 MachineOperand& mop = MI->getOperand(i); 335 if (mop.isRegister() && mop.getReg() == li.reg) { 336 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) { 337 // Attempt to fold the memory reference into the instruction. If we 338 // can do this, we don't need to insert spill code. 339 if (lv_) 340 lv_->instructionChanged(MI, fmi); 341 MachineBasicBlock &MBB = *MI->getParent(); 342 vrm.virtFolded(li.reg, MI, i, fmi); 343 mi2iMap_.erase(MI); 344 i2miMap_[index/InstrSlots::NUM] = fmi; 345 mi2iMap_[fmi] = index; 346 MI = MBB.insert(MBB.erase(MI), fmi); 347 ++numFolded; 348 // Folding the load/store can completely change the instruction in 349 // unpredictable ways, rescan it from the beginning. 350 goto RestartInstruction; 351 } else { 352 // Create a new virtual register for the spill interval. 353 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc); 354 355 // Scan all of the operands of this instruction rewriting operands 356 // to use NewVReg instead of li.reg as appropriate. We do this for 357 // two reasons: 358 // 359 // 1. If the instr reads the same spilled vreg multiple times, we 360 // want to reuse the NewVReg. 361 // 2. If the instr is a two-addr instruction, we are required to 362 // keep the src/dst regs pinned. 363 // 364 // Keep track of whether we replace a use and/or def so that we can 365 // create the spill interval with the appropriate range. 366 mop.setReg(NewVReg); 367 368 bool HasUse = mop.isUse(); 369 bool HasDef = mop.isDef(); 370 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { 371 if (MI->getOperand(j).isReg() && 372 MI->getOperand(j).getReg() == li.reg) { 373 MI->getOperand(j).setReg(NewVReg); 374 HasUse |= MI->getOperand(j).isUse(); 375 HasDef |= MI->getOperand(j).isDef(); 376 } 377 } 378 379 // create a new register for this spill 380 vrm.grow(); 381 vrm.assignVirt2StackSlot(NewVReg, slot); 382 LiveInterval &nI = getOrCreateInterval(NewVReg); 383 assert(nI.empty()); 384 385 // the spill weight is now infinity as it 386 // cannot be spilled again 387 nI.weight = HUGE_VALF; 388 389 if (HasUse) { 390 LiveRange LR(getLoadIndex(index), getUseIndex(index), 391 nI.getNextValue(~0U, 0)); 392 DOUT << " +" << LR; 393 nI.addRange(LR); 394 } 395 if (HasDef) { 396 LiveRange LR(getDefIndex(index), getStoreIndex(index), 397 nI.getNextValue(~0U, 0)); 398 DOUT << " +" << LR; 399 nI.addRange(LR); 400 } 401 402 added.push_back(&nI); 403 404 // update live variables if it is available 405 if (lv_) 406 lv_->addVirtualRegisterKilled(NewVReg, MI); 407 408 DOUT << "\t\t\t\tadded new interval: "; 409 nI.print(DOUT, mri_); 410 DOUT << '\n'; 411 } 412 } 413 } 414 } 415 } 416 417 return added; 418} 419 420void LiveIntervals::printRegName(unsigned reg) const { 421 if (MRegisterInfo::isPhysicalRegister(reg)) 422 llvm_cerr << mri_->getName(reg); 423 else 424 llvm_cerr << "%reg" << reg; 425} 426 427/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to 428/// two addr elimination. 429static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg, 430 const TargetInstrInfo *TII) { 431 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 432 MachineOperand &MO1 = MI->getOperand(i); 433 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { 434 for (unsigned j = i+1; j < e; ++j) { 435 MachineOperand &MO2 = MI->getOperand(j); 436 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && 437 TII->getOperandConstraint(MI->getOpcode(),j,TOI::TIED_TO) == (int)i) 438 return true; 439 } 440 } 441 } 442 return false; 443} 444 445void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 446 MachineBasicBlock::iterator mi, 447 unsigned MIIdx, 448 LiveInterval &interval) { 449 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); 450 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 451 452 // Virtual registers may be defined multiple times (due to phi 453 // elimination and 2-addr elimination). Much of what we do only has to be 454 // done once for the vreg. We use an empty interval to detect the first 455 // time we see a vreg. 456 if (interval.empty()) { 457 // Get the Idx of the defining instructions. 458 unsigned defIndex = getDefIndex(MIIdx); 459 460 unsigned ValNum; 461 unsigned SrcReg, DstReg; 462 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 463 ValNum = interval.getNextValue(~0U, 0); 464 else 465 ValNum = interval.getNextValue(defIndex, SrcReg); 466 467 assert(ValNum == 0 && "First value in interval is not 0?"); 468 ValNum = 0; // Clue in the optimizer. 469 470 // Loop over all of the blocks that the vreg is defined in. There are 471 // two cases we have to handle here. The most common case is a vreg 472 // whose lifetime is contained within a basic block. In this case there 473 // will be a single kill, in MBB, which comes after the definition. 474 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 475 // FIXME: what about dead vars? 476 unsigned killIdx; 477 if (vi.Kills[0] != mi) 478 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 479 else 480 killIdx = defIndex+1; 481 482 // If the kill happens after the definition, we have an intra-block 483 // live range. 484 if (killIdx > defIndex) { 485 assert(vi.AliveBlocks.empty() && 486 "Shouldn't be alive across any blocks!"); 487 LiveRange LR(defIndex, killIdx, ValNum); 488 interval.addRange(LR); 489 DOUT << " +" << LR << "\n"; 490 return; 491 } 492 } 493 494 // The other case we handle is when a virtual register lives to the end 495 // of the defining block, potentially live across some blocks, then is 496 // live into some number of blocks, but gets killed. Start by adding a 497 // range that goes from this definition to the end of the defining block. 498 LiveRange NewLR(defIndex, 499 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 500 ValNum); 501 DOUT << " +" << NewLR; 502 interval.addRange(NewLR); 503 504 // Iterate over all of the blocks that the variable is completely 505 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 506 // live interval. 507 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 508 if (vi.AliveBlocks[i]) { 509 MachineBasicBlock *MBB = mf_->getBlockNumbered(i); 510 if (!MBB->empty()) { 511 LiveRange LR(getMBBStartIdx(i), 512 getInstructionIndex(&MBB->back()) + InstrSlots::NUM, 513 ValNum); 514 interval.addRange(LR); 515 DOUT << " +" << LR; 516 } 517 } 518 } 519 520 // Finally, this virtual register is live from the start of any killing 521 // block to the 'use' slot of the killing instruction. 522 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 523 MachineInstr *Kill = vi.Kills[i]; 524 LiveRange LR(getMBBStartIdx(Kill->getParent()), 525 getUseIndex(getInstructionIndex(Kill))+1, 526 ValNum); 527 interval.addRange(LR); 528 DOUT << " +" << LR; 529 } 530 531 } else { 532 // If this is the second time we see a virtual register definition, it 533 // must be due to phi elimination or two addr elimination. If this is 534 // the result of two address elimination, then the vreg is one of the 535 // def-and-use register operand. 536 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) { 537 // If this is a two-address definition, then we have already processed 538 // the live range. The only problem is that we didn't realize there 539 // are actually two values in the live interval. Because of this we 540 // need to take the LiveRegion that defines this register and split it 541 // into two values. 542 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 543 unsigned RedefIndex = getDefIndex(MIIdx); 544 545 // Delete the initial value, which should be short and continuous, 546 // because the 2-addr copy must be in the same MBB as the redef. 547 interval.removeRange(DefIndex, RedefIndex); 548 549 // Two-address vregs should always only be redefined once. This means 550 // that at this point, there should be exactly one value number in it. 551 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!"); 552 553 // The new value number (#1) is defined by the instruction we claimed 554 // defined value #0. 555 unsigned ValNo = interval.getNextValue(0, 0); 556 interval.setValueNumberInfo(1, interval.getValNumInfo(0)); 557 558 // Value#0 is now defined by the 2-addr instruction. 559 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U)); 560 561 // Add the new live interval which replaces the range for the input copy. 562 LiveRange LR(DefIndex, RedefIndex, ValNo); 563 DOUT << " replace range with " << LR; 564 interval.addRange(LR); 565 566 // If this redefinition is dead, we need to add a dummy unit live 567 // range covering the def slot. 568 if (lv_->RegisterDefIsDead(mi, interval.reg)) 569 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 570 571 DOUT << "RESULT: "; 572 interval.print(DOUT, mri_); 573 574 } else { 575 // Otherwise, this must be because of phi elimination. If this is the 576 // first redefinition of the vreg that we have seen, go back and change 577 // the live range in the PHI block to be a different value number. 578 if (interval.containsOneValue()) { 579 assert(vi.Kills.size() == 1 && 580 "PHI elimination vreg should have one kill, the PHI itself!"); 581 582 // Remove the old range that we now know has an incorrect number. 583 MachineInstr *Killer = vi.Kills[0]; 584 unsigned Start = getMBBStartIdx(Killer->getParent()); 585 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 586 DOUT << "Removing [" << Start << "," << End << "] from: "; 587 interval.print(DOUT, mri_); DOUT << "\n"; 588 interval.removeRange(Start, End); 589 DOUT << "RESULT: "; interval.print(DOUT, mri_); 590 591 // Replace the interval with one of a NEW value number. Note that this 592 // value number isn't actually defined by an instruction, weird huh? :) 593 LiveRange LR(Start, End, interval.getNextValue(~0U, 0)); 594 DOUT << " replace range with " << LR; 595 interval.addRange(LR); 596 DOUT << "RESULT: "; interval.print(DOUT, mri_); 597 } 598 599 // In the case of PHI elimination, each variable definition is only 600 // live until the end of the block. We've already taken care of the 601 // rest of the live range. 602 unsigned defIndex = getDefIndex(MIIdx); 603 604 unsigned ValNum; 605 unsigned SrcReg, DstReg; 606 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 607 ValNum = interval.getNextValue(~0U, 0); 608 else 609 ValNum = interval.getNextValue(defIndex, SrcReg); 610 611 LiveRange LR(defIndex, 612 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum); 613 interval.addRange(LR); 614 DOUT << " +" << LR; 615 } 616 } 617 618 DOUT << '\n'; 619} 620 621void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 622 MachineBasicBlock::iterator mi, 623 unsigned MIIdx, 624 LiveInterval &interval, 625 unsigned SrcReg) { 626 // A physical register cannot be live across basic block, so its 627 // lifetime must end somewhere in its defining basic block. 628 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); 629 630 unsigned baseIndex = MIIdx; 631 unsigned start = getDefIndex(baseIndex); 632 unsigned end = start; 633 634 // If it is not used after definition, it is considered dead at 635 // the instruction defining it. Hence its interval is: 636 // [defSlot(def), defSlot(def)+1) 637 if (lv_->RegisterDefIsDead(mi, interval.reg)) { 638 DOUT << " dead"; 639 end = getDefIndex(start) + 1; 640 goto exit; 641 } 642 643 // If it is not dead on definition, it must be killed by a 644 // subsequent instruction. Hence its interval is: 645 // [defSlot(def), useSlot(kill)+1) 646 while (++mi != MBB->end()) { 647 baseIndex += InstrSlots::NUM; 648 if (lv_->KillsRegister(mi, interval.reg)) { 649 DOUT << " killed"; 650 end = getUseIndex(baseIndex) + 1; 651 goto exit; 652 } else if (lv_->ModifiesRegister(mi, interval.reg)) { 653 // Another instruction redefines the register before it is ever read. 654 // Then the register is essentially dead at the instruction that defines 655 // it. Hence its interval is: 656 // [defSlot(def), defSlot(def)+1) 657 DOUT << " dead"; 658 end = getDefIndex(start) + 1; 659 goto exit; 660 } 661 } 662 663 // The only case we should have a dead physreg here without a killing or 664 // instruction where we know it's dead is if it is live-in to the function 665 // and never used. 666 assert(!SrcReg && "physreg was not killed in defining block!"); 667 end = getDefIndex(start) + 1; // It's dead. 668 669exit: 670 assert(start < end && "did not find end of interval?"); 671 672 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U, 673 SrcReg)); 674 interval.addRange(LR); 675 DOUT << " +" << LR << '\n'; 676} 677 678void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 679 MachineBasicBlock::iterator MI, 680 unsigned MIIdx, 681 unsigned reg) { 682 if (MRegisterInfo::isVirtualRegister(reg)) 683 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); 684 else if (allocatableRegs_[reg]) { 685 unsigned SrcReg, DstReg; 686 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) 687 SrcReg = 0; 688 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); 689 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 690 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); 691 } 692} 693 694/// computeIntervals - computes the live intervals for virtual 695/// registers. for some ordering of the machine instructions [1,N] a 696/// live interval is an interval [i, j) where 1 <= i <= j < N for 697/// which a variable is live 698void LiveIntervals::computeIntervals() { 699 DOUT << "********** COMPUTING LIVE INTERVALS **********\n" 700 << "********** Function: " 701 << ((Value*)mf_->getFunction())->getName() << '\n'; 702 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); 703 704 // Track the index of the current machine instr. 705 unsigned MIIndex = 0; 706 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); 707 MBBI != E; ++MBBI) { 708 MachineBasicBlock *MBB = MBBI; 709 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; 710 711 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); 712 if (IgnoreFirstInstr) { 713 ++MI; 714 IgnoreFirstInstr = false; 715 MIIndex += InstrSlots::NUM; 716 } 717 718 for (; MI != miEnd; ++MI) { 719 DOUT << MIIndex << "\t" << *MI; 720 721 // Handle defs. 722 for (int i = MI->getNumOperands() - 1; i >= 0; --i) { 723 MachineOperand &MO = MI->getOperand(i); 724 // handle register defs - build intervals 725 if (MO.isRegister() && MO.getReg() && MO.isDef()) 726 handleRegisterDef(MBB, MI, MIIndex, MO.getReg()); 727 } 728 729 MIIndex += InstrSlots::NUM; 730 } 731 } 732} 733 734/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA 735/// being the source and IntB being the dest, thus this defines a value number 736/// in IntB. If the source value number (in IntA) is defined by a copy from B, 737/// see if we can merge these two pieces of B into a single value number, 738/// eliminating a copy. For example: 739/// 740/// A3 = B0 741/// ... 742/// B1 = A3 <- this copy 743/// 744/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 745/// value number to be replaced with B0 (which simplifies the B liveinterval). 746/// 747/// This returns true if an interval was modified. 748/// 749bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, 750 MachineInstr *CopyMI) { 751 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 752 753 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 754 // the example above. 755 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 756 unsigned BValNo = BLR->ValId; 757 758 // Get the location that B is defined at. Two options: either this value has 759 // an unknown definition point or it is defined at CopyIdx. If unknown, we 760 // can't process it. 761 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo); 762 if (BValNoDefIdx == ~0U) return false; 763 assert(BValNoDefIdx == CopyIdx && 764 "Copy doesn't define the value?"); 765 766 // AValNo is the value number in A that defines the copy, A0 in the example. 767 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); 768 unsigned AValNo = AValLR->ValId; 769 770 // If AValNo is defined as a copy from IntB, we can potentially process this. 771 772 // Get the instruction that defines this value number. 773 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo); 774 if (!SrcReg) return false; // Not defined by a copy. 775 776 // If the value number is not defined by a copy instruction, ignore it. 777 778 // If the source register comes from an interval other than IntB, we can't 779 // handle this. 780 if (rep(SrcReg) != IntB.reg) return false; 781 782 // Get the LiveRange in IntB that this value number starts with. 783 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo); 784 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1); 785 786 // Make sure that the end of the live range is inside the same block as 787 // CopyMI. 788 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1); 789 if (!ValLREndInst || 790 ValLREndInst->getParent() != CopyMI->getParent()) return false; 791 792 // Okay, we now know that ValLR ends in the same block that the CopyMI 793 // live-range starts. If there are no intervening live ranges between them in 794 // IntB, we can merge them. 795 if (ValLR+1 != BLR) return false; 796 797 DOUT << "\nExtending: "; IntB.print(DOUT, mri_); 798 799 // We are about to delete CopyMI, so need to remove it as the 'instruction 800 // that defines this value #'. 801 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0)); 802 803 // Okay, we can merge them. We need to insert a new liverange: 804 // [ValLR.end, BLR.begin) of either value number, then we merge the 805 // two value numbers. 806 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; 807 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 808 809 // If the IntB live range is assigned to a physical register, and if that 810 // physreg has aliases, 811 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { 812 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) { 813 LiveInterval &AliasLI = getInterval(*AS); 814 AliasLI.addRange(LiveRange(FillerStart, FillerEnd, 815 AliasLI.getNextValue(~0U, 0))); 816 } 817 } 818 819 // Okay, merge "B1" into the same value number as "B0". 820 if (BValNo != ValLR->ValId) 821 IntB.MergeValueNumberInto(BValNo, ValLR->ValId); 822 DOUT << " result = "; IntB.print(DOUT, mri_); 823 DOUT << "\n"; 824 825 // Finally, delete the copy instruction. 826 RemoveMachineInstrFromMaps(CopyMI); 827 CopyMI->eraseFromParent(); 828 ++numPeep; 829 return true; 830} 831 832 833/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 834/// which are the src/dst of the copy instruction CopyMI. This returns true 835/// if the copy was successfully coallesced away, or if it is never possible 836/// to coallesce these this copy, due to register constraints. It returns 837/// false if it is not currently possible to coallesce this interval, but 838/// it may be possible if other things get coallesced. 839bool LiveIntervals::JoinCopy(MachineInstr *CopyMI, 840 unsigned SrcReg, unsigned DstReg) { 841 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI; 842 843 // Get representative registers. 844 SrcReg = rep(SrcReg); 845 DstReg = rep(DstReg); 846 847 // If they are already joined we continue. 848 if (SrcReg == DstReg) { 849 DOUT << "\tCopy already coallesced.\n"; 850 return true; // Not coallescable. 851 } 852 853 // If they are both physical registers, we cannot join them. 854 if (MRegisterInfo::isPhysicalRegister(SrcReg) && 855 MRegisterInfo::isPhysicalRegister(DstReg)) { 856 DOUT << "\tCan not coallesce physregs.\n"; 857 return true; // Not coallescable. 858 } 859 860 // We only join virtual registers with allocatable physical registers. 861 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){ 862 DOUT << "\tSrc reg is unallocatable physreg.\n"; 863 return true; // Not coallescable. 864 } 865 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){ 866 DOUT << "\tDst reg is unallocatable physreg.\n"; 867 return true; // Not coallescable. 868 } 869 870 // If they are not of the same register class, we cannot join them. 871 if (differingRegisterClasses(SrcReg, DstReg)) { 872 DOUT << "\tSrc/Dest are different register classes.\n"; 873 return true; // Not coallescable. 874 } 875 876 LiveInterval &SrcInt = getInterval(SrcReg); 877 LiveInterval &DestInt = getInterval(DstReg); 878 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg && 879 "Register mapping is horribly broken!"); 880 881 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_); 882 DOUT << " and "; DestInt.print(DOUT, mri_); 883 DOUT << ": "; 884 885 // Okay, attempt to join these two intervals. On failure, this returns false. 886 // Otherwise, if one of the intervals being joined is a physreg, this method 887 // always canonicalizes DestInt to be it. The output "SrcInt" will not have 888 // been modified, so we can use this information below to update aliases. 889 if (!JoinIntervals(DestInt, SrcInt)) { 890 // Coallescing failed. 891 892 // If we can eliminate the copy without merging the live ranges, do so now. 893 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI)) 894 return true; 895 896 // Otherwise, we are unable to join the intervals. 897 DOUT << "Interference!\n"; 898 return false; 899 } 900 901 bool Swapped = SrcReg == DestInt.reg; 902 if (Swapped) 903 std::swap(SrcReg, DstReg); 904 assert(MRegisterInfo::isVirtualRegister(SrcReg) && 905 "LiveInterval::join didn't work right!"); 906 907 // If we're about to merge live ranges into a physical register live range, 908 // we have to update any aliased register's live ranges to indicate that they 909 // have clobbered values for this range. 910 if (MRegisterInfo::isPhysicalRegister(DstReg)) { 911 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS) 912 getInterval(*AS).MergeInClobberRanges(SrcInt); 913 } 914 915 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_); 916 DOUT << "\n"; 917 918 // If the intervals were swapped by Join, swap them back so that the register 919 // mapping (in the r2i map) is correct. 920 if (Swapped) SrcInt.swap(DestInt); 921 r2iMap_.erase(SrcReg); 922 r2rMap_[SrcReg] = DstReg; 923 924 // Finally, delete the copy instruction. 925 RemoveMachineInstrFromMaps(CopyMI); 926 CopyMI->eraseFromParent(); 927 ++numPeep; 928 ++numJoins; 929 return true; 930} 931 932/// ComputeUltimateVN - Assuming we are going to join two live intervals, 933/// compute what the resultant value numbers for each value in the input two 934/// ranges will be. This is complicated by copies between the two which can 935/// and will commonly cause multiple value numbers to be merged into one. 936/// 937/// VN is the value number that we're trying to resolve. InstDefiningValue 938/// keeps track of the new InstDefiningValue assignment for the result 939/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 940/// whether a value in this or other is a copy from the opposite set. 941/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 942/// already been assigned. 943/// 944/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 945/// contains the value number the copy is from. 946/// 947static unsigned ComputeUltimateVN(unsigned VN, 948 SmallVector<std::pair<unsigned, 949 unsigned>, 16> &ValueNumberInfo, 950 SmallVector<int, 16> &ThisFromOther, 951 SmallVector<int, 16> &OtherFromThis, 952 SmallVector<int, 16> &ThisValNoAssignments, 953 SmallVector<int, 16> &OtherValNoAssignments, 954 LiveInterval &ThisLI, LiveInterval &OtherLI) { 955 // If the VN has already been computed, just return it. 956 if (ThisValNoAssignments[VN] >= 0) 957 return ThisValNoAssignments[VN]; 958// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); 959 960 // If this val is not a copy from the other val, then it must be a new value 961 // number in the destination. 962 int OtherValNo = ThisFromOther[VN]; 963 if (OtherValNo == -1) { 964 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN)); 965 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1; 966 } 967 968 // Otherwise, this *is* a copy from the RHS. If the other side has already 969 // been computed, return it. 970 if (OtherValNoAssignments[OtherValNo] >= 0) 971 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo]; 972 973 // Mark this value number as currently being computed, then ask what the 974 // ultimate value # of the other value is. 975 ThisValNoAssignments[VN] = -2; 976 unsigned UltimateVN = 977 ComputeUltimateVN(OtherValNo, ValueNumberInfo, 978 OtherFromThis, ThisFromOther, 979 OtherValNoAssignments, ThisValNoAssignments, 980 OtherLI, ThisLI); 981 return ThisValNoAssignments[VN] = UltimateVN; 982} 983 984static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) { 985 return std::find(V.begin(), V.end(), Val) != V.end(); 986} 987 988/// SimpleJoin - Attempt to joint the specified interval into this one. The 989/// caller of this method must guarantee that the RHS only contains a single 990/// value number and that the RHS is not defined by a copy from this 991/// interval. This returns false if the intervals are not joinable, or it 992/// joins them and returns true. 993bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { 994 assert(RHS.containsOneValue()); 995 996 // Some number (potentially more than one) value numbers in the current 997 // interval may be defined as copies from the RHS. Scan the overlapping 998 // portions of the LHS and RHS, keeping track of this and looking for 999 // overlapping live ranges that are NOT defined as copies. If these exist, we 1000 // cannot coallesce. 1001 1002 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); 1003 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); 1004 1005 if (LHSIt->start < RHSIt->start) { 1006 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); 1007 if (LHSIt != LHS.begin()) --LHSIt; 1008 } else if (RHSIt->start < LHSIt->start) { 1009 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); 1010 if (RHSIt != RHS.begin()) --RHSIt; 1011 } 1012 1013 SmallVector<unsigned, 8> EliminatedLHSVals; 1014 1015 while (1) { 1016 // Determine if these live intervals overlap. 1017 bool Overlaps = false; 1018 if (LHSIt->start <= RHSIt->start) 1019 Overlaps = LHSIt->end > RHSIt->start; 1020 else 1021 Overlaps = RHSIt->end > LHSIt->start; 1022 1023 // If the live intervals overlap, there are two interesting cases: if the 1024 // LHS interval is defined by a copy from the RHS, it's ok and we record 1025 // that the LHS value # is the same as the RHS. If it's not, then we cannot 1026 // coallesce these live ranges and we bail out. 1027 if (Overlaps) { 1028 // If we haven't already recorded that this value # is safe, check it. 1029 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) { 1030 // Copy from the RHS? 1031 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId); 1032 if (rep(SrcReg) != RHS.reg) 1033 return false; // Nope, bail out. 1034 1035 EliminatedLHSVals.push_back(LHSIt->ValId); 1036 } 1037 1038 // We know this entire LHS live range is okay, so skip it now. 1039 if (++LHSIt == LHSEnd) break; 1040 continue; 1041 } 1042 1043 if (LHSIt->end < RHSIt->end) { 1044 if (++LHSIt == LHSEnd) break; 1045 } else { 1046 // One interesting case to check here. It's possible that we have 1047 // something like "X3 = Y" which defines a new value number in the LHS, 1048 // and is the last use of this liverange of the RHS. In this case, we 1049 // want to notice this copy (so that it gets coallesced away) even though 1050 // the live ranges don't actually overlap. 1051 if (LHSIt->start == RHSIt->end) { 1052 if (InVector(LHSIt->ValId, EliminatedLHSVals)) { 1053 // We already know that this value number is going to be merged in 1054 // if coallescing succeeds. Just skip the liverange. 1055 if (++LHSIt == LHSEnd) break; 1056 } else { 1057 // Otherwise, if this is a copy from the RHS, mark it as being merged 1058 // in. 1059 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) { 1060 EliminatedLHSVals.push_back(LHSIt->ValId); 1061 1062 // We know this entire LHS live range is okay, so skip it now. 1063 if (++LHSIt == LHSEnd) break; 1064 } 1065 } 1066 } 1067 1068 if (++RHSIt == RHSEnd) break; 1069 } 1070 } 1071 1072 // If we got here, we know that the coallescing will be successful and that 1073 // the value numbers in EliminatedLHSVals will all be merged together. Since 1074 // the most common case is that EliminatedLHSVals has a single number, we 1075 // optimize for it: if there is more than one value, we merge them all into 1076 // the lowest numbered one, then handle the interval as if we were merging 1077 // with one value number. 1078 unsigned LHSValNo; 1079 if (EliminatedLHSVals.size() > 1) { 1080 // Loop through all the equal value numbers merging them into the smallest 1081 // one. 1082 unsigned Smallest = EliminatedLHSVals[0]; 1083 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { 1084 if (EliminatedLHSVals[i] < Smallest) { 1085 // Merge the current notion of the smallest into the smaller one. 1086 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); 1087 Smallest = EliminatedLHSVals[i]; 1088 } else { 1089 // Merge into the smallest. 1090 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); 1091 } 1092 } 1093 LHSValNo = Smallest; 1094 } else { 1095 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); 1096 LHSValNo = EliminatedLHSVals[0]; 1097 } 1098 1099 // Okay, now that there is a single LHS value number that we're merging the 1100 // RHS into, update the value number info for the LHS to indicate that the 1101 // value number is defined where the RHS value number was. 1102 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0)); 1103 1104 // Okay, the final step is to loop over the RHS live intervals, adding them to 1105 // the LHS. 1106 LHS.MergeRangesInAsValue(RHS, LHSValNo); 1107 LHS.weight += RHS.weight; 1108 1109 return true; 1110} 1111 1112/// JoinIntervals - Attempt to join these two intervals. On failure, this 1113/// returns false. Otherwise, if one of the intervals being joined is a 1114/// physreg, this method always canonicalizes LHS to be it. The output 1115/// "RHS" will not have been modified, so we can use this information 1116/// below to update aliases. 1117bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) { 1118 // Compute the final value assignment, assuming that the live ranges can be 1119 // coallesced. 1120 SmallVector<int, 16> LHSValNoAssignments; 1121 SmallVector<int, 16> RHSValNoAssignments; 1122 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo; 1123 1124 // Compute ultimate value numbers for the LHS and RHS values. 1125 if (RHS.containsOneValue()) { 1126 // Copies from a liveinterval with a single value are simple to handle and 1127 // very common, handle the special case here. This is important, because 1128 // often RHS is small and LHS is large (e.g. a physreg). 1129 1130 // Find out if the RHS is defined as a copy from some value in the LHS. 1131 int RHSValID = -1; 1132 std::pair<unsigned,unsigned> RHSValNoInfo; 1133 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0); 1134 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { 1135 // If RHS is not defined as a copy from the LHS, we can use simpler and 1136 // faster checks to see if the live ranges are coallescable. This joiner 1137 // can't swap the LHS/RHS intervals though. 1138 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { 1139 return SimpleJoin(LHS, RHS); 1140 } else { 1141 RHSValNoInfo = RHS.getValNumInfo(0); 1142 } 1143 } else { 1144 // It was defined as a copy from the LHS, find out what value # it is. 1145 unsigned ValInst = RHS.getInstForValNum(0); 1146 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1147 RHSValNoInfo = LHS.getValNumInfo(RHSValID); 1148 } 1149 1150 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1151 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1152 ValueNumberInfo.resize(LHS.getNumValNums()); 1153 1154 // Okay, *all* of the values in LHS that are defined as a copy from RHS 1155 // should now get updated. 1156 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1157 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) { 1158 if (rep(LHSSrcReg) != RHS.reg) { 1159 // If this is not a copy from the RHS, its value number will be 1160 // unmodified by the coallescing. 1161 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1162 LHSValNoAssignments[VN] = VN; 1163 } else if (RHSValID == -1) { 1164 // Otherwise, it is a copy from the RHS, and we don't already have a 1165 // value# for it. Keep the current value number, but remember it. 1166 LHSValNoAssignments[VN] = RHSValID = VN; 1167 ValueNumberInfo[VN] = RHSValNoInfo; 1168 } else { 1169 // Otherwise, use the specified value #. 1170 LHSValNoAssignments[VN] = RHSValID; 1171 if (VN != (unsigned)RHSValID) 1172 ValueNumberInfo[VN].first = ~1U; 1173 else 1174 ValueNumberInfo[VN] = RHSValNoInfo; 1175 } 1176 } else { 1177 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1178 LHSValNoAssignments[VN] = VN; 1179 } 1180 } 1181 1182 assert(RHSValID != -1 && "Didn't find value #?"); 1183 RHSValNoAssignments[0] = RHSValID; 1184 1185 } else { 1186 // Loop over the value numbers of the LHS, seeing if any are defined from 1187 // the RHS. 1188 SmallVector<int, 16> LHSValsDefinedFromRHS; 1189 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1); 1190 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1191 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN); 1192 if (ValSrcReg == 0) // Src not defined by a copy? 1193 continue; 1194 1195 // DstReg is known to be a register in the LHS interval. If the src is 1196 // from the RHS interval, we can use its value #. 1197 if (rep(ValSrcReg) != RHS.reg) 1198 continue; 1199 1200 // Figure out the value # from the RHS. 1201 unsigned ValInst = LHS.getInstForValNum(VN); 1202 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId; 1203 } 1204 1205 // Loop over the value numbers of the RHS, seeing if any are defined from 1206 // the LHS. 1207 SmallVector<int, 16> RHSValsDefinedFromLHS; 1208 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1); 1209 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1210 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN); 1211 if (ValSrcReg == 0) // Src not defined by a copy? 1212 continue; 1213 1214 // DstReg is known to be a register in the RHS interval. If the src is 1215 // from the LHS interval, we can use its value #. 1216 if (rep(ValSrcReg) != LHS.reg) 1217 continue; 1218 1219 // Figure out the value # from the LHS. 1220 unsigned ValInst = RHS.getInstForValNum(VN); 1221 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1222 } 1223 1224 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1225 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1226 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1227 1228 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1229 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U) 1230 continue; 1231 ComputeUltimateVN(VN, ValueNumberInfo, 1232 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1233 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS); 1234 } 1235 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1236 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U) 1237 continue; 1238 // If this value number isn't a copy from the LHS, it's a new number. 1239 if (RHSValsDefinedFromLHS[VN] == -1) { 1240 ValueNumberInfo.push_back(RHS.getValNumInfo(VN)); 1241 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1; 1242 continue; 1243 } 1244 1245 ComputeUltimateVN(VN, ValueNumberInfo, 1246 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1247 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS); 1248 } 1249 } 1250 1251 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1252 // interval lists to see if these intervals are coallescable. 1253 LiveInterval::const_iterator I = LHS.begin(); 1254 LiveInterval::const_iterator IE = LHS.end(); 1255 LiveInterval::const_iterator J = RHS.begin(); 1256 LiveInterval::const_iterator JE = RHS.end(); 1257 1258 // Skip ahead until the first place of potential sharing. 1259 if (I->start < J->start) { 1260 I = std::upper_bound(I, IE, J->start); 1261 if (I != LHS.begin()) --I; 1262 } else if (J->start < I->start) { 1263 J = std::upper_bound(J, JE, I->start); 1264 if (J != RHS.begin()) --J; 1265 } 1266 1267 while (1) { 1268 // Determine if these two live ranges overlap. 1269 bool Overlaps; 1270 if (I->start < J->start) { 1271 Overlaps = I->end > J->start; 1272 } else { 1273 Overlaps = J->end > I->start; 1274 } 1275 1276 // If so, check value # info to determine if they are really different. 1277 if (Overlaps) { 1278 // If the live range overlap will map to the same value number in the 1279 // result liverange, we can still coallesce them. If not, we can't. 1280 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId]) 1281 return false; 1282 } 1283 1284 if (I->end < J->end) { 1285 ++I; 1286 if (I == IE) break; 1287 } else { 1288 ++J; 1289 if (J == JE) break; 1290 } 1291 } 1292 1293 // If we get here, we know that we can coallesce the live ranges. Ask the 1294 // intervals to coallesce themselves now. 1295 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], 1296 ValueNumberInfo); 1297 return true; 1298} 1299 1300 1301namespace { 1302 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1303 // depth of the basic block (the unsigned), and then on the MBB number. 1304 struct DepthMBBCompare { 1305 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1306 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1307 if (LHS.first > RHS.first) return true; // Deeper loops first 1308 return LHS.first == RHS.first && 1309 LHS.second->getNumber() < RHS.second->getNumber(); 1310 } 1311 }; 1312} 1313 1314 1315void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB, 1316 std::vector<CopyRec> &TryAgain) { 1317 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; 1318 1319 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1320 MII != E;) { 1321 MachineInstr *Inst = MII++; 1322 1323 // If this isn't a copy, we can't join intervals. 1324 unsigned SrcReg, DstReg; 1325 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; 1326 1327 if (!JoinCopy(Inst, SrcReg, DstReg)) 1328 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg)); 1329 } 1330} 1331 1332 1333void LiveIntervals::joinIntervals() { 1334 DOUT << "********** JOINING INTERVALS ***********\n"; 1335 1336 std::vector<CopyRec> TryAgainList; 1337 1338 const LoopInfo &LI = getAnalysis<LoopInfo>(); 1339 if (LI.begin() == LI.end()) { 1340 // If there are no loops in the function, join intervals in function order. 1341 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1342 I != E; ++I) 1343 CopyCoallesceInMBB(I, TryAgainList); 1344 } else { 1345 // Otherwise, join intervals in inner loops before other intervals. 1346 // Unfortunately we can't just iterate over loop hierarchy here because 1347 // there may be more MBB's than BB's. Collect MBB's for sorting. 1348 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1349 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1350 I != E; ++I) 1351 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 1352 1353 // Sort by loop depth. 1354 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1355 1356 // Finally, join intervals in loop nest order. 1357 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1358 CopyCoallesceInMBB(MBBs[i].second, TryAgainList); 1359 } 1360 1361 // Joining intervals can allow other intervals to be joined. Iteratively join 1362 // until we make no progress. 1363 bool ProgressMade = true; 1364 while (ProgressMade) { 1365 ProgressMade = false; 1366 1367 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1368 CopyRec &TheCopy = TryAgainList[i]; 1369 if (TheCopy.MI && 1370 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) { 1371 TheCopy.MI = 0; // Mark this one as done. 1372 ProgressMade = true; 1373 } 1374 } 1375 } 1376 1377 DOUT << "*** Register mapping ***\n"; 1378 for (int i = 0, e = r2rMap_.size(); i != e; ++i) 1379 if (r2rMap_[i]) { 1380 DOUT << " reg " << i << " -> "; 1381 DEBUG(printRegName(r2rMap_[i])); 1382 DOUT << "\n"; 1383 } 1384} 1385 1386/// Return true if the two specified registers belong to different register 1387/// classes. The registers may be either phys or virt regs. 1388bool LiveIntervals::differingRegisterClasses(unsigned RegA, 1389 unsigned RegB) const { 1390 1391 // Get the register classes for the first reg. 1392 if (MRegisterInfo::isPhysicalRegister(RegA)) { 1393 assert(MRegisterInfo::isVirtualRegister(RegB) && 1394 "Shouldn't consider two physregs!"); 1395 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 1396 } 1397 1398 // Compare against the regclass for the second reg. 1399 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 1400 if (MRegisterInfo::isVirtualRegister(RegB)) 1401 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 1402 else 1403 return !RegClass->contains(RegB); 1404} 1405 1406LiveInterval LiveIntervals::createInterval(unsigned reg) { 1407 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 1408 HUGE_VALF : 0.0F; 1409 return LiveInterval(reg, Weight); 1410} 1411