LiveIntervalAnalysis.cpp revision ba59a1e453e110f7b84233f07613f9c5d9a39b87
1//===-- LiveIntervalAnalysis.cpp - Live Interval Analysis -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveInterval analysis pass which is used 11// by the Linear Scan Register allocator. This pass linearizes the 12// basic blocks of the function in DFS order and uses the 13// LiveVariables pass to conservatively compute live intervals for 14// each virtual and physical register. 15// 16//===----------------------------------------------------------------------===// 17 18#define DEBUG_TYPE "liveintervals" 19#include "llvm/CodeGen/LiveIntervalAnalysis.h" 20#include "VirtRegMap.h" 21#include "llvm/Value.h" 22#include "llvm/Analysis/LoopInfo.h" 23#include "llvm/CodeGen/LiveVariables.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstr.h" 26#include "llvm/CodeGen/Passes.h" 27#include "llvm/CodeGen/SSARegMap.h" 28#include "llvm/Target/MRegisterInfo.h" 29#include "llvm/Target/TargetInstrInfo.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/ADT/STLExtras.h" 35#include <algorithm> 36using namespace llvm; 37 38namespace { 39 RegisterPass<LiveIntervals> X("liveintervals", "Live Interval Analysis"); 40 41 static Statistic<> numIntervals 42 ("liveintervals", "Number of original intervals"); 43 44 static Statistic<> numIntervalsAfter 45 ("liveintervals", "Number of intervals after coalescing"); 46 47 static Statistic<> numJoins 48 ("liveintervals", "Number of interval joins performed"); 49 50 static Statistic<> numPeep 51 ("liveintervals", "Number of identity moves eliminated after coalescing"); 52 53 static Statistic<> numFolded 54 ("liveintervals", "Number of loads/stores folded into instructions"); 55 56 static cl::opt<bool> 57 EnableJoining("join-liveintervals", 58 cl::desc("Coallesce copies (default=true)"), 59 cl::init(true)); 60} 61 62void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const { 63 AU.addRequired<LiveVariables>(); 64 AU.addPreservedID(PHIEliminationID); 65 AU.addRequiredID(PHIEliminationID); 66 AU.addRequiredID(TwoAddressInstructionPassID); 67 AU.addRequired<LoopInfo>(); 68 MachineFunctionPass::getAnalysisUsage(AU); 69} 70 71void LiveIntervals::releaseMemory() { 72 mi2iMap_.clear(); 73 i2miMap_.clear(); 74 r2iMap_.clear(); 75 r2rMap_.clear(); 76} 77 78 79static bool isZeroLengthInterval(LiveInterval *li) { 80 for (LiveInterval::Ranges::const_iterator 81 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i) 82 if (i->end - i->start > LiveIntervals::InstrSlots::NUM) 83 return false; 84 return true; 85} 86 87 88/// runOnMachineFunction - Register allocate the whole function 89/// 90bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { 91 mf_ = &fn; 92 tm_ = &fn.getTarget(); 93 mri_ = tm_->getRegisterInfo(); 94 tii_ = tm_->getInstrInfo(); 95 lv_ = &getAnalysis<LiveVariables>(); 96 allocatableRegs_ = mri_->getAllocatableSet(fn); 97 r2rMap_.grow(mf_->getSSARegMap()->getLastVirtReg()); 98 99 // If this function has any live ins, insert a dummy instruction at the 100 // beginning of the function that we will pretend "defines" the values. This 101 // is to make the interval analysis simpler by providing a number. 102 if (fn.livein_begin() != fn.livein_end()) { 103 unsigned FirstLiveIn = fn.livein_begin()->first; 104 105 // Find a reg class that contains this live in. 106 const TargetRegisterClass *RC = 0; 107 for (MRegisterInfo::regclass_iterator RCI = mri_->regclass_begin(), 108 E = mri_->regclass_end(); RCI != E; ++RCI) 109 if ((*RCI)->contains(FirstLiveIn)) { 110 RC = *RCI; 111 break; 112 } 113 114 MachineInstr *OldFirstMI = fn.begin()->begin(); 115 mri_->copyRegToReg(*fn.begin(), fn.begin()->begin(), 116 FirstLiveIn, FirstLiveIn, RC); 117 assert(OldFirstMI != fn.begin()->begin() && 118 "copyRetToReg didn't insert anything!"); 119 } 120 121 // Number MachineInstrs and MachineBasicBlocks. 122 // Initialize MBB indexes to a sentinal. 123 MBB2IdxMap.resize(mf_->getNumBlockIDs(), ~0U); 124 125 unsigned MIIndex = 0; 126 for (MachineFunction::iterator MBB = mf_->begin(), E = mf_->end(); 127 MBB != E; ++MBB) { 128 // Set the MBB2IdxMap entry for this MBB. 129 MBB2IdxMap[MBB->getNumber()] = MIIndex; 130 131 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 132 I != E; ++I) { 133 bool inserted = mi2iMap_.insert(std::make_pair(I, MIIndex)).second; 134 assert(inserted && "multiple MachineInstr -> index mappings"); 135 i2miMap_.push_back(I); 136 MIIndex += InstrSlots::NUM; 137 } 138 } 139 140 // Note intervals due to live-in values. 141 if (fn.livein_begin() != fn.livein_end()) { 142 MachineBasicBlock *Entry = fn.begin(); 143 for (MachineFunction::livein_iterator I = fn.livein_begin(), 144 E = fn.livein_end(); I != E; ++I) { 145 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 146 getOrCreateInterval(I->first), 0); 147 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS) 148 handlePhysicalRegisterDef(Entry, Entry->begin(), 0, 149 getOrCreateInterval(*AS), 0); 150 } 151 } 152 153 computeIntervals(); 154 155 numIntervals += getNumIntervals(); 156 157 DOUT << "********** INTERVALS **********\n"; 158 for (iterator I = begin(), E = end(); I != E; ++I) { 159 I->second.print(DOUT, mri_); 160 DOUT << "\n"; 161 } 162 163 // Join (coallesce) intervals if requested. 164 if (EnableJoining) joinIntervals(); 165 166 numIntervalsAfter += getNumIntervals(); 167 168 169 // perform a final pass over the instructions and compute spill 170 // weights, coalesce virtual registers and remove identity moves. 171 const LoopInfo &loopInfo = getAnalysis<LoopInfo>(); 172 173 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 174 mbbi != mbbe; ++mbbi) { 175 MachineBasicBlock* mbb = mbbi; 176 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock()); 177 178 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); 179 mii != mie; ) { 180 // if the move will be an identity move delete it 181 unsigned srcReg, dstReg, RegRep; 182 if (tii_->isMoveInstr(*mii, srcReg, dstReg) && 183 (RegRep = rep(srcReg)) == rep(dstReg)) { 184 // remove from def list 185 getOrCreateInterval(RegRep); 186 RemoveMachineInstrFromMaps(mii); 187 mii = mbbi->erase(mii); 188 ++numPeep; 189 } 190 else { 191 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { 192 const MachineOperand &mop = mii->getOperand(i); 193 if (mop.isRegister() && mop.getReg() && 194 MRegisterInfo::isVirtualRegister(mop.getReg())) { 195 // replace register with representative register 196 unsigned reg = rep(mop.getReg()); 197 mii->getOperand(i).setReg(reg); 198 199 LiveInterval &RegInt = getInterval(reg); 200 RegInt.weight += 201 (mop.isUse() + mop.isDef()) * pow(10.0F, (int)loopDepth); 202 } 203 } 204 ++mii; 205 } 206 } 207 } 208 209 210 for (iterator I = begin(), E = end(); I != E; ++I) { 211 LiveInterval &LI = I->second; 212 if (MRegisterInfo::isVirtualRegister(LI.reg)) { 213 // If the live interval length is essentially zero, i.e. in every live 214 // range the use follows def immediately, it doesn't make sense to spill 215 // it and hope it will be easier to allocate for this li. 216 if (isZeroLengthInterval(&LI)) 217 LI.weight = HUGE_VALF; 218 219 // Divide the weight of the interval by its size. This encourages 220 // spilling of intervals that are large and have few uses, and 221 // discourages spilling of small intervals with many uses. 222 unsigned Size = 0; 223 for (LiveInterval::iterator II = LI.begin(), E = LI.end(); II != E;++II) 224 Size += II->end - II->start; 225 226 LI.weight /= Size; 227 } 228 } 229 230 DEBUG(dump()); 231 return true; 232} 233 234/// print - Implement the dump method. 235void LiveIntervals::print(std::ostream &O, const Module* ) const { 236 O << "********** INTERVALS **********\n"; 237 for (const_iterator I = begin(), E = end(); I != E; ++I) { 238 I->second.print(DOUT, mri_); 239 DOUT << "\n"; 240 } 241 242 O << "********** MACHINEINSTRS **********\n"; 243 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); 244 mbbi != mbbe; ++mbbi) { 245 O << ((Value*)mbbi->getBasicBlock())->getName() << ":\n"; 246 for (MachineBasicBlock::iterator mii = mbbi->begin(), 247 mie = mbbi->end(); mii != mie; ++mii) { 248 O << getInstructionIndex(mii) << '\t' << *mii; 249 } 250 } 251} 252 253/// CreateNewLiveInterval - Create a new live interval with the given live 254/// ranges. The new live interval will have an infinite spill weight. 255LiveInterval& 256LiveIntervals::CreateNewLiveInterval(const LiveInterval *LI, 257 const std::vector<LiveRange> &LRs) { 258 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(LI->reg); 259 260 // Create a new virtual register for the spill interval. 261 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(RC); 262 263 // Replace the old virtual registers in the machine operands with the shiny 264 // new one. 265 for (std::vector<LiveRange>::const_iterator 266 I = LRs.begin(), E = LRs.end(); I != E; ++I) { 267 unsigned Index = getBaseIndex(I->start); 268 unsigned End = getBaseIndex(I->end - 1) + InstrSlots::NUM; 269 270 for (; Index != End; Index += InstrSlots::NUM) { 271 // Skip deleted instructions 272 while (Index != End && !getInstructionFromIndex(Index)) 273 Index += InstrSlots::NUM; 274 275 if (Index == End) break; 276 277 MachineInstr *MI = getInstructionFromIndex(Index); 278 279 for (unsigned J = 0, e = MI->getNumOperands(); J != e; ++J) { 280 MachineOperand &MOp = MI->getOperand(J); 281 if (MOp.isRegister() && rep(MOp.getReg()) == LI->reg) 282 MOp.setReg(NewVReg); 283 } 284 } 285 } 286 287 LiveInterval &NewLI = getOrCreateInterval(NewVReg); 288 289 // The spill weight is now infinity as it cannot be spilled again 290 NewLI.weight = float(HUGE_VAL); 291 292 for (std::vector<LiveRange>::const_iterator 293 I = LRs.begin(), E = LRs.end(); I != E; ++I) { 294 DOUT << " Adding live range " << *I << " to new interval\n"; 295 NewLI.addRange(*I); 296 } 297 298 DOUT << "Created new live interval " << NewLI << "\n"; 299 return NewLI; 300} 301 302std::vector<LiveInterval*> LiveIntervals:: 303addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) { 304 // since this is called after the analysis is done we don't know if 305 // LiveVariables is available 306 lv_ = getAnalysisToUpdate<LiveVariables>(); 307 308 std::vector<LiveInterval*> added; 309 310 assert(li.weight != HUGE_VALF && 311 "attempt to spill already spilled interval!"); 312 313 DOUT << "\t\t\t\tadding intervals for spills for interval: "; 314 li.print(DOUT, mri_); 315 DOUT << '\n'; 316 317 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg); 318 319 for (LiveInterval::Ranges::const_iterator 320 i = li.ranges.begin(), e = li.ranges.end(); i != e; ++i) { 321 unsigned index = getBaseIndex(i->start); 322 unsigned end = getBaseIndex(i->end-1) + InstrSlots::NUM; 323 for (; index != end; index += InstrSlots::NUM) { 324 // skip deleted instructions 325 while (index != end && !getInstructionFromIndex(index)) 326 index += InstrSlots::NUM; 327 if (index == end) break; 328 329 MachineInstr *MI = getInstructionFromIndex(index); 330 331 RestartInstruction: 332 for (unsigned i = 0; i != MI->getNumOperands(); ++i) { 333 MachineOperand& mop = MI->getOperand(i); 334 if (mop.isRegister() && mop.getReg() == li.reg) { 335 if (MachineInstr *fmi = mri_->foldMemoryOperand(MI, i, slot)) { 336 // Attempt to fold the memory reference into the instruction. If we 337 // can do this, we don't need to insert spill code. 338 if (lv_) 339 lv_->instructionChanged(MI, fmi); 340 MachineBasicBlock &MBB = *MI->getParent(); 341 vrm.virtFolded(li.reg, MI, i, fmi); 342 mi2iMap_.erase(MI); 343 i2miMap_[index/InstrSlots::NUM] = fmi; 344 mi2iMap_[fmi] = index; 345 MI = MBB.insert(MBB.erase(MI), fmi); 346 ++numFolded; 347 // Folding the load/store can completely change the instruction in 348 // unpredictable ways, rescan it from the beginning. 349 goto RestartInstruction; 350 } else { 351 // Create a new virtual register for the spill interval. 352 unsigned NewVReg = mf_->getSSARegMap()->createVirtualRegister(rc); 353 354 // Scan all of the operands of this instruction rewriting operands 355 // to use NewVReg instead of li.reg as appropriate. We do this for 356 // two reasons: 357 // 358 // 1. If the instr reads the same spilled vreg multiple times, we 359 // want to reuse the NewVReg. 360 // 2. If the instr is a two-addr instruction, we are required to 361 // keep the src/dst regs pinned. 362 // 363 // Keep track of whether we replace a use and/or def so that we can 364 // create the spill interval with the appropriate range. 365 mop.setReg(NewVReg); 366 367 bool HasUse = mop.isUse(); 368 bool HasDef = mop.isDef(); 369 for (unsigned j = i+1, e = MI->getNumOperands(); j != e; ++j) { 370 if (MI->getOperand(j).isReg() && 371 MI->getOperand(j).getReg() == li.reg) { 372 MI->getOperand(j).setReg(NewVReg); 373 HasUse |= MI->getOperand(j).isUse(); 374 HasDef |= MI->getOperand(j).isDef(); 375 } 376 } 377 378 // create a new register for this spill 379 vrm.grow(); 380 vrm.assignVirt2StackSlot(NewVReg, slot); 381 LiveInterval &nI = getOrCreateInterval(NewVReg); 382 assert(nI.empty()); 383 384 // the spill weight is now infinity as it 385 // cannot be spilled again 386 nI.weight = HUGE_VALF; 387 388 if (HasUse) { 389 LiveRange LR(getLoadIndex(index), getUseIndex(index), 390 nI.getNextValue(~0U, 0)); 391 DOUT << " +" << LR; 392 nI.addRange(LR); 393 } 394 if (HasDef) { 395 LiveRange LR(getDefIndex(index), getStoreIndex(index), 396 nI.getNextValue(~0U, 0)); 397 DOUT << " +" << LR; 398 nI.addRange(LR); 399 } 400 401 added.push_back(&nI); 402 403 // update live variables if it is available 404 if (lv_) 405 lv_->addVirtualRegisterKilled(NewVReg, MI); 406 407 DOUT << "\t\t\t\tadded new interval: "; 408 nI.print(DOUT, mri_); 409 DOUT << '\n'; 410 } 411 } 412 } 413 } 414 } 415 416 return added; 417} 418 419void LiveIntervals::printRegName(unsigned reg) const { 420 if (MRegisterInfo::isPhysicalRegister(reg)) 421 llvm_cerr << mri_->getName(reg); 422 else 423 llvm_cerr << "%reg" << reg; 424} 425 426/// isReDefinedByTwoAddr - Returns true if the Reg re-definition is due to 427/// two addr elimination. 428static bool isReDefinedByTwoAddr(MachineInstr *MI, unsigned Reg, 429 const TargetInstrInfo *TII) { 430 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 431 MachineOperand &MO1 = MI->getOperand(i); 432 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { 433 for (unsigned j = i+1; j < e; ++j) { 434 MachineOperand &MO2 = MI->getOperand(j); 435 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && 436 TII->getOperandConstraint(MI->getOpcode(),j,TOI::TIED_TO) == (int)i) 437 return true; 438 } 439 } 440 } 441 return false; 442} 443 444void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, 445 MachineBasicBlock::iterator mi, 446 unsigned MIIdx, 447 LiveInterval &interval) { 448 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); 449 LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg); 450 451 // Virtual registers may be defined multiple times (due to phi 452 // elimination and 2-addr elimination). Much of what we do only has to be 453 // done once for the vreg. We use an empty interval to detect the first 454 // time we see a vreg. 455 if (interval.empty()) { 456 // Get the Idx of the defining instructions. 457 unsigned defIndex = getDefIndex(MIIdx); 458 459 unsigned ValNum; 460 unsigned SrcReg, DstReg; 461 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 462 ValNum = interval.getNextValue(~0U, 0); 463 else 464 ValNum = interval.getNextValue(defIndex, SrcReg); 465 466 assert(ValNum == 0 && "First value in interval is not 0?"); 467 ValNum = 0; // Clue in the optimizer. 468 469 // Loop over all of the blocks that the vreg is defined in. There are 470 // two cases we have to handle here. The most common case is a vreg 471 // whose lifetime is contained within a basic block. In this case there 472 // will be a single kill, in MBB, which comes after the definition. 473 if (vi.Kills.size() == 1 && vi.Kills[0]->getParent() == mbb) { 474 // FIXME: what about dead vars? 475 unsigned killIdx; 476 if (vi.Kills[0] != mi) 477 killIdx = getUseIndex(getInstructionIndex(vi.Kills[0]))+1; 478 else 479 killIdx = defIndex+1; 480 481 // If the kill happens after the definition, we have an intra-block 482 // live range. 483 if (killIdx > defIndex) { 484 assert(vi.AliveBlocks.empty() && 485 "Shouldn't be alive across any blocks!"); 486 LiveRange LR(defIndex, killIdx, ValNum); 487 interval.addRange(LR); 488 DOUT << " +" << LR << "\n"; 489 return; 490 } 491 } 492 493 // The other case we handle is when a virtual register lives to the end 494 // of the defining block, potentially live across some blocks, then is 495 // live into some number of blocks, but gets killed. Start by adding a 496 // range that goes from this definition to the end of the defining block. 497 LiveRange NewLR(defIndex, 498 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, 499 ValNum); 500 DOUT << " +" << NewLR; 501 interval.addRange(NewLR); 502 503 // Iterate over all of the blocks that the variable is completely 504 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the 505 // live interval. 506 for (unsigned i = 0, e = vi.AliveBlocks.size(); i != e; ++i) { 507 if (vi.AliveBlocks[i]) { 508 MachineBasicBlock *MBB = mf_->getBlockNumbered(i); 509 if (!MBB->empty()) { 510 LiveRange LR(getMBBStartIdx(i), 511 getInstructionIndex(&MBB->back()) + InstrSlots::NUM, 512 ValNum); 513 interval.addRange(LR); 514 DOUT << " +" << LR; 515 } 516 } 517 } 518 519 // Finally, this virtual register is live from the start of any killing 520 // block to the 'use' slot of the killing instruction. 521 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) { 522 MachineInstr *Kill = vi.Kills[i]; 523 LiveRange LR(getMBBStartIdx(Kill->getParent()), 524 getUseIndex(getInstructionIndex(Kill))+1, 525 ValNum); 526 interval.addRange(LR); 527 DOUT << " +" << LR; 528 } 529 530 } else { 531 // If this is the second time we see a virtual register definition, it 532 // must be due to phi elimination or two addr elimination. If this is 533 // the result of two address elimination, then the vreg is one of the 534 // def-and-use register operand. 535 if (isReDefinedByTwoAddr(mi, interval.reg, tii_)) { 536 // If this is a two-address definition, then we have already processed 537 // the live range. The only problem is that we didn't realize there 538 // are actually two values in the live interval. Because of this we 539 // need to take the LiveRegion that defines this register and split it 540 // into two values. 541 unsigned DefIndex = getDefIndex(getInstructionIndex(vi.DefInst)); 542 unsigned RedefIndex = getDefIndex(MIIdx); 543 544 // Delete the initial value, which should be short and continuous, 545 // because the 2-addr copy must be in the same MBB as the redef. 546 interval.removeRange(DefIndex, RedefIndex); 547 548 // Two-address vregs should always only be redefined once. This means 549 // that at this point, there should be exactly one value number in it. 550 assert(interval.containsOneValue() && "Unexpected 2-addr liveint!"); 551 552 // The new value number (#1) is defined by the instruction we claimed 553 // defined value #0. 554 unsigned ValNo = interval.getNextValue(0, 0); 555 interval.setValueNumberInfo(1, interval.getValNumInfo(0)); 556 557 // Value#0 is now defined by the 2-addr instruction. 558 interval.setValueNumberInfo(0, std::make_pair(~0U, 0U)); 559 560 // Add the new live interval which replaces the range for the input copy. 561 LiveRange LR(DefIndex, RedefIndex, ValNo); 562 DOUT << " replace range with " << LR; 563 interval.addRange(LR); 564 565 // If this redefinition is dead, we need to add a dummy unit live 566 // range covering the def slot. 567 if (lv_->RegisterDefIsDead(mi, interval.reg)) 568 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0)); 569 570 DOUT << "RESULT: "; 571 interval.print(DOUT, mri_); 572 573 } else { 574 // Otherwise, this must be because of phi elimination. If this is the 575 // first redefinition of the vreg that we have seen, go back and change 576 // the live range in the PHI block to be a different value number. 577 if (interval.containsOneValue()) { 578 assert(vi.Kills.size() == 1 && 579 "PHI elimination vreg should have one kill, the PHI itself!"); 580 581 // Remove the old range that we now know has an incorrect number. 582 MachineInstr *Killer = vi.Kills[0]; 583 unsigned Start = getMBBStartIdx(Killer->getParent()); 584 unsigned End = getUseIndex(getInstructionIndex(Killer))+1; 585 DOUT << "Removing [" << Start << "," << End << "] from: "; 586 interval.print(DOUT, mri_); DOUT << "\n"; 587 interval.removeRange(Start, End); 588 DOUT << "RESULT: "; interval.print(DOUT, mri_); 589 590 // Replace the interval with one of a NEW value number. Note that this 591 // value number isn't actually defined by an instruction, weird huh? :) 592 LiveRange LR(Start, End, interval.getNextValue(~0U, 0)); 593 DOUT << " replace range with " << LR; 594 interval.addRange(LR); 595 DOUT << "RESULT: "; interval.print(DOUT, mri_); 596 } 597 598 // In the case of PHI elimination, each variable definition is only 599 // live until the end of the block. We've already taken care of the 600 // rest of the live range. 601 unsigned defIndex = getDefIndex(MIIdx); 602 603 unsigned ValNum; 604 unsigned SrcReg, DstReg; 605 if (!tii_->isMoveInstr(*mi, SrcReg, DstReg)) 606 ValNum = interval.getNextValue(~0U, 0); 607 else 608 ValNum = interval.getNextValue(defIndex, SrcReg); 609 610 LiveRange LR(defIndex, 611 getInstructionIndex(&mbb->back()) + InstrSlots::NUM, ValNum); 612 interval.addRange(LR); 613 DOUT << " +" << LR; 614 } 615 } 616 617 DOUT << '\n'; 618} 619 620void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB, 621 MachineBasicBlock::iterator mi, 622 unsigned MIIdx, 623 LiveInterval &interval, 624 unsigned SrcReg) { 625 // A physical register cannot be live across basic block, so its 626 // lifetime must end somewhere in its defining basic block. 627 DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg)); 628 629 unsigned baseIndex = MIIdx; 630 unsigned start = getDefIndex(baseIndex); 631 unsigned end = start; 632 633 // If it is not used after definition, it is considered dead at 634 // the instruction defining it. Hence its interval is: 635 // [defSlot(def), defSlot(def)+1) 636 if (lv_->RegisterDefIsDead(mi, interval.reg)) { 637 DOUT << " dead"; 638 end = getDefIndex(start) + 1; 639 goto exit; 640 } 641 642 // If it is not dead on definition, it must be killed by a 643 // subsequent instruction. Hence its interval is: 644 // [defSlot(def), useSlot(kill)+1) 645 while (++mi != MBB->end()) { 646 baseIndex += InstrSlots::NUM; 647 if (lv_->KillsRegister(mi, interval.reg)) { 648 DOUT << " killed"; 649 end = getUseIndex(baseIndex) + 1; 650 goto exit; 651 } else if (lv_->ModifiesRegister(mi, interval.reg)) { 652 // Another instruction redefines the register before it is ever read. 653 // Then the register is essentially dead at the instruction that defines 654 // it. Hence its interval is: 655 // [defSlot(def), defSlot(def)+1) 656 DOUT << " dead"; 657 end = getDefIndex(start) + 1; 658 goto exit; 659 } 660 } 661 662 // The only case we should have a dead physreg here without a killing or 663 // instruction where we know it's dead is if it is live-in to the function 664 // and never used. 665 assert(!SrcReg && "physreg was not killed in defining block!"); 666 end = getDefIndex(start) + 1; // It's dead. 667 668exit: 669 assert(start < end && "did not find end of interval?"); 670 671 LiveRange LR(start, end, interval.getNextValue(SrcReg != 0 ? start : ~0U, 672 SrcReg)); 673 interval.addRange(LR); 674 DOUT << " +" << LR << '\n'; 675} 676 677void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, 678 MachineBasicBlock::iterator MI, 679 unsigned MIIdx, 680 unsigned reg) { 681 if (MRegisterInfo::isVirtualRegister(reg)) 682 handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); 683 else if (allocatableRegs_[reg]) { 684 unsigned SrcReg, DstReg; 685 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) 686 SrcReg = 0; 687 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); 688 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS) 689 handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); 690 } 691} 692 693/// computeIntervals - computes the live intervals for virtual 694/// registers. for some ordering of the machine instructions [1,N] a 695/// live interval is an interval [i, j) where 1 <= i <= j < N for 696/// which a variable is live 697void LiveIntervals::computeIntervals() { 698 DOUT << "********** COMPUTING LIVE INTERVALS **********\n" 699 << "********** Function: " 700 << ((Value*)mf_->getFunction())->getName() << '\n'; 701 bool IgnoreFirstInstr = mf_->livein_begin() != mf_->livein_end(); 702 703 // Track the index of the current machine instr. 704 unsigned MIIndex = 0; 705 for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end(); 706 MBBI != E; ++MBBI) { 707 MachineBasicBlock *MBB = MBBI; 708 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; 709 710 MachineBasicBlock::iterator MI = MBB->begin(), miEnd = MBB->end(); 711 if (IgnoreFirstInstr) { 712 ++MI; 713 IgnoreFirstInstr = false; 714 MIIndex += InstrSlots::NUM; 715 } 716 717 for (; MI != miEnd; ++MI) { 718 DOUT << MIIndex << "\t" << *MI; 719 720 // Handle defs. 721 for (int i = MI->getNumOperands() - 1; i >= 0; --i) { 722 MachineOperand &MO = MI->getOperand(i); 723 // handle register defs - build intervals 724 if (MO.isRegister() && MO.getReg() && MO.isDef()) 725 handleRegisterDef(MBB, MI, MIIndex, MO.getReg()); 726 } 727 728 MIIndex += InstrSlots::NUM; 729 } 730 } 731} 732 733/// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA 734/// being the source and IntB being the dest, thus this defines a value number 735/// in IntB. If the source value number (in IntA) is defined by a copy from B, 736/// see if we can merge these two pieces of B into a single value number, 737/// eliminating a copy. For example: 738/// 739/// A3 = B0 740/// ... 741/// B1 = A3 <- this copy 742/// 743/// In this case, B0 can be extended to where the B1 copy lives, allowing the B1 744/// value number to be replaced with B0 (which simplifies the B liveinterval). 745/// 746/// This returns true if an interval was modified. 747/// 748bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB, 749 MachineInstr *CopyMI) { 750 unsigned CopyIdx = getDefIndex(getInstructionIndex(CopyMI)); 751 752 // BValNo is a value number in B that is defined by a copy from A. 'B3' in 753 // the example above. 754 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); 755 unsigned BValNo = BLR->ValId; 756 757 // Get the location that B is defined at. Two options: either this value has 758 // an unknown definition point or it is defined at CopyIdx. If unknown, we 759 // can't process it. 760 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo); 761 if (BValNoDefIdx == ~0U) return false; 762 assert(BValNoDefIdx == CopyIdx && 763 "Copy doesn't define the value?"); 764 765 // AValNo is the value number in A that defines the copy, A0 in the example. 766 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1); 767 unsigned AValNo = AValLR->ValId; 768 769 // If AValNo is defined as a copy from IntB, we can potentially process this. 770 771 // Get the instruction that defines this value number. 772 unsigned SrcReg = IntA.getSrcRegForValNum(AValNo); 773 if (!SrcReg) return false; // Not defined by a copy. 774 775 // If the value number is not defined by a copy instruction, ignore it. 776 777 // If the source register comes from an interval other than IntB, we can't 778 // handle this. 779 if (rep(SrcReg) != IntB.reg) return false; 780 781 // Get the LiveRange in IntB that this value number starts with. 782 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo); 783 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1); 784 785 // Make sure that the end of the live range is inside the same block as 786 // CopyMI. 787 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1); 788 if (!ValLREndInst || 789 ValLREndInst->getParent() != CopyMI->getParent()) return false; 790 791 // Okay, we now know that ValLR ends in the same block that the CopyMI 792 // live-range starts. If there are no intervening live ranges between them in 793 // IntB, we can merge them. 794 if (ValLR+1 != BLR) return false; 795 796 DOUT << "\nExtending: "; IntB.print(DOUT, mri_); 797 798 // We are about to delete CopyMI, so need to remove it as the 'instruction 799 // that defines this value #'. 800 IntB.setValueNumberInfo(BValNo, std::make_pair(~0U, 0)); 801 802 // Okay, we can merge them. We need to insert a new liverange: 803 // [ValLR.end, BLR.begin) of either value number, then we merge the 804 // two value numbers. 805 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; 806 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo)); 807 808 // If the IntB live range is assigned to a physical register, and if that 809 // physreg has aliases, 810 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { 811 for (const unsigned *AS = mri_->getAliasSet(IntB.reg); *AS; ++AS) { 812 LiveInterval &AliasLI = getInterval(*AS); 813 AliasLI.addRange(LiveRange(FillerStart, FillerEnd, 814 AliasLI.getNextValue(~0U, 0))); 815 } 816 } 817 818 // Okay, merge "B1" into the same value number as "B0". 819 if (BValNo != ValLR->ValId) 820 IntB.MergeValueNumberInto(BValNo, ValLR->ValId); 821 DOUT << " result = "; IntB.print(DOUT, mri_); 822 DOUT << "\n"; 823 824 // Finally, delete the copy instruction. 825 RemoveMachineInstrFromMaps(CopyMI); 826 CopyMI->eraseFromParent(); 827 ++numPeep; 828 return true; 829} 830 831 832/// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 833/// which are the src/dst of the copy instruction CopyMI. This returns true 834/// if the copy was successfully coallesced away, or if it is never possible 835/// to coallesce these this copy, due to register constraints. It returns 836/// false if it is not currently possible to coallesce this interval, but 837/// it may be possible if other things get coallesced. 838bool LiveIntervals::JoinCopy(MachineInstr *CopyMI, 839 unsigned SrcReg, unsigned DstReg) { 840 DOUT << getInstructionIndex(CopyMI) << '\t' << *CopyMI; 841 842 // Get representative registers. 843 SrcReg = rep(SrcReg); 844 DstReg = rep(DstReg); 845 846 // If they are already joined we continue. 847 if (SrcReg == DstReg) { 848 DOUT << "\tCopy already coallesced.\n"; 849 return true; // Not coallescable. 850 } 851 852 // If they are both physical registers, we cannot join them. 853 if (MRegisterInfo::isPhysicalRegister(SrcReg) && 854 MRegisterInfo::isPhysicalRegister(DstReg)) { 855 DOUT << "\tCan not coallesce physregs.\n"; 856 return true; // Not coallescable. 857 } 858 859 // We only join virtual registers with allocatable physical registers. 860 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){ 861 DOUT << "\tSrc reg is unallocatable physreg.\n"; 862 return true; // Not coallescable. 863 } 864 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){ 865 DOUT << "\tDst reg is unallocatable physreg.\n"; 866 return true; // Not coallescable. 867 } 868 869 // If they are not of the same register class, we cannot join them. 870 if (differingRegisterClasses(SrcReg, DstReg)) { 871 DOUT << "\tSrc/Dest are different register classes.\n"; 872 return true; // Not coallescable. 873 } 874 875 LiveInterval &SrcInt = getInterval(SrcReg); 876 LiveInterval &DestInt = getInterval(DstReg); 877 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg && 878 "Register mapping is horribly broken!"); 879 880 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_); 881 DOUT << " and "; DestInt.print(DOUT, mri_); 882 DOUT << ": "; 883 884 // Okay, attempt to join these two intervals. On failure, this returns false. 885 // Otherwise, if one of the intervals being joined is a physreg, this method 886 // always canonicalizes DestInt to be it. The output "SrcInt" will not have 887 // been modified, so we can use this information below to update aliases. 888 if (!JoinIntervals(DestInt, SrcInt)) { 889 // Coallescing failed. 890 891 // If we can eliminate the copy without merging the live ranges, do so now. 892 if (AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI)) 893 return true; 894 895 // Otherwise, we are unable to join the intervals. 896 DOUT << "Interference!\n"; 897 return false; 898 } 899 900 bool Swapped = SrcReg == DestInt.reg; 901 if (Swapped) 902 std::swap(SrcReg, DstReg); 903 assert(MRegisterInfo::isVirtualRegister(SrcReg) && 904 "LiveInterval::join didn't work right!"); 905 906 // If we're about to merge live ranges into a physical register live range, 907 // we have to update any aliased register's live ranges to indicate that they 908 // have clobbered values for this range. 909 if (MRegisterInfo::isPhysicalRegister(DstReg)) { 910 for (const unsigned *AS = mri_->getAliasSet(DstReg); *AS; ++AS) 911 getInterval(*AS).MergeInClobberRanges(SrcInt); 912 } 913 914 DOUT << "\n\t\tJoined. Result = "; DestInt.print(DOUT, mri_); 915 DOUT << "\n"; 916 917 // If the intervals were swapped by Join, swap them back so that the register 918 // mapping (in the r2i map) is correct. 919 if (Swapped) SrcInt.swap(DestInt); 920 r2iMap_.erase(SrcReg); 921 r2rMap_[SrcReg] = DstReg; 922 923 // Finally, delete the copy instruction. 924 RemoveMachineInstrFromMaps(CopyMI); 925 CopyMI->eraseFromParent(); 926 ++numPeep; 927 ++numJoins; 928 return true; 929} 930 931/// ComputeUltimateVN - Assuming we are going to join two live intervals, 932/// compute what the resultant value numbers for each value in the input two 933/// ranges will be. This is complicated by copies between the two which can 934/// and will commonly cause multiple value numbers to be merged into one. 935/// 936/// VN is the value number that we're trying to resolve. InstDefiningValue 937/// keeps track of the new InstDefiningValue assignment for the result 938/// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of 939/// whether a value in this or other is a copy from the opposite set. 940/// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have 941/// already been assigned. 942/// 943/// ThisFromOther[x] - If x is defined as a copy from the other interval, this 944/// contains the value number the copy is from. 945/// 946static unsigned ComputeUltimateVN(unsigned VN, 947 SmallVector<std::pair<unsigned, 948 unsigned>, 16> &ValueNumberInfo, 949 SmallVector<int, 16> &ThisFromOther, 950 SmallVector<int, 16> &OtherFromThis, 951 SmallVector<int, 16> &ThisValNoAssignments, 952 SmallVector<int, 16> &OtherValNoAssignments, 953 LiveInterval &ThisLI, LiveInterval &OtherLI) { 954 // If the VN has already been computed, just return it. 955 if (ThisValNoAssignments[VN] >= 0) 956 return ThisValNoAssignments[VN]; 957// assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?"); 958 959 // If this val is not a copy from the other val, then it must be a new value 960 // number in the destination. 961 int OtherValNo = ThisFromOther[VN]; 962 if (OtherValNo == -1) { 963 ValueNumberInfo.push_back(ThisLI.getValNumInfo(VN)); 964 return ThisValNoAssignments[VN] = ValueNumberInfo.size()-1; 965 } 966 967 // Otherwise, this *is* a copy from the RHS. If the other side has already 968 // been computed, return it. 969 if (OtherValNoAssignments[OtherValNo] >= 0) 970 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo]; 971 972 // Mark this value number as currently being computed, then ask what the 973 // ultimate value # of the other value is. 974 ThisValNoAssignments[VN] = -2; 975 unsigned UltimateVN = 976 ComputeUltimateVN(OtherValNo, ValueNumberInfo, 977 OtherFromThis, ThisFromOther, 978 OtherValNoAssignments, ThisValNoAssignments, 979 OtherLI, ThisLI); 980 return ThisValNoAssignments[VN] = UltimateVN; 981} 982 983static bool InVector(unsigned Val, const SmallVector<unsigned, 8> &V) { 984 return std::find(V.begin(), V.end(), Val) != V.end(); 985} 986 987/// SimpleJoin - Attempt to joint the specified interval into this one. The 988/// caller of this method must guarantee that the RHS only contains a single 989/// value number and that the RHS is not defined by a copy from this 990/// interval. This returns false if the intervals are not joinable, or it 991/// joins them and returns true. 992bool LiveIntervals::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) { 993 assert(RHS.containsOneValue()); 994 995 // Some number (potentially more than one) value numbers in the current 996 // interval may be defined as copies from the RHS. Scan the overlapping 997 // portions of the LHS and RHS, keeping track of this and looking for 998 // overlapping live ranges that are NOT defined as copies. If these exist, we 999 // cannot coallesce. 1000 1001 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); 1002 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); 1003 1004 if (LHSIt->start < RHSIt->start) { 1005 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); 1006 if (LHSIt != LHS.begin()) --LHSIt; 1007 } else if (RHSIt->start < LHSIt->start) { 1008 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); 1009 if (RHSIt != RHS.begin()) --RHSIt; 1010 } 1011 1012 SmallVector<unsigned, 8> EliminatedLHSVals; 1013 1014 while (1) { 1015 // Determine if these live intervals overlap. 1016 bool Overlaps = false; 1017 if (LHSIt->start <= RHSIt->start) 1018 Overlaps = LHSIt->end > RHSIt->start; 1019 else 1020 Overlaps = RHSIt->end > LHSIt->start; 1021 1022 // If the live intervals overlap, there are two interesting cases: if the 1023 // LHS interval is defined by a copy from the RHS, it's ok and we record 1024 // that the LHS value # is the same as the RHS. If it's not, then we cannot 1025 // coallesce these live ranges and we bail out. 1026 if (Overlaps) { 1027 // If we haven't already recorded that this value # is safe, check it. 1028 if (!InVector(LHSIt->ValId, EliminatedLHSVals)) { 1029 // Copy from the RHS? 1030 unsigned SrcReg = LHS.getSrcRegForValNum(LHSIt->ValId); 1031 if (rep(SrcReg) != RHS.reg) 1032 return false; // Nope, bail out. 1033 1034 EliminatedLHSVals.push_back(LHSIt->ValId); 1035 } 1036 1037 // We know this entire LHS live range is okay, so skip it now. 1038 if (++LHSIt == LHSEnd) break; 1039 continue; 1040 } 1041 1042 if (LHSIt->end < RHSIt->end) { 1043 if (++LHSIt == LHSEnd) break; 1044 } else { 1045 // One interesting case to check here. It's possible that we have 1046 // something like "X3 = Y" which defines a new value number in the LHS, 1047 // and is the last use of this liverange of the RHS. In this case, we 1048 // want to notice this copy (so that it gets coallesced away) even though 1049 // the live ranges don't actually overlap. 1050 if (LHSIt->start == RHSIt->end) { 1051 if (InVector(LHSIt->ValId, EliminatedLHSVals)) { 1052 // We already know that this value number is going to be merged in 1053 // if coallescing succeeds. Just skip the liverange. 1054 if (++LHSIt == LHSEnd) break; 1055 } else { 1056 // Otherwise, if this is a copy from the RHS, mark it as being merged 1057 // in. 1058 if (rep(LHS.getSrcRegForValNum(LHSIt->ValId)) == RHS.reg) { 1059 EliminatedLHSVals.push_back(LHSIt->ValId); 1060 1061 // We know this entire LHS live range is okay, so skip it now. 1062 if (++LHSIt == LHSEnd) break; 1063 } 1064 } 1065 } 1066 1067 if (++RHSIt == RHSEnd) break; 1068 } 1069 } 1070 1071 // If we got here, we know that the coallescing will be successful and that 1072 // the value numbers in EliminatedLHSVals will all be merged together. Since 1073 // the most common case is that EliminatedLHSVals has a single number, we 1074 // optimize for it: if there is more than one value, we merge them all into 1075 // the lowest numbered one, then handle the interval as if we were merging 1076 // with one value number. 1077 unsigned LHSValNo; 1078 if (EliminatedLHSVals.size() > 1) { 1079 // Loop through all the equal value numbers merging them into the smallest 1080 // one. 1081 unsigned Smallest = EliminatedLHSVals[0]; 1082 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { 1083 if (EliminatedLHSVals[i] < Smallest) { 1084 // Merge the current notion of the smallest into the smaller one. 1085 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); 1086 Smallest = EliminatedLHSVals[i]; 1087 } else { 1088 // Merge into the smallest. 1089 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); 1090 } 1091 } 1092 LHSValNo = Smallest; 1093 } else { 1094 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?"); 1095 LHSValNo = EliminatedLHSVals[0]; 1096 } 1097 1098 // Okay, now that there is a single LHS value number that we're merging the 1099 // RHS into, update the value number info for the LHS to indicate that the 1100 // value number is defined where the RHS value number was. 1101 LHS.setValueNumberInfo(LHSValNo, RHS.getValNumInfo(0)); 1102 1103 // Okay, the final step is to loop over the RHS live intervals, adding them to 1104 // the LHS. 1105 LHS.MergeRangesInAsValue(RHS, LHSValNo); 1106 LHS.weight += RHS.weight; 1107 1108 return true; 1109} 1110 1111/// JoinIntervals - Attempt to join these two intervals. On failure, this 1112/// returns false. Otherwise, if one of the intervals being joined is a 1113/// physreg, this method always canonicalizes LHS to be it. The output 1114/// "RHS" will not have been modified, so we can use this information 1115/// below to update aliases. 1116bool LiveIntervals::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS) { 1117 // Compute the final value assignment, assuming that the live ranges can be 1118 // coallesced. 1119 SmallVector<int, 16> LHSValNoAssignments; 1120 SmallVector<int, 16> RHSValNoAssignments; 1121 SmallVector<std::pair<unsigned,unsigned>, 16> ValueNumberInfo; 1122 1123 // Compute ultimate value numbers for the LHS and RHS values. 1124 if (RHS.containsOneValue()) { 1125 // Copies from a liveinterval with a single value are simple to handle and 1126 // very common, handle the special case here. This is important, because 1127 // often RHS is small and LHS is large (e.g. a physreg). 1128 1129 // Find out if the RHS is defined as a copy from some value in the LHS. 1130 int RHSValID = -1; 1131 std::pair<unsigned,unsigned> RHSValNoInfo; 1132 unsigned RHSSrcReg = RHS.getSrcRegForValNum(0); 1133 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) { 1134 // If RHS is not defined as a copy from the LHS, we can use simpler and 1135 // faster checks to see if the live ranges are coallescable. This joiner 1136 // can't swap the LHS/RHS intervals though. 1137 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { 1138 return SimpleJoin(LHS, RHS); 1139 } else { 1140 RHSValNoInfo = RHS.getValNumInfo(0); 1141 } 1142 } else { 1143 // It was defined as a copy from the LHS, find out what value # it is. 1144 unsigned ValInst = RHS.getInstForValNum(0); 1145 RHSValID = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1146 RHSValNoInfo = LHS.getValNumInfo(RHSValID); 1147 } 1148 1149 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1150 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1151 ValueNumberInfo.resize(LHS.getNumValNums()); 1152 1153 // Okay, *all* of the values in LHS that are defined as a copy from RHS 1154 // should now get updated. 1155 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1156 if (unsigned LHSSrcReg = LHS.getSrcRegForValNum(VN)) { 1157 if (rep(LHSSrcReg) != RHS.reg) { 1158 // If this is not a copy from the RHS, its value number will be 1159 // unmodified by the coallescing. 1160 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1161 LHSValNoAssignments[VN] = VN; 1162 } else if (RHSValID == -1) { 1163 // Otherwise, it is a copy from the RHS, and we don't already have a 1164 // value# for it. Keep the current value number, but remember it. 1165 LHSValNoAssignments[VN] = RHSValID = VN; 1166 ValueNumberInfo[VN] = RHSValNoInfo; 1167 } else { 1168 // Otherwise, use the specified value #. 1169 LHSValNoAssignments[VN] = RHSValID; 1170 if (VN != (unsigned)RHSValID) 1171 ValueNumberInfo[VN].first = ~1U; 1172 else 1173 ValueNumberInfo[VN] = RHSValNoInfo; 1174 } 1175 } else { 1176 ValueNumberInfo[VN] = LHS.getValNumInfo(VN); 1177 LHSValNoAssignments[VN] = VN; 1178 } 1179 } 1180 1181 assert(RHSValID != -1 && "Didn't find value #?"); 1182 RHSValNoAssignments[0] = RHSValID; 1183 1184 } else { 1185 // Loop over the value numbers of the LHS, seeing if any are defined from 1186 // the RHS. 1187 SmallVector<int, 16> LHSValsDefinedFromRHS; 1188 LHSValsDefinedFromRHS.resize(LHS.getNumValNums(), -1); 1189 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1190 unsigned ValSrcReg = LHS.getSrcRegForValNum(VN); 1191 if (ValSrcReg == 0) // Src not defined by a copy? 1192 continue; 1193 1194 // DstReg is known to be a register in the LHS interval. If the src is 1195 // from the RHS interval, we can use its value #. 1196 if (rep(ValSrcReg) != RHS.reg) 1197 continue; 1198 1199 // Figure out the value # from the RHS. 1200 unsigned ValInst = LHS.getInstForValNum(VN); 1201 LHSValsDefinedFromRHS[VN] = RHS.getLiveRangeContaining(ValInst-1)->ValId; 1202 } 1203 1204 // Loop over the value numbers of the RHS, seeing if any are defined from 1205 // the LHS. 1206 SmallVector<int, 16> RHSValsDefinedFromLHS; 1207 RHSValsDefinedFromLHS.resize(RHS.getNumValNums(), -1); 1208 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1209 unsigned ValSrcReg = RHS.getSrcRegForValNum(VN); 1210 if (ValSrcReg == 0) // Src not defined by a copy? 1211 continue; 1212 1213 // DstReg is known to be a register in the RHS interval. If the src is 1214 // from the LHS interval, we can use its value #. 1215 if (rep(ValSrcReg) != LHS.reg) 1216 continue; 1217 1218 // Figure out the value # from the LHS. 1219 unsigned ValInst = RHS.getInstForValNum(VN); 1220 RHSValsDefinedFromLHS[VN] = LHS.getLiveRangeContaining(ValInst-1)->ValId; 1221 } 1222 1223 LHSValNoAssignments.resize(LHS.getNumValNums(), -1); 1224 RHSValNoAssignments.resize(RHS.getNumValNums(), -1); 1225 ValueNumberInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); 1226 1227 for (unsigned VN = 0, e = LHS.getNumValNums(); VN != e; ++VN) { 1228 if (LHSValNoAssignments[VN] >= 0 || LHS.getInstForValNum(VN) == ~2U) 1229 continue; 1230 ComputeUltimateVN(VN, ValueNumberInfo, 1231 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, 1232 LHSValNoAssignments, RHSValNoAssignments, LHS, RHS); 1233 } 1234 for (unsigned VN = 0, e = RHS.getNumValNums(); VN != e; ++VN) { 1235 if (RHSValNoAssignments[VN] >= 0 || RHS.getInstForValNum(VN) == ~2U) 1236 continue; 1237 // If this value number isn't a copy from the LHS, it's a new number. 1238 if (RHSValsDefinedFromLHS[VN] == -1) { 1239 ValueNumberInfo.push_back(RHS.getValNumInfo(VN)); 1240 RHSValNoAssignments[VN] = ValueNumberInfo.size()-1; 1241 continue; 1242 } 1243 1244 ComputeUltimateVN(VN, ValueNumberInfo, 1245 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, 1246 RHSValNoAssignments, LHSValNoAssignments, RHS, LHS); 1247 } 1248 } 1249 1250 // Armed with the mappings of LHS/RHS values to ultimate values, walk the 1251 // interval lists to see if these intervals are coallescable. 1252 LiveInterval::const_iterator I = LHS.begin(); 1253 LiveInterval::const_iterator IE = LHS.end(); 1254 LiveInterval::const_iterator J = RHS.begin(); 1255 LiveInterval::const_iterator JE = RHS.end(); 1256 1257 // Skip ahead until the first place of potential sharing. 1258 if (I->start < J->start) { 1259 I = std::upper_bound(I, IE, J->start); 1260 if (I != LHS.begin()) --I; 1261 } else if (J->start < I->start) { 1262 J = std::upper_bound(J, JE, I->start); 1263 if (J != RHS.begin()) --J; 1264 } 1265 1266 while (1) { 1267 // Determine if these two live ranges overlap. 1268 bool Overlaps; 1269 if (I->start < J->start) { 1270 Overlaps = I->end > J->start; 1271 } else { 1272 Overlaps = J->end > I->start; 1273 } 1274 1275 // If so, check value # info to determine if they are really different. 1276 if (Overlaps) { 1277 // If the live range overlap will map to the same value number in the 1278 // result liverange, we can still coallesce them. If not, we can't. 1279 if (LHSValNoAssignments[I->ValId] != RHSValNoAssignments[J->ValId]) 1280 return false; 1281 } 1282 1283 if (I->end < J->end) { 1284 ++I; 1285 if (I == IE) break; 1286 } else { 1287 ++J; 1288 if (J == JE) break; 1289 } 1290 } 1291 1292 // If we get here, we know that we can coallesce the live ranges. Ask the 1293 // intervals to coallesce themselves now. 1294 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], 1295 ValueNumberInfo); 1296 return true; 1297} 1298 1299 1300namespace { 1301 // DepthMBBCompare - Comparison predicate that sort first based on the loop 1302 // depth of the basic block (the unsigned), and then on the MBB number. 1303 struct DepthMBBCompare { 1304 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair; 1305 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const { 1306 if (LHS.first > RHS.first) return true; // Deeper loops first 1307 return LHS.first == RHS.first && 1308 LHS.second->getNumber() < RHS.second->getNumber(); 1309 } 1310 }; 1311} 1312 1313 1314void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB, 1315 std::vector<CopyRec> &TryAgain) { 1316 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n"; 1317 1318 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); 1319 MII != E;) { 1320 MachineInstr *Inst = MII++; 1321 1322 // If this isn't a copy, we can't join intervals. 1323 unsigned SrcReg, DstReg; 1324 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue; 1325 1326 if (!JoinCopy(Inst, SrcReg, DstReg)) 1327 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg)); 1328 } 1329} 1330 1331 1332void LiveIntervals::joinIntervals() { 1333 DOUT << "********** JOINING INTERVALS ***********\n"; 1334 1335 std::vector<CopyRec> TryAgainList; 1336 1337 const LoopInfo &LI = getAnalysis<LoopInfo>(); 1338 if (LI.begin() == LI.end()) { 1339 // If there are no loops in the function, join intervals in function order. 1340 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1341 I != E; ++I) 1342 CopyCoallesceInMBB(I, TryAgainList); 1343 } else { 1344 // Otherwise, join intervals in inner loops before other intervals. 1345 // Unfortunately we can't just iterate over loop hierarchy here because 1346 // there may be more MBB's than BB's. Collect MBB's for sorting. 1347 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; 1348 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); 1349 I != E; ++I) 1350 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I)); 1351 1352 // Sort by loop depth. 1353 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); 1354 1355 // Finally, join intervals in loop nest order. 1356 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) 1357 CopyCoallesceInMBB(MBBs[i].second, TryAgainList); 1358 } 1359 1360 // Joining intervals can allow other intervals to be joined. Iteratively join 1361 // until we make no progress. 1362 bool ProgressMade = true; 1363 while (ProgressMade) { 1364 ProgressMade = false; 1365 1366 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) { 1367 CopyRec &TheCopy = TryAgainList[i]; 1368 if (TheCopy.MI && 1369 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) { 1370 TheCopy.MI = 0; // Mark this one as done. 1371 ProgressMade = true; 1372 } 1373 } 1374 } 1375 1376 DOUT << "*** Register mapping ***\n"; 1377 for (int i = 0, e = r2rMap_.size(); i != e; ++i) 1378 if (r2rMap_[i]) { 1379 DOUT << " reg " << i << " -> "; 1380 DEBUG(printRegName(r2rMap_[i])); 1381 DOUT << "\n"; 1382 } 1383} 1384 1385/// Return true if the two specified registers belong to different register 1386/// classes. The registers may be either phys or virt regs. 1387bool LiveIntervals::differingRegisterClasses(unsigned RegA, 1388 unsigned RegB) const { 1389 1390 // Get the register classes for the first reg. 1391 if (MRegisterInfo::isPhysicalRegister(RegA)) { 1392 assert(MRegisterInfo::isVirtualRegister(RegB) && 1393 "Shouldn't consider two physregs!"); 1394 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA); 1395 } 1396 1397 // Compare against the regclass for the second reg. 1398 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA); 1399 if (MRegisterInfo::isVirtualRegister(RegB)) 1400 return RegClass != mf_->getSSARegMap()->getRegClass(RegB); 1401 else 1402 return !RegClass->contains(RegB); 1403} 1404 1405LiveInterval LiveIntervals::createInterval(unsigned reg) { 1406 float Weight = MRegisterInfo::isPhysicalRegister(reg) ? 1407 HUGE_VALF : 0.0F; 1408 return LiveInterval(reg, Weight); 1409} 1410