LiveVariables.cpp revision 40a627ddf87fe8e5fe057fba405cc0893cf14e70
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveVariable analysis pass. For each machine 11// instruction in the function, this pass calculates the set of registers that 12// are immediately dead after the instruction (i.e., the instruction calculates 13// the value, but it is never used) and the set of registers that are used by 14// the instruction, but are never used after the instruction (i.e., they are 15// killed). 16// 17// This class computes live variables using are sparse implementation based on 18// the machine code SSA form. This class computes live variable information for 19// each virtual and _register allocatable_ physical register in a function. It 20// uses the dominance properties of SSA form to efficiently compute live 21// variables for virtual registers, and assumes that physical registers are only 22// live within a single basic block (allowing it to do a single local analysis 23// to resolve physical register lifetimes in each basic block). If a physical 24// register is not register allocatable, it is not tracked. This is useful for 25// things like the stack pointer and condition codes. 26// 27//===----------------------------------------------------------------------===// 28 29#include "llvm/CodeGen/LiveVariables.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineRegisterInfo.h" 32#include "llvm/Target/MRegisterInfo.h" 33#include "llvm/Target/TargetInstrInfo.h" 34#include "llvm/Target/TargetMachine.h" 35#include "llvm/ADT/DepthFirstIterator.h" 36#include "llvm/ADT/SmallPtrSet.h" 37#include "llvm/ADT/STLExtras.h" 38#include "llvm/Config/alloca.h" 39#include <algorithm> 40using namespace llvm; 41 42char LiveVariables::ID = 0; 43static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis"); 44 45void LiveVariables::VarInfo::dump() const { 46 cerr << " Alive in blocks: "; 47 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i) 48 if (AliveBlocks[i]) cerr << i << ", "; 49 cerr << " Used in blocks: "; 50 for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i) 51 if (UsedBlocks[i]) cerr << i << ", "; 52 cerr << "\n Killed by:"; 53 if (Kills.empty()) 54 cerr << " No instructions.\n"; 55 else { 56 for (unsigned i = 0, e = Kills.size(); i != e; ++i) 57 cerr << "\n #" << i << ": " << *Kills[i]; 58 cerr << "\n"; 59 } 60} 61 62LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 63 assert(MRegisterInfo::isVirtualRegister(RegIdx) && 64 "getVarInfo: not a virtual register!"); 65 RegIdx -= MRegisterInfo::FirstVirtualRegister; 66 if (RegIdx >= VirtRegInfo.size()) { 67 if (RegIdx >= 2*VirtRegInfo.size()) 68 VirtRegInfo.resize(RegIdx*2); 69 else 70 VirtRegInfo.resize(2*VirtRegInfo.size()); 71 } 72 VarInfo &VI = VirtRegInfo[RegIdx]; 73 VI.AliveBlocks.resize(MF->getNumBlockIDs()); 74 VI.UsedBlocks.resize(MF->getNumBlockIDs()); 75 return VI; 76} 77 78bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { 79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 80 MachineOperand &MO = MI->getOperand(i); 81 if (MO.isRegister() && MO.isKill()) { 82 if ((MO.getReg() == Reg) || 83 (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 84 MRegisterInfo::isPhysicalRegister(Reg) && 85 RegInfo->isSubRegister(MO.getReg(), Reg))) 86 return true; 87 } 88 } 89 return false; 90} 91 92bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { 93 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 94 MachineOperand &MO = MI->getOperand(i); 95 if (MO.isRegister() && MO.isDead()) { 96 if ((MO.getReg() == Reg) || 97 (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 98 MRegisterInfo::isPhysicalRegister(Reg) && 99 RegInfo->isSubRegister(MO.getReg(), Reg))) 100 return true; 101 } 102 } 103 return false; 104} 105 106bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { 107 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 108 MachineOperand &MO = MI->getOperand(i); 109 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) 110 return true; 111 } 112 return false; 113} 114 115void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo, 116 MachineBasicBlock *DefBlock, 117 MachineBasicBlock *MBB, 118 std::vector<MachineBasicBlock*> &WorkList) { 119 unsigned BBNum = MBB->getNumber(); 120 121 // Check to see if this basic block is one of the killing blocks. If so, 122 // remove it... 123 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 124 if (VRInfo.Kills[i]->getParent() == MBB) { 125 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 126 break; 127 } 128 129 if (MBB == DefBlock) return; // Terminate recursion 130 131 if (VRInfo.AliveBlocks[BBNum]) 132 return; // We already know the block is live 133 134 // Mark the variable known alive in this bb 135 VRInfo.AliveBlocks[BBNum] = true; 136 137 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(), 138 E = MBB->pred_rend(); PI != E; ++PI) 139 WorkList.push_back(*PI); 140} 141 142void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo, 143 MachineBasicBlock *DefBlock, 144 MachineBasicBlock *MBB) { 145 std::vector<MachineBasicBlock*> WorkList; 146 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList); 147 while (!WorkList.empty()) { 148 MachineBasicBlock *Pred = WorkList.back(); 149 WorkList.pop_back(); 150 MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList); 151 } 152} 153 154 155void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, 156 MachineInstr *MI) { 157 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); 158 assert(MRI.getVRegDef(reg) && "Register use before def!"); 159 160 unsigned BBNum = MBB->getNumber(); 161 162 VarInfo& VRInfo = getVarInfo(reg); 163 VRInfo.UsedBlocks[BBNum] = true; 164 VRInfo.NumUses++; 165 166 // Check to see if this basic block is already a kill block... 167 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { 168 // Yes, this register is killed in this basic block already. Increase the 169 // live range by updating the kill instruction. 170 VRInfo.Kills.back() = MI; 171 return; 172 } 173 174#ifndef NDEBUG 175 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 176 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!"); 177#endif 178 179 assert(MBB != MRI.getVRegDef(reg)->getParent() && 180 "Should have kill for defblock!"); 181 182 // Add a new kill entry for this basic block. 183 // If this virtual register is already marked as alive in this basic block, 184 // that means it is alive in at least one of the successor block, it's not 185 // a kill. 186 if (!VRInfo.AliveBlocks[BBNum]) 187 VRInfo.Kills.push_back(MI); 188 189 // Update all dominating blocks to mark them known live. 190 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 191 E = MBB->pred_end(); PI != E; ++PI) 192 MarkVirtRegAliveInBlock(VRInfo, MRI.getVRegDef(reg)->getParent(), *PI); 193} 194 195bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI, 196 const MRegisterInfo *RegInfo, 197 bool AddIfNotFound) { 198 bool Found = false; 199 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 200 MachineOperand &MO = MI->getOperand(i); 201 if (MO.isRegister() && MO.isUse()) { 202 unsigned Reg = MO.getReg(); 203 if (!Reg) 204 continue; 205 if (Reg == IncomingReg) { 206 MO.setIsKill(); 207 Found = true; 208 break; 209 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 210 MRegisterInfo::isPhysicalRegister(IncomingReg) && 211 RegInfo->isSuperRegister(IncomingReg, Reg) && 212 MO.isKill()) 213 // A super-register kill already exists. 214 Found = true; 215 } 216 } 217 218 // If not found, this means an alias of one of the operand is killed. Add a 219 // new implicit operand if required. 220 if (!Found && AddIfNotFound) { 221 MI->addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/, 222 true/*IsImp*/,true/*IsKill*/)); 223 return true; 224 } 225 return Found; 226} 227 228bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI, 229 const MRegisterInfo *RegInfo, 230 bool AddIfNotFound) { 231 bool Found = false; 232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 233 MachineOperand &MO = MI->getOperand(i); 234 if (MO.isRegister() && MO.isDef()) { 235 unsigned Reg = MO.getReg(); 236 if (!Reg) 237 continue; 238 if (Reg == IncomingReg) { 239 MO.setIsDead(); 240 Found = true; 241 break; 242 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 243 MRegisterInfo::isPhysicalRegister(IncomingReg) && 244 RegInfo->isSuperRegister(IncomingReg, Reg) && 245 MO.isDead()) 246 // There exists a super-register that's marked dead. 247 return true; 248 } 249 } 250 251 // If not found, this means an alias of one of the operand is dead. Add a 252 // new implicit operand. 253 if (!Found && AddIfNotFound) { 254 MI->addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/, 255 true/*IsImp*/,false/*IsKill*/, 256 true/*IsDead*/)); 257 return true; 258 } 259 return Found; 260} 261 262void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 263 // Turn previous partial def's into read/mod/write. 264 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) { 265 MachineInstr *Def = PhysRegPartDef[Reg][i]; 266 // First one is just a def. This means the use is reading some undef bits. 267 if (i != 0) 268 Def->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, 269 true/*IsImp*/,true/*IsKill*/)); 270 Def->addOperand(MachineOperand::CreateReg(Reg,true/*IsDef*/,true/*IsImp*/)); 271 } 272 PhysRegPartDef[Reg].clear(); 273 274 // There was an earlier def of a super-register. Add implicit def to that MI. 275 // A: EAX = ... 276 // B: = AX 277 // Add implicit def to A. 278 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] && 279 !PhysRegUsed[Reg]) { 280 MachineInstr *Def = PhysRegInfo[Reg]; 281 if (!Def->findRegisterDefOperand(Reg)) 282 Def->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 283 true/*IsImp*/)); 284 } 285 286 // There is a now a proper use, forget about the last partial use. 287 PhysRegPartUse[Reg] = NULL; 288 PhysRegInfo[Reg] = MI; 289 PhysRegUsed[Reg] = true; 290 291 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 292 unsigned SubReg = *SubRegs; ++SubRegs) { 293 PhysRegInfo[SubReg] = MI; 294 PhysRegUsed[SubReg] = true; 295 } 296 297 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); 298 unsigned SuperReg = *SuperRegs; ++SuperRegs) { 299 // Remember the partial use of this superreg if it was previously defined. 300 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL; 301 if (!HasPrevDef) { 302 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg); 303 unsigned SSReg = *SSRegs; ++SSRegs) { 304 if (PhysRegInfo[SSReg] != NULL) { 305 HasPrevDef = true; 306 break; 307 } 308 } 309 } 310 if (HasPrevDef) { 311 PhysRegInfo[SuperReg] = MI; 312 PhysRegPartUse[SuperReg] = MI; 313 } 314 } 315} 316 317bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI, 318 SmallSet<unsigned, 4> &SubKills) { 319 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 320 unsigned SubReg = *SubRegs; ++SubRegs) { 321 MachineInstr *LastRef = PhysRegInfo[SubReg]; 322 if (LastRef != RefMI || 323 !HandlePhysRegKill(SubReg, RefMI, SubKills)) 324 SubKills.insert(SubReg); 325 } 326 327 if (*RegInfo->getImmediateSubRegisters(Reg) == 0) { 328 // No sub-registers, just check if reg is killed by RefMI. 329 if (PhysRegInfo[Reg] == RefMI) 330 return true; 331 } else if (SubKills.empty()) 332 // None of the sub-registers are killed elsewhere... 333 return true; 334 return false; 335} 336 337void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI, 338 SmallSet<unsigned, 4> &SubKills) { 339 if (SubKills.count(Reg) == 0) 340 addRegisterKilled(Reg, MI, RegInfo, true); 341 else { 342 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 343 unsigned SubReg = *SubRegs; ++SubRegs) 344 addRegisterKills(SubReg, MI, SubKills); 345 } 346} 347 348bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) { 349 SmallSet<unsigned, 4> SubKills; 350 if (HandlePhysRegKill(Reg, RefMI, SubKills)) { 351 addRegisterKilled(Reg, RefMI, RegInfo, true); 352 return true; 353 } else { 354 // Some sub-registers are killed by another MI. 355 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 356 unsigned SubReg = *SubRegs; ++SubRegs) 357 addRegisterKills(SubReg, RefMI, SubKills); 358 return false; 359 } 360} 361 362void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 363 // Does this kill a previous version of this register? 364 if (MachineInstr *LastRef = PhysRegInfo[Reg]) { 365 if (PhysRegUsed[Reg]) { 366 if (!HandlePhysRegKill(Reg, LastRef)) { 367 if (PhysRegPartUse[Reg]) 368 addRegisterKilled(Reg, PhysRegPartUse[Reg], RegInfo, true); 369 } 370 } else if (PhysRegPartUse[Reg]) 371 // Add implicit use / kill to last partial use. 372 addRegisterKilled(Reg, PhysRegPartUse[Reg], RegInfo, true); 373 else if (LastRef != MI) 374 // Defined, but not used. However, watch out for cases where a super-reg 375 // is also defined on the same MI. 376 addRegisterDead(Reg, LastRef, RegInfo); 377 } 378 379 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 380 unsigned SubReg = *SubRegs; ++SubRegs) { 381 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) { 382 if (PhysRegUsed[SubReg]) { 383 if (!HandlePhysRegKill(SubReg, LastRef)) { 384 if (PhysRegPartUse[SubReg]) 385 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], RegInfo, true); 386 } 387 } else if (PhysRegPartUse[SubReg]) 388 // Add implicit use / kill to last use of a sub-register. 389 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], RegInfo, true); 390 else if (LastRef != MI) 391 // This must be a def of the subreg on the same MI. 392 addRegisterDead(SubReg, LastRef, RegInfo); 393 } 394 } 395 396 if (MI) { 397 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); 398 unsigned SuperReg = *SuperRegs; ++SuperRegs) { 399 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) { 400 // The larger register is previously defined. Now a smaller part is 401 // being re-defined. Treat it as read/mod/write. 402 // EAX = 403 // AX = EAX<imp-use,kill>, EAX<imp-def> 404 MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/, 405 true/*IsImp*/,true/*IsKill*/)); 406 MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/, 407 true/*IsImp*/)); 408 PhysRegInfo[SuperReg] = MI; 409 PhysRegUsed[SuperReg] = false; 410 PhysRegPartUse[SuperReg] = NULL; 411 } else { 412 // Remember this partial def. 413 PhysRegPartDef[SuperReg].push_back(MI); 414 } 415 } 416 417 PhysRegInfo[Reg] = MI; 418 PhysRegUsed[Reg] = false; 419 PhysRegPartDef[Reg].clear(); 420 PhysRegPartUse[Reg] = NULL; 421 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 422 unsigned SubReg = *SubRegs; ++SubRegs) { 423 PhysRegInfo[SubReg] = MI; 424 PhysRegUsed[SubReg] = false; 425 PhysRegPartDef[SubReg].clear(); 426 PhysRegPartUse[SubReg] = NULL; 427 } 428 } 429} 430 431bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { 432 MF = &mf; 433 RegInfo = MF->getTarget().getRegisterInfo(); 434 MachineRegisterInfo& MRI = mf.getRegInfo(); 435 assert(RegInfo && "Target doesn't have register information?"); 436 437 ReservedRegisters = RegInfo->getReservedRegs(mf); 438 439 unsigned NumRegs = RegInfo->getNumRegs(); 440 PhysRegInfo = new MachineInstr*[NumRegs]; 441 PhysRegUsed = new bool[NumRegs]; 442 PhysRegPartUse = new MachineInstr*[NumRegs]; 443 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs]; 444 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()]; 445 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); 446 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); 447 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); 448 449 /// Get some space for a respectable number of registers... 450 VirtRegInfo.resize(64); 451 452 analyzePHINodes(mf); 453 454 // Calculate live variable information in depth first order on the CFG of the 455 // function. This guarantees that we will see the definition of a virtual 456 // register before its uses due to dominance properties of SSA (except for PHI 457 // nodes, which are treated as a special case). 458 // 459 MachineBasicBlock *Entry = MF->begin(); 460 SmallPtrSet<MachineBasicBlock*,16> Visited; 461 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> > 462 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); 463 DFI != E; ++DFI) { 464 MachineBasicBlock *MBB = *DFI; 465 466 // Mark live-in registers as live-in. 467 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(), 468 EE = MBB->livein_end(); II != EE; ++II) { 469 assert(MRegisterInfo::isPhysicalRegister(*II) && 470 "Cannot have a live-in virtual register!"); 471 HandlePhysRegDef(*II, 0); 472 } 473 474 // Loop over all of the instructions, processing them. 475 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 476 I != E; ++I) { 477 MachineInstr *MI = I; 478 479 // Process all of the operands of the instruction... 480 unsigned NumOperandsToProcess = MI->getNumOperands(); 481 482 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 483 // of the uses. They will be handled in other basic blocks. 484 if (MI->getOpcode() == TargetInstrInfo::PHI) 485 NumOperandsToProcess = 1; 486 487 // Process all uses... 488 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 489 MachineOperand &MO = MI->getOperand(i); 490 if (MO.isRegister() && MO.isUse() && MO.getReg()) { 491 if (MRegisterInfo::isVirtualRegister(MO.getReg())){ 492 HandleVirtRegUse(MO.getReg(), MBB, MI); 493 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 494 !ReservedRegisters[MO.getReg()]) { 495 HandlePhysRegUse(MO.getReg(), MI); 496 } 497 } 498 } 499 500 // Process all defs... 501 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 502 MachineOperand &MO = MI->getOperand(i); 503 if (MO.isRegister() && MO.isDef() && MO.getReg()) { 504 if (MRegisterInfo::isVirtualRegister(MO.getReg())) { 505 VarInfo &VRInfo = getVarInfo(MO.getReg()); 506 // Defaults to dead 507 VRInfo.Kills.push_back(MI); 508 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 509 !ReservedRegisters[MO.getReg()]) { 510 HandlePhysRegDef(MO.getReg(), MI); 511 } 512 } 513 } 514 } 515 516 // Handle any virtual assignments from PHI nodes which might be at the 517 // bottom of this basic block. We check all of our successor blocks to see 518 // if they have PHI nodes, and if so, we simulate an assignment at the end 519 // of the current block. 520 if (!PHIVarInfo[MBB->getNumber()].empty()) { 521 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()]; 522 523 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(), 524 E = VarInfoVec.end(); I != E; ++I) { 525 // Only mark it alive only in the block we are representing. 526 MarkVirtRegAliveInBlock(getVarInfo(*I), MRI.getVRegDef(*I)->getParent(), 527 MBB); 528 } 529 } 530 531 // Finally, if the last instruction in the block is a return, make sure to mark 532 // it as using all of the live-out values in the function. 533 if (!MBB->empty() && MBB->back().getDesc().isReturn()) { 534 MachineInstr *Ret = &MBB->back(); 535 for (MachineRegisterInfo::liveout_iterator 536 I = MF->getRegInfo().liveout_begin(), 537 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 538 assert(MRegisterInfo::isPhysicalRegister(*I) && 539 "Cannot have a live-in virtual register!"); 540 HandlePhysRegUse(*I, Ret); 541 // Add live-out registers as implicit uses. 542 if (Ret->findRegisterUseOperandIdx(*I) == -1) 543 Ret->addOperand(MachineOperand::CreateReg(*I, false, true)); 544 } 545 } 546 547 // Loop over PhysRegInfo, killing any registers that are available at the 548 // end of the basic block. This also resets the PhysRegInfo map. 549 for (unsigned i = 0; i != NumRegs; ++i) 550 if (PhysRegInfo[i]) 551 HandlePhysRegDef(i, 0); 552 553 // Clear some states between BB's. These are purely local information. 554 for (unsigned i = 0; i != NumRegs; ++i) 555 PhysRegPartDef[i].clear(); 556 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); 557 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); 558 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); 559 } 560 561 // Convert and transfer the dead / killed information we have gathered into 562 // VirtRegInfo onto MI's. 563 // 564 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) 565 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) { 566 if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i + 567 MRegisterInfo::FirstVirtualRegister)) 568 addRegisterDead(i + MRegisterInfo::FirstVirtualRegister, 569 VirtRegInfo[i].Kills[j], RegInfo); 570 else 571 addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister, 572 VirtRegInfo[i].Kills[j], RegInfo); 573 } 574 575 // Check to make sure there are no unreachable blocks in the MC CFG for the 576 // function. If so, it is due to a bug in the instruction selector or some 577 // other part of the code generator if this happens. 578#ifndef NDEBUG 579 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i) 580 assert(Visited.count(&*i) != 0 && "unreachable basic block found"); 581#endif 582 583 delete[] PhysRegInfo; 584 delete[] PhysRegUsed; 585 delete[] PhysRegPartUse; 586 delete[] PhysRegPartDef; 587 delete[] PHIVarInfo; 588 589 return false; 590} 591 592/// instructionChanged - When the address of an instruction changes, this 593/// method should be called so that live variables can update its internal 594/// data structures. This removes the records for OldMI, transfering them to 595/// the records for NewMI. 596void LiveVariables::instructionChanged(MachineInstr *OldMI, 597 MachineInstr *NewMI) { 598 // If the instruction defines any virtual registers, update the VarInfo, 599 // kill and dead information for the instruction. 600 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { 601 MachineOperand &MO = OldMI->getOperand(i); 602 if (MO.isRegister() && MO.getReg() && 603 MRegisterInfo::isVirtualRegister(MO.getReg())) { 604 unsigned Reg = MO.getReg(); 605 VarInfo &VI = getVarInfo(Reg); 606 if (MO.isDef()) { 607 if (MO.isDead()) { 608 MO.setIsDead(false); 609 addVirtualRegisterDead(Reg, NewMI); 610 } 611 } 612 if (MO.isKill()) { 613 MO.setIsKill(false); 614 addVirtualRegisterKilled(Reg, NewMI); 615 } 616 // If this is a kill of the value, update the VI kills list. 617 if (VI.removeKill(OldMI)) 618 VI.Kills.push_back(NewMI); // Yes, there was a kill of it 619 } 620 } 621} 622 623/// transferKillDeadInfo - Similar to instructionChanged except it does not 624/// update live variables internal data structures. 625void LiveVariables::transferKillDeadInfo(MachineInstr *OldMI, 626 MachineInstr *NewMI, 627 const MRegisterInfo *RegInfo) { 628 // If the instruction defines any virtual registers, update the VarInfo, 629 // kill and dead information for the instruction. 630 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { 631 MachineOperand &MO = OldMI->getOperand(i); 632 if (MO.isRegister() && MO.getReg() && 633 MRegisterInfo::isVirtualRegister(MO.getReg())) { 634 unsigned Reg = MO.getReg(); 635 if (MO.isDef()) { 636 if (MO.isDead()) { 637 MO.setIsDead(false); 638 addRegisterDead(Reg, NewMI, RegInfo); 639 } 640 } 641 if (MO.isKill()) { 642 MO.setIsKill(false); 643 addRegisterKilled(Reg, NewMI, RegInfo); 644 } 645 } 646 } 647} 648 649 650/// removeVirtualRegistersKilled - Remove all killed info for the specified 651/// instruction. 652void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { 653 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 654 MachineOperand &MO = MI->getOperand(i); 655 if (MO.isRegister() && MO.isKill()) { 656 MO.setIsKill(false); 657 unsigned Reg = MO.getReg(); 658 if (MRegisterInfo::isVirtualRegister(Reg)) { 659 bool removed = getVarInfo(Reg).removeKill(MI); 660 assert(removed && "kill not in register's VarInfo?"); 661 } 662 } 663 } 664} 665 666/// removeVirtualRegistersDead - Remove all of the dead registers for the 667/// specified instruction from the live variable information. 668void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { 669 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 670 MachineOperand &MO = MI->getOperand(i); 671 if (MO.isRegister() && MO.isDead()) { 672 MO.setIsDead(false); 673 unsigned Reg = MO.getReg(); 674 if (MRegisterInfo::isVirtualRegister(Reg)) { 675 bool removed = getVarInfo(Reg).removeKill(MI); 676 assert(removed && "kill not in register's VarInfo?"); 677 } 678 } 679 } 680} 681 682/// analyzePHINodes - Gather information about the PHI nodes in here. In 683/// particular, we want to map the variable information of a virtual 684/// register which is used in a PHI node. We map that to the BB the vreg is 685/// coming from. 686/// 687void LiveVariables::analyzePHINodes(const MachineFunction& Fn) { 688 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 689 I != E; ++I) 690 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 691 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 692 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 693 PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]. 694 push_back(BBI->getOperand(i).getReg()); 695} 696