LiveVariables.cpp revision 60c7df2c9311fc35ab02f1600419e91d55d5b133
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the LiveVariable analysis pass.  For each machine
11// instruction in the function, this pass calculates the set of registers that
12// are immediately dead after the instruction (i.e., the instruction calculates
13// the value, but it is never used) and the set of registers that are used by
14// the instruction, but are never used after the instruction (i.e., they are
15// killed).
16//
17// This class computes live variables using are sparse implementation based on
18// the machine code SSA form.  This class computes live variable information for
19// each virtual and _register allocatable_ physical register in a function.  It
20// uses the dominance properties of SSA form to efficiently compute live
21// variables for virtual registers, and assumes that physical registers are only
22// live within a single basic block (allowing it to do a single local analysis
23// to resolve physical register lifetimes in each basic block).  If a physical
24// register is not register allocatable, it is not tracked.  This is useful for
25// things like the stack pointer and condition codes.
26//
27//===----------------------------------------------------------------------===//
28
29#include "llvm/CodeGen/LiveVariables.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/Target/TargetRegisterInfo.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/ADT/DepthFirstIterator.h"
37#include "llvm/ADT/SmallPtrSet.h"
38#include "llvm/ADT/SmallSet.h"
39#include "llvm/ADT/STLExtras.h"
40#include <algorithm>
41using namespace llvm;
42
43char LiveVariables::ID = 0;
44static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis");
45
46
47void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
48  AU.addRequiredID(UnreachableMachineBlockElimID);
49  AU.setPreservesAll();
50  MachineFunctionPass::getAnalysisUsage(AU);
51}
52
53void LiveVariables::VarInfo::dump() const {
54  errs() << "  Alive in blocks: ";
55  for (SparseBitVector<>::iterator I = AliveBlocks.begin(),
56           E = AliveBlocks.end(); I != E; ++I)
57    errs() << *I << ", ";
58  errs() << "\n  Killed by:";
59  if (Kills.empty())
60    errs() << " No instructions.\n";
61  else {
62    for (unsigned i = 0, e = Kills.size(); i != e; ++i)
63      errs() << "\n    #" << i << ": " << *Kills[i];
64    errs() << "\n";
65  }
66}
67
68/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
69LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) {
70  assert(TargetRegisterInfo::isVirtualRegister(RegIdx) &&
71         "getVarInfo: not a virtual register!");
72  RegIdx -= TargetRegisterInfo::FirstVirtualRegister;
73  if (RegIdx >= VirtRegInfo.size()) {
74    if (RegIdx >= 2*VirtRegInfo.size())
75      VirtRegInfo.resize(RegIdx*2);
76    else
77      VirtRegInfo.resize(2*VirtRegInfo.size());
78  }
79  return VirtRegInfo[RegIdx];
80}
81
82void LiveVariables::MarkVirtRegAliveInBlock(VarInfo& VRInfo,
83                                            MachineBasicBlock *DefBlock,
84                                            MachineBasicBlock *MBB,
85                                    std::vector<MachineBasicBlock*> &WorkList) {
86  unsigned BBNum = MBB->getNumber();
87
88  // Check to see if this basic block is one of the killing blocks.  If so,
89  // remove it.
90  for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
91    if (VRInfo.Kills[i]->getParent() == MBB) {
92      VRInfo.Kills.erase(VRInfo.Kills.begin()+i);  // Erase entry
93      break;
94    }
95
96  if (MBB == DefBlock) return;  // Terminate recursion
97
98  if (VRInfo.AliveBlocks.test(BBNum))
99    return;  // We already know the block is live
100
101  // Mark the variable known alive in this bb
102  VRInfo.AliveBlocks.set(BBNum);
103
104  for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(),
105         E = MBB->pred_rend(); PI != E; ++PI)
106    WorkList.push_back(*PI);
107}
108
109void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
110                                            MachineBasicBlock *DefBlock,
111                                            MachineBasicBlock *MBB) {
112  std::vector<MachineBasicBlock*> WorkList;
113  MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
114
115  while (!WorkList.empty()) {
116    MachineBasicBlock *Pred = WorkList.back();
117    WorkList.pop_back();
118    MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
119  }
120}
121
122void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
123                                     MachineInstr *MI) {
124  assert(MRI->getVRegDef(reg) && "Register use before def!");
125
126  unsigned BBNum = MBB->getNumber();
127
128  VarInfo& VRInfo = getVarInfo(reg);
129  VRInfo.NumUses++;
130
131  // Check to see if this basic block is already a kill block.
132  if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
133    // Yes, this register is killed in this basic block already. Increase the
134    // live range by updating the kill instruction.
135    VRInfo.Kills.back() = MI;
136    return;
137  }
138
139#ifndef NDEBUG
140  for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
141    assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
142#endif
143
144  // This situation can occur:
145  //
146  //     ,------.
147  //     |      |
148  //     |      v
149  //     |   t2 = phi ... t1 ...
150  //     |      |
151  //     |      v
152  //     |   t1 = ...
153  //     |  ... = ... t1 ...
154  //     |      |
155  //     `------'
156  //
157  // where there is a use in a PHI node that's a predecessor to the defining
158  // block. We don't want to mark all predecessors as having the value "alive"
159  // in this case.
160  if (MBB == MRI->getVRegDef(reg)->getParent()) return;
161
162  // Add a new kill entry for this basic block. If this virtual register is
163  // already marked as alive in this basic block, that means it is alive in at
164  // least one of the successor blocks, it's not a kill.
165  if (!VRInfo.AliveBlocks.test(BBNum))
166    VRInfo.Kills.push_back(MI);
167
168  // Update all dominating blocks to mark them as "known live".
169  for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
170         E = MBB->pred_end(); PI != E; ++PI)
171    MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
172}
173
174void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
175  VarInfo &VRInfo = getVarInfo(Reg);
176
177  if (VRInfo.AliveBlocks.empty())
178    // If vr is not alive in any block, then defaults to dead.
179    VRInfo.Kills.push_back(MI);
180}
181
182/// FindLastPartialDef - Return the last partial def of the specified register.
183/// Also returns the sub-registers that're defined by the instruction.
184MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg,
185                                            SmallSet<unsigned,4> &PartDefRegs) {
186  unsigned LastDefReg = 0;
187  unsigned LastDefDist = 0;
188  MachineInstr *LastDef = NULL;
189  for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
190       unsigned SubReg = *SubRegs; ++SubRegs) {
191    MachineInstr *Def = PhysRegDef[SubReg];
192    if (!Def)
193      continue;
194    unsigned Dist = DistanceMap[Def];
195    if (Dist > LastDefDist) {
196      LastDefReg  = SubReg;
197      LastDef     = Def;
198      LastDefDist = Dist;
199    }
200  }
201
202  if (!LastDef)
203    return 0;
204
205  PartDefRegs.insert(LastDefReg);
206  for (unsigned i = 0, e = LastDef->getNumOperands(); i != e; ++i) {
207    MachineOperand &MO = LastDef->getOperand(i);
208    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
209      continue;
210    unsigned DefReg = MO.getReg();
211    if (TRI->isSubRegister(Reg, DefReg)) {
212      PartDefRegs.insert(DefReg);
213      for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg);
214           unsigned SubReg = *SubRegs; ++SubRegs)
215        PartDefRegs.insert(SubReg);
216    }
217  }
218  return LastDef;
219}
220
221/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
222/// implicit defs to a machine instruction if there was an earlier def of its
223/// super-register.
224void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
225  // If there was a previous use or a "full" def all is well.
226  if (!PhysRegDef[Reg] && !PhysRegUse[Reg]) {
227    // Otherwise, the last sub-register def implicitly defines this register.
228    // e.g.
229    // AH =
230    // AL = ... <imp-def EAX>, <imp-kill AH>
231    //    = AH
232    // ...
233    //    = EAX
234    // All of the sub-registers must have been defined before the use of Reg!
235    SmallSet<unsigned, 4> PartDefRegs;
236    MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
237    // If LastPartialDef is NULL, it must be using a livein register.
238    if (LastPartialDef) {
239      LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
240                                                           true/*IsImp*/));
241      PhysRegDef[Reg] = LastPartialDef;
242      SmallSet<unsigned, 8> Processed;
243      for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
244           unsigned SubReg = *SubRegs; ++SubRegs) {
245        if (Processed.count(SubReg))
246          continue;
247        if (PartDefRegs.count(SubReg))
248          continue;
249        // This part of Reg was defined before the last partial def. It's killed
250        // here.
251        LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
252                                                             false/*IsDef*/,
253                                                             true/*IsImp*/));
254        PhysRegDef[SubReg] = LastPartialDef;
255        for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
256          Processed.insert(*SS);
257      }
258    }
259  }
260
261  // Remember this use.
262  PhysRegUse[Reg]  = MI;
263  for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
264       unsigned SubReg = *SubRegs; ++SubRegs)
265    PhysRegUse[SubReg] =  MI;
266}
267
268/// hasRegisterUseBelow - Return true if the specified register is used after
269/// the current instruction and before it's next definition.
270bool LiveVariables::hasRegisterUseBelow(unsigned Reg,
271                                        MachineBasicBlock::iterator I,
272                                        MachineBasicBlock *MBB) {
273  if (I == MBB->end())
274    return false;
275
276  // First find out if there are any uses / defs below.
277  bool hasDistInfo = true;
278  unsigned CurDist = DistanceMap[I];
279  SmallVector<MachineInstr*, 4> Uses;
280  SmallVector<MachineInstr*, 4> Defs;
281  for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
282         RE = MRI->reg_end(); RI != RE; ++RI) {
283    MachineOperand &UDO = RI.getOperand();
284    MachineInstr *UDMI = &*RI;
285    if (UDMI->getParent() != MBB)
286      continue;
287    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
288    bool isBelow = false;
289    if (DI == DistanceMap.end()) {
290      // Must be below if it hasn't been assigned a distance yet.
291      isBelow = true;
292      hasDistInfo = false;
293    } else if (DI->second > CurDist)
294      isBelow = true;
295    if (isBelow) {
296      if (UDO.isUse())
297        Uses.push_back(UDMI);
298      if (UDO.isDef())
299        Defs.push_back(UDMI);
300    }
301  }
302
303  if (Uses.empty())
304    // No uses below.
305    return false;
306  else if (!Uses.empty() && Defs.empty())
307    // There are uses below but no defs below.
308    return true;
309  // There are both uses and defs below. We need to know which comes first.
310  if (!hasDistInfo) {
311    // Complete DistanceMap for this MBB. This information is computed only
312    // once per MBB.
313    ++I;
314    ++CurDist;
315    for (MachineBasicBlock::iterator E = MBB->end(); I != E; ++I, ++CurDist)
316      DistanceMap.insert(std::make_pair(I, CurDist));
317  }
318
319  unsigned EarliestUse = DistanceMap[Uses[0]];
320  for (unsigned i = 1, e = Uses.size(); i != e; ++i) {
321    unsigned Dist = DistanceMap[Uses[i]];
322    if (Dist < EarliestUse)
323      EarliestUse = Dist;
324  }
325  for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
326    unsigned Dist = DistanceMap[Defs[i]];
327    if (Dist < EarliestUse)
328      // The register is defined before its first use below.
329      return false;
330  }
331  return true;
332}
333
334bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *MI) {
335  if (!PhysRegUse[Reg] && !PhysRegDef[Reg])
336    return false;
337
338  MachineInstr *LastRefOrPartRef = PhysRegUse[Reg]
339    ? PhysRegUse[Reg] : PhysRegDef[Reg];
340  unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
341  // The whole register is used.
342  // AL =
343  // AH =
344  //
345  //    = AX
346  //    = AL, AX<imp-use, kill>
347  // AX =
348  //
349  // Or whole register is defined, but not used at all.
350  // AX<dead> =
351  // ...
352  // AX =
353  //
354  // Or whole register is defined, but only partly used.
355  // AX<dead> = AL<imp-def>
356  //    = AL<kill>
357  // AX =
358  SmallSet<unsigned, 8> PartUses;
359  for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
360       unsigned SubReg = *SubRegs; ++SubRegs) {
361    if (MachineInstr *Use = PhysRegUse[SubReg]) {
362      PartUses.insert(SubReg);
363      for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
364        PartUses.insert(*SS);
365      unsigned Dist = DistanceMap[Use];
366      if (Dist > LastRefOrPartRefDist) {
367        LastRefOrPartRefDist = Dist;
368        LastRefOrPartRef = Use;
369      }
370    }
371  }
372
373  if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI)
374    // If the last reference is the last def, then it's not used at all.
375    // That is, unless we are currently processing the last reference itself.
376    LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
377
378  // Partial uses. Mark register def dead and add implicit def of
379  // sub-registers which are used.
380  // EAX<dead>  = op  AL<imp-def>
381  // That is, EAX def is dead but AL def extends pass it.
382  // Enable this after live interval analysis is fixed to improve codegen!
383  else if (!PhysRegUse[Reg]) {
384    PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
385    for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
386         unsigned SubReg = *SubRegs; ++SubRegs) {
387      if (PartUses.count(SubReg)) {
388        bool NeedDef = true;
389        if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
390          MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg);
391          if (MO) {
392            NeedDef = false;
393            assert(!MO->isDead());
394          }
395        }
396        if (NeedDef)
397          PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
398                                                                true, true));
399        LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
400        for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
401          PartUses.erase(*SS);
402      }
403    }
404  }
405  else
406    LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
407  return true;
408}
409
410void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
411  // What parts of the register are previously defined?
412  SmallSet<unsigned, 32> Live;
413  if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
414    Live.insert(Reg);
415    for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
416      Live.insert(*SS);
417  } else {
418    for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
419         unsigned SubReg = *SubRegs; ++SubRegs) {
420      // If a register isn't itself defined, but all parts that make up of it
421      // are defined, then consider it also defined.
422      // e.g.
423      // AL =
424      // AH =
425      //    = AX
426      if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
427        Live.insert(SubReg);
428        for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
429          Live.insert(*SS);
430      }
431    }
432  }
433
434  // Start from the largest piece, find the last time any part of the register
435  // is referenced.
436  if (!HandlePhysRegKill(Reg, MI)) {
437    // Only some of the sub-registers are used.
438    for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
439         unsigned SubReg = *SubRegs; ++SubRegs) {
440      if (!Live.count(SubReg))
441        // Skip if this sub-register isn't defined.
442        continue;
443      if (HandlePhysRegKill(SubReg, MI)) {
444        Live.erase(SubReg);
445        for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS)
446          Live.erase(*SS);
447      }
448    }
449    assert(Live.empty() && "Not all defined registers are killed / dead?");
450  }
451
452  if (MI) {
453    // Does this extend the live range of a super-register?
454    SmallSet<unsigned, 8> Processed;
455    for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
456         unsigned SuperReg = *SuperRegs; ++SuperRegs) {
457      if (Processed.count(SuperReg))
458        continue;
459      MachineInstr *LastRef = PhysRegUse[SuperReg]
460        ? PhysRegUse[SuperReg] : PhysRegDef[SuperReg];
461      if (LastRef && LastRef != MI) {
462        // The larger register is previously defined. Now a smaller part is
463        // being re-defined. Treat it as read/mod/write if there are uses
464        // below.
465        // EAX =
466        // AX  =        EAX<imp-use,kill>, EAX<imp-def>
467        // ...
468        ///    =  EAX
469        if (hasRegisterUseBelow(SuperReg, MI, MI->getParent())) {
470          MI->addOperand(MachineOperand::CreateReg(SuperReg, false/*IsDef*/,
471                                                   true/*IsImp*/,true/*IsKill*/));
472          MI->addOperand(MachineOperand::CreateReg(SuperReg, true/*IsDef*/,
473                                                   true/*IsImp*/));
474          PhysRegDef[SuperReg]  = MI;
475          PhysRegUse[SuperReg]  = NULL;
476          Processed.insert(SuperReg);
477          for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
478            PhysRegDef[*SS]  = MI;
479            PhysRegUse[*SS]  = NULL;
480            Processed.insert(*SS);
481          }
482        } else {
483          // Otherwise, the super register is killed.
484          if (HandlePhysRegKill(SuperReg, MI)) {
485            PhysRegDef[SuperReg]  = NULL;
486            PhysRegUse[SuperReg]  = NULL;
487            for (const unsigned *SS = TRI->getSubRegisters(SuperReg); *SS; ++SS) {
488              PhysRegDef[*SS]  = NULL;
489              PhysRegUse[*SS]  = NULL;
490              Processed.insert(*SS);
491            }
492          }
493        }
494      }
495    }
496
497    // Remember this def.
498    PhysRegDef[Reg]  = MI;
499    PhysRegUse[Reg]  = NULL;
500    for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
501         unsigned SubReg = *SubRegs; ++SubRegs) {
502      PhysRegDef[SubReg]  = MI;
503      PhysRegUse[SubReg]  = NULL;
504    }
505  }
506}
507
508bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
509  MF = &mf;
510  MRI = &mf.getRegInfo();
511  TRI = MF->getTarget().getRegisterInfo();
512
513  ReservedRegisters = TRI->getReservedRegs(mf);
514
515  unsigned NumRegs = TRI->getNumRegs();
516  PhysRegDef  = new MachineInstr*[NumRegs];
517  PhysRegUse  = new MachineInstr*[NumRegs];
518  PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()];
519  std::fill(PhysRegDef,  PhysRegDef  + NumRegs, (MachineInstr*)0);
520  std::fill(PhysRegUse,  PhysRegUse  + NumRegs, (MachineInstr*)0);
521
522  /// Get some space for a respectable number of registers.
523  VirtRegInfo.resize(64);
524
525  analyzePHINodes(mf);
526
527  // Calculate live variable information in depth first order on the CFG of the
528  // function.  This guarantees that we will see the definition of a virtual
529  // register before its uses due to dominance properties of SSA (except for PHI
530  // nodes, which are treated as a special case).
531  MachineBasicBlock *Entry = MF->begin();
532  SmallPtrSet<MachineBasicBlock*,16> Visited;
533
534  for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> >
535         DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
536       DFI != E; ++DFI) {
537    MachineBasicBlock *MBB = *DFI;
538
539    // Mark live-in registers as live-in.
540    for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(),
541           EE = MBB->livein_end(); II != EE; ++II) {
542      assert(TargetRegisterInfo::isPhysicalRegister(*II) &&
543             "Cannot have a live-in virtual register!");
544      HandlePhysRegDef(*II, 0);
545    }
546
547    // Loop over all of the instructions, processing them.
548    DistanceMap.clear();
549    unsigned Dist = 0;
550    for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
551         I != E; ++I) {
552      MachineInstr *MI = I;
553      DistanceMap.insert(std::make_pair(MI, Dist++));
554
555      // Process all of the operands of the instruction...
556      unsigned NumOperandsToProcess = MI->getNumOperands();
557
558      // Unless it is a PHI node.  In this case, ONLY process the DEF, not any
559      // of the uses.  They will be handled in other basic blocks.
560      if (MI->getOpcode() == TargetInstrInfo::PHI)
561        NumOperandsToProcess = 1;
562
563      SmallVector<unsigned, 4> UseRegs;
564      SmallVector<unsigned, 4> DefRegs;
565      for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
566        const MachineOperand &MO = MI->getOperand(i);
567        if (!MO.isReg() || MO.getReg() == 0)
568          continue;
569        unsigned MOReg = MO.getReg();
570        if (MO.isUse())
571          UseRegs.push_back(MOReg);
572        if (MO.isDef())
573          DefRegs.push_back(MOReg);
574      }
575
576      // Process all uses.
577      for (unsigned i = 0, e = UseRegs.size(); i != e; ++i) {
578        unsigned MOReg = UseRegs[i];
579        if (TargetRegisterInfo::isVirtualRegister(MOReg))
580          HandleVirtRegUse(MOReg, MBB, MI);
581        else if (!ReservedRegisters[MOReg])
582          HandlePhysRegUse(MOReg, MI);
583      }
584
585      // Process all defs.
586      for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) {
587        unsigned MOReg = DefRegs[i];
588        if (TargetRegisterInfo::isVirtualRegister(MOReg))
589          HandleVirtRegDef(MOReg, MI);
590        else if (!ReservedRegisters[MOReg])
591          HandlePhysRegDef(MOReg, MI);
592      }
593    }
594
595    // Handle any virtual assignments from PHI nodes which might be at the
596    // bottom of this basic block.  We check all of our successor blocks to see
597    // if they have PHI nodes, and if so, we simulate an assignment at the end
598    // of the current block.
599    if (!PHIVarInfo[MBB->getNumber()].empty()) {
600      SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
601
602      for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(),
603             E = VarInfoVec.end(); I != E; ++I)
604        // Mark it alive only in the block we are representing.
605        MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
606                                MBB);
607    }
608
609    // Finally, if the last instruction in the block is a return, make sure to
610    // mark it as using all of the live-out values in the function.
611    if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
612      MachineInstr *Ret = &MBB->back();
613
614      for (MachineRegisterInfo::liveout_iterator
615           I = MF->getRegInfo().liveout_begin(),
616           E = MF->getRegInfo().liveout_end(); I != E; ++I) {
617        assert(TargetRegisterInfo::isPhysicalRegister(*I) &&
618               "Cannot have a live-out virtual register!");
619        HandlePhysRegUse(*I, Ret);
620
621        // Add live-out registers as implicit uses.
622        if (!Ret->readsRegister(*I))
623          Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
624      }
625    }
626
627    // Loop over PhysRegDef / PhysRegUse, killing any registers that are
628    // available at the end of the basic block.
629    for (unsigned i = 0; i != NumRegs; ++i)
630      if (PhysRegDef[i] || PhysRegUse[i])
631        HandlePhysRegDef(i, 0);
632
633    std::fill(PhysRegDef,  PhysRegDef  + NumRegs, (MachineInstr*)0);
634    std::fill(PhysRegUse,  PhysRegUse  + NumRegs, (MachineInstr*)0);
635  }
636
637  // Convert and transfer the dead / killed information we have gathered into
638  // VirtRegInfo onto MI's.
639  for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i)
640    for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j)
641      if (VirtRegInfo[i].Kills[j] ==
642          MRI->getVRegDef(i + TargetRegisterInfo::FirstVirtualRegister))
643        VirtRegInfo[i]
644          .Kills[j]->addRegisterDead(i +
645                                     TargetRegisterInfo::FirstVirtualRegister,
646                                     TRI);
647      else
648        VirtRegInfo[i]
649          .Kills[j]->addRegisterKilled(i +
650                                       TargetRegisterInfo::FirstVirtualRegister,
651                                       TRI);
652
653  // Check to make sure there are no unreachable blocks in the MC CFG for the
654  // function.  If so, it is due to a bug in the instruction selector or some
655  // other part of the code generator if this happens.
656#ifndef NDEBUG
657  for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i)
658    assert(Visited.count(&*i) != 0 && "unreachable basic block found");
659#endif
660
661  delete[] PhysRegDef;
662  delete[] PhysRegUse;
663  delete[] PHIVarInfo;
664
665  return false;
666}
667
668/// replaceKillInstruction - Update register kill info by replacing a kill
669/// instruction with a new one.
670void LiveVariables::replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
671                                           MachineInstr *NewMI) {
672  VarInfo &VI = getVarInfo(Reg);
673  std::replace(VI.Kills.begin(), VI.Kills.end(), OldMI, NewMI);
674}
675
676/// removeVirtualRegistersKilled - Remove all killed info for the specified
677/// instruction.
678void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) {
679  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
680    MachineOperand &MO = MI->getOperand(i);
681    if (MO.isReg() && MO.isKill()) {
682      MO.setIsKill(false);
683      unsigned Reg = MO.getReg();
684      if (TargetRegisterInfo::isVirtualRegister(Reg)) {
685        bool removed = getVarInfo(Reg).removeKill(MI);
686        assert(removed && "kill not in register's VarInfo?");
687        removed = true;
688      }
689    }
690  }
691}
692
693/// analyzePHINodes - Gather information about the PHI nodes in here. In
694/// particular, we want to map the variable information of a virtual register
695/// which is used in a PHI node. We map that to the BB the vreg is coming from.
696///
697void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
698  for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
699       I != E; ++I)
700    for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
701         BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
702      for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
703        PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
704          .push_back(BBI->getOperand(i).getReg());
705}
706