LiveVariables.cpp revision 6d6d352ed9bf69f06d8084b76042d7e9b3980cb5
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the LiveVariable analysis pass. For each machine 11// instruction in the function, this pass calculates the set of registers that 12// are immediately dead after the instruction (i.e., the instruction calculates 13// the value, but it is never used) and the set of registers that are used by 14// the instruction, but are never used after the instruction (i.e., they are 15// killed). 16// 17// This class computes live variables using are sparse implementation based on 18// the machine code SSA form. This class computes live variable information for 19// each virtual and _register allocatable_ physical register in a function. It 20// uses the dominance properties of SSA form to efficiently compute live 21// variables for virtual registers, and assumes that physical registers are only 22// live within a single basic block (allowing it to do a single local analysis 23// to resolve physical register lifetimes in each basic block). If a physical 24// register is not register allocatable, it is not tracked. This is useful for 25// things like the stack pointer and condition codes. 26// 27//===----------------------------------------------------------------------===// 28 29#include "llvm/CodeGen/LiveVariables.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/Target/MRegisterInfo.h" 32#include "llvm/Target/TargetInstrInfo.h" 33#include "llvm/Target/TargetMachine.h" 34#include "llvm/ADT/DepthFirstIterator.h" 35#include "llvm/ADT/SmallPtrSet.h" 36#include "llvm/ADT/STLExtras.h" 37#include "llvm/Config/alloca.h" 38#include <algorithm> 39using namespace llvm; 40 41char LiveVariables::ID = 0; 42static RegisterPass<LiveVariables> X("livevars", "Live Variable Analysis"); 43 44void LiveVariables::VarInfo::dump() const { 45 cerr << "Register Defined by: "; 46 if (DefInst) 47 cerr << *DefInst; 48 else 49 cerr << "<null>\n"; 50 cerr << " Alive in blocks: "; 51 for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i) 52 if (AliveBlocks[i]) cerr << i << ", "; 53 cerr << "\n Killed by:"; 54 if (Kills.empty()) 55 cerr << " No instructions.\n"; 56 else { 57 for (unsigned i = 0, e = Kills.size(); i != e; ++i) 58 cerr << "\n #" << i << ": " << *Kills[i]; 59 cerr << "\n"; 60 } 61} 62 63LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 64 assert(MRegisterInfo::isVirtualRegister(RegIdx) && 65 "getVarInfo: not a virtual register!"); 66 RegIdx -= MRegisterInfo::FirstVirtualRegister; 67 if (RegIdx >= VirtRegInfo.size()) { 68 if (RegIdx >= 2*VirtRegInfo.size()) 69 VirtRegInfo.resize(RegIdx*2); 70 else 71 VirtRegInfo.resize(2*VirtRegInfo.size()); 72 } 73 VarInfo &VI = VirtRegInfo[RegIdx]; 74 VI.AliveBlocks.resize(MF->getNumBlockIDs()); 75 return VI; 76} 77 78bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { 79 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 80 MachineOperand &MO = MI->getOperand(i); 81 if (MO.isReg() && MO.isKill()) { 82 if ((MO.getReg() == Reg) || 83 (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 84 MRegisterInfo::isPhysicalRegister(Reg) && 85 RegInfo->isSubRegister(MO.getReg(), Reg))) 86 return true; 87 } 88 } 89 return false; 90} 91 92bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { 93 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 94 MachineOperand &MO = MI->getOperand(i); 95 if (MO.isReg() && MO.isDead()) { 96 if ((MO.getReg() == Reg) || 97 (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 98 MRegisterInfo::isPhysicalRegister(Reg) && 99 RegInfo->isSubRegister(MO.getReg(), Reg))) 100 return true; 101 } 102 } 103 return false; 104} 105 106bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { 107 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 108 MachineOperand &MO = MI->getOperand(i); 109 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) 110 return true; 111 } 112 return false; 113} 114 115void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 116 MachineBasicBlock *MBB, 117 std::vector<MachineBasicBlock*> &WorkList) { 118 unsigned BBNum = MBB->getNumber(); 119 120 // Check to see if this basic block is one of the killing blocks. If so, 121 // remove it... 122 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 123 if (VRInfo.Kills[i]->getParent() == MBB) { 124 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 125 break; 126 } 127 128 if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion 129 130 if (VRInfo.AliveBlocks[BBNum]) 131 return; // We already know the block is live 132 133 // Mark the variable known alive in this bb 134 VRInfo.AliveBlocks[BBNum] = true; 135 136 for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(), 137 E = MBB->pred_rend(); PI != E; ++PI) 138 WorkList.push_back(*PI); 139} 140 141void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 142 MachineBasicBlock *MBB) { 143 std::vector<MachineBasicBlock*> WorkList; 144 MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList); 145 while (!WorkList.empty()) { 146 MachineBasicBlock *Pred = WorkList.back(); 147 WorkList.pop_back(); 148 MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList); 149 } 150} 151 152 153void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, 154 MachineInstr *MI) { 155 assert(VRInfo.DefInst && "Register use before def!"); 156 157 VRInfo.NumUses++; 158 159 // Check to see if this basic block is already a kill block... 160 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { 161 // Yes, this register is killed in this basic block already. Increase the 162 // live range by updating the kill instruction. 163 VRInfo.Kills.back() = MI; 164 return; 165 } 166 167#ifndef NDEBUG 168 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 169 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!"); 170#endif 171 172 assert(MBB != VRInfo.DefInst->getParent() && 173 "Should have kill for defblock!"); 174 175 // Add a new kill entry for this basic block. 176 // If this virtual register is already marked as alive in this basic block, 177 // that means it is alive in at least one of the successor block, it's not 178 // a kill. 179 if (!VRInfo.AliveBlocks[MBB->getNumber()]) 180 VRInfo.Kills.push_back(MI); 181 182 // Update all dominating blocks to mark them known live. 183 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), 184 E = MBB->pred_end(); PI != E; ++PI) 185 MarkVirtRegAliveInBlock(VRInfo, *PI); 186} 187 188bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI, 189 bool AddIfNotFound) { 190 bool Found = false; 191 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 192 MachineOperand &MO = MI->getOperand(i); 193 if (MO.isReg() && MO.isUse()) { 194 unsigned Reg = MO.getReg(); 195 if (!Reg) 196 continue; 197 if (Reg == IncomingReg) { 198 MO.setIsKill(); 199 Found = true; 200 break; 201 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 202 MRegisterInfo::isPhysicalRegister(IncomingReg) && 203 RegInfo->isSuperRegister(IncomingReg, Reg) && 204 MO.isKill()) 205 // A super-register kill already exists. 206 return true; 207 } 208 } 209 210 // If not found, this means an alias of one of the operand is killed. Add a 211 // new implicit operand if required. 212 if (!Found && AddIfNotFound) { 213 MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); 214 return true; 215 } 216 return Found; 217} 218 219bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI, 220 bool AddIfNotFound) { 221 bool Found = false; 222 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 223 MachineOperand &MO = MI->getOperand(i); 224 if (MO.isReg() && MO.isDef()) { 225 unsigned Reg = MO.getReg(); 226 if (!Reg) 227 continue; 228 if (Reg == IncomingReg) { 229 MO.setIsDead(); 230 Found = true; 231 break; 232 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 233 MRegisterInfo::isPhysicalRegister(IncomingReg) && 234 RegInfo->isSuperRegister(IncomingReg, Reg) && 235 MO.isDead()) 236 // There exists a super-register that's marked dead. 237 return true; 238 } 239 } 240 241 // If not found, this means an alias of one of the operand is dead. Add a 242 // new implicit operand. 243 if (!Found && AddIfNotFound) { 244 MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/, 245 true/*IsDead*/); 246 return true; 247 } 248 return Found; 249} 250 251void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 252 // Turn previous partial def's into read/mod/write. 253 for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) { 254 MachineInstr *Def = PhysRegPartDef[Reg][i]; 255 // First one is just a def. This means the use is reading some undef bits. 256 if (i != 0) 257 Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); 258 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); 259 } 260 PhysRegPartDef[Reg].clear(); 261 262 // There was an earlier def of a super-register. Add implicit def to that MI. 263 // A: EAX = ... 264 // B: = AX 265 // Add implicit def to A. 266 if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] && 267 !PhysRegUsed[Reg]) { 268 MachineInstr *Def = PhysRegInfo[Reg]; 269 if (!Def->findRegisterDefOperand(Reg)) 270 Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); 271 } 272 273 // There is a now a proper use, forget about the last partial use. 274 PhysRegPartUse[Reg] = NULL; 275 PhysRegInfo[Reg] = MI; 276 PhysRegUsed[Reg] = true; 277 278 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 279 unsigned SubReg = *SubRegs; ++SubRegs) { 280 PhysRegInfo[SubReg] = MI; 281 PhysRegUsed[SubReg] = true; 282 } 283 284 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); 285 unsigned SuperReg = *SuperRegs; ++SuperRegs) { 286 // Remember the partial use of this superreg if it was previously defined. 287 bool HasPrevDef = PhysRegInfo[SuperReg] != NULL; 288 if (!HasPrevDef) { 289 for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg); 290 unsigned SSReg = *SSRegs; ++SSRegs) { 291 if (PhysRegInfo[SSReg] != NULL) { 292 HasPrevDef = true; 293 break; 294 } 295 } 296 } 297 if (HasPrevDef) { 298 PhysRegInfo[SuperReg] = MI; 299 PhysRegPartUse[SuperReg] = MI; 300 } 301 } 302} 303 304bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI, 305 SmallSet<unsigned, 4> &SubKills) { 306 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 307 unsigned SubReg = *SubRegs; ++SubRegs) { 308 MachineInstr *LastRef = PhysRegInfo[SubReg]; 309 if (LastRef != RefMI) 310 SubKills.insert(SubReg); 311 else if (!HandlePhysRegKill(SubReg, RefMI, SubKills)) 312 SubKills.insert(SubReg); 313 } 314 315 if (*RegInfo->getImmediateSubRegisters(Reg) == 0) { 316 // No sub-registers, just check if reg is killed by RefMI. 317 if (PhysRegInfo[Reg] == RefMI) 318 return true; 319 } else if (SubKills.empty()) 320 // None of the sub-registers are killed elsewhere... 321 return true; 322 return false; 323} 324 325void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI, 326 SmallSet<unsigned, 4> &SubKills) { 327 if (SubKills.count(Reg) == 0) 328 addRegisterKilled(Reg, MI, true); 329 else { 330 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 331 unsigned SubReg = *SubRegs; ++SubRegs) 332 addRegisterKills(SubReg, MI, SubKills); 333 } 334} 335 336bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) { 337 SmallSet<unsigned, 4> SubKills; 338 if (HandlePhysRegKill(Reg, RefMI, SubKills)) { 339 addRegisterKilled(Reg, RefMI); 340 return true; 341 } else { 342 // Some sub-registers are killed by another MI. 343 for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); 344 unsigned SubReg = *SubRegs; ++SubRegs) 345 addRegisterKills(SubReg, RefMI, SubKills); 346 return false; 347 } 348} 349 350void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 351 // Does this kill a previous version of this register? 352 if (MachineInstr *LastRef = PhysRegInfo[Reg]) { 353 if (PhysRegUsed[Reg]) { 354 if (!HandlePhysRegKill(Reg, LastRef)) { 355 if (PhysRegPartUse[Reg]) 356 addRegisterKilled(Reg, PhysRegPartUse[Reg], true); 357 } 358 } else if (PhysRegPartUse[Reg]) 359 // Add implicit use / kill to last partial use. 360 addRegisterKilled(Reg, PhysRegPartUse[Reg], true); 361 else 362 addRegisterDead(Reg, LastRef); 363 } 364 365 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 366 unsigned SubReg = *SubRegs; ++SubRegs) { 367 if (MachineInstr *LastRef = PhysRegInfo[SubReg]) { 368 if (PhysRegUsed[SubReg]) { 369 if (!HandlePhysRegKill(SubReg, LastRef)) { 370 if (PhysRegPartUse[SubReg]) 371 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true); 372 } 373 } else if (PhysRegPartUse[SubReg]) 374 // Add implicit use / kill to last use of a sub-register. 375 addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true); 376 else if (LastRef != MI) 377 // This must be a def of the subreg on the same MI. 378 addRegisterDead(SubReg, LastRef); 379 } 380 } 381 382 if (MI) { 383 for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); 384 unsigned SuperReg = *SuperRegs; ++SuperRegs) { 385 if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) { 386 // The larger register is previously defined. Now a smaller part is 387 // being re-defined. Treat it as read/mod/write. 388 // EAX = 389 // AX = EAX<imp-use,kill>, EAX<imp-def> 390 MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); 391 MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/); 392 PhysRegInfo[SuperReg] = MI; 393 PhysRegUsed[SuperReg] = false; 394 PhysRegPartUse[SuperReg] = NULL; 395 } else { 396 // Remember this partial def. 397 PhysRegPartDef[SuperReg].push_back(MI); 398 } 399 } 400 401 PhysRegInfo[Reg] = MI; 402 PhysRegUsed[Reg] = false; 403 PhysRegPartDef[Reg].clear(); 404 PhysRegPartUse[Reg] = NULL; 405 for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); 406 unsigned SubReg = *SubRegs; ++SubRegs) { 407 PhysRegInfo[SubReg] = MI; 408 PhysRegUsed[SubReg] = false; 409 PhysRegPartDef[SubReg].clear(); 410 PhysRegPartUse[SubReg] = NULL; 411 } 412 } 413} 414 415bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { 416 MF = &mf; 417 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 418 RegInfo = MF->getTarget().getRegisterInfo(); 419 assert(RegInfo && "Target doesn't have register information?"); 420 421 ReservedRegisters = RegInfo->getReservedRegs(mf); 422 423 unsigned NumRegs = RegInfo->getNumRegs(); 424 PhysRegInfo = new MachineInstr*[NumRegs]; 425 PhysRegUsed = new bool[NumRegs]; 426 PhysRegPartUse = new MachineInstr*[NumRegs]; 427 PhysRegPartDef = new SmallVector<MachineInstr*,4>[NumRegs]; 428 PHIVarInfo = new SmallVector<unsigned, 4>[MF->getNumBlockIDs()]; 429 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); 430 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); 431 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); 432 433 /// Get some space for a respectable number of registers... 434 VirtRegInfo.resize(64); 435 436 analyzePHINodes(mf); 437 438 // Calculate live variable information in depth first order on the CFG of the 439 // function. This guarantees that we will see the definition of a virtual 440 // register before its uses due to dominance properties of SSA (except for PHI 441 // nodes, which are treated as a special case). 442 // 443 MachineBasicBlock *Entry = MF->begin(); 444 SmallPtrSet<MachineBasicBlock*,16> Visited; 445 for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> > 446 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); 447 DFI != E; ++DFI) { 448 MachineBasicBlock *MBB = *DFI; 449 450 // Mark live-in registers as live-in. 451 for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(), 452 EE = MBB->livein_end(); II != EE; ++II) { 453 assert(MRegisterInfo::isPhysicalRegister(*II) && 454 "Cannot have a live-in virtual register!"); 455 HandlePhysRegDef(*II, 0); 456 } 457 458 // Loop over all of the instructions, processing them. 459 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 460 I != E; ++I) { 461 MachineInstr *MI = I; 462 463 // Process all of the operands of the instruction... 464 unsigned NumOperandsToProcess = MI->getNumOperands(); 465 466 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 467 // of the uses. They will be handled in other basic blocks. 468 if (MI->getOpcode() == TargetInstrInfo::PHI) 469 NumOperandsToProcess = 1; 470 471 // Process all uses... 472 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 473 MachineOperand &MO = MI->getOperand(i); 474 if (MO.isRegister() && MO.isUse() && MO.getReg()) { 475 if (MRegisterInfo::isVirtualRegister(MO.getReg())){ 476 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); 477 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 478 !ReservedRegisters[MO.getReg()]) { 479 HandlePhysRegUse(MO.getReg(), MI); 480 } 481 } 482 } 483 484 // Process all defs... 485 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 486 MachineOperand &MO = MI->getOperand(i); 487 if (MO.isRegister() && MO.isDef() && MO.getReg()) { 488 if (MRegisterInfo::isVirtualRegister(MO.getReg())) { 489 VarInfo &VRInfo = getVarInfo(MO.getReg()); 490 491 assert(VRInfo.DefInst == 0 && "Variable multiply defined!"); 492 VRInfo.DefInst = MI; 493 // Defaults to dead 494 VRInfo.Kills.push_back(MI); 495 } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && 496 !ReservedRegisters[MO.getReg()]) { 497 HandlePhysRegDef(MO.getReg(), MI); 498 } 499 } 500 } 501 } 502 503 // Handle any virtual assignments from PHI nodes which might be at the 504 // bottom of this basic block. We check all of our successor blocks to see 505 // if they have PHI nodes, and if so, we simulate an assignment at the end 506 // of the current block. 507 if (!PHIVarInfo[MBB->getNumber()].empty()) { 508 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()]; 509 510 for (SmallVector<unsigned, 4>::iterator I = VarInfoVec.begin(), 511 E = VarInfoVec.end(); I != E; ++I) { 512 VarInfo& VRInfo = getVarInfo(*I); 513 assert(VRInfo.DefInst && "Register use before def (or no def)!"); 514 515 // Only mark it alive only in the block we are representing. 516 MarkVirtRegAliveInBlock(VRInfo, MBB); 517 } 518 } 519 520 // Finally, if the last instruction in the block is a return, make sure to mark 521 // it as using all of the live-out values in the function. 522 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { 523 MachineInstr *Ret = &MBB->back(); 524 for (MachineFunction::liveout_iterator I = MF->liveout_begin(), 525 E = MF->liveout_end(); I != E; ++I) { 526 assert(MRegisterInfo::isPhysicalRegister(*I) && 527 "Cannot have a live-in virtual register!"); 528 HandlePhysRegUse(*I, Ret); 529 // Add live-out registers as implicit uses. 530 if (Ret->findRegisterUseOperandIdx(*I) == -1) 531 Ret->addRegOperand(*I, false, true); 532 } 533 } 534 535 // Loop over PhysRegInfo, killing any registers that are available at the 536 // end of the basic block. This also resets the PhysRegInfo map. 537 for (unsigned i = 0; i != NumRegs; ++i) 538 if (PhysRegInfo[i]) 539 HandlePhysRegDef(i, 0); 540 541 // Clear some states between BB's. These are purely local information. 542 for (unsigned i = 0; i != NumRegs; ++i) 543 PhysRegPartDef[i].clear(); 544 std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); 545 std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); 546 std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); 547 } 548 549 // Convert and transfer the dead / killed information we have gathered into 550 // VirtRegInfo onto MI's. 551 // 552 for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) 553 for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) { 554 if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst) 555 addRegisterDead(i + MRegisterInfo::FirstVirtualRegister, 556 VirtRegInfo[i].Kills[j]); 557 else 558 addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister, 559 VirtRegInfo[i].Kills[j]); 560 } 561 562 // Check to make sure there are no unreachable blocks in the MC CFG for the 563 // function. If so, it is due to a bug in the instruction selector or some 564 // other part of the code generator if this happens. 565#ifndef NDEBUG 566 for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i) 567 assert(Visited.count(&*i) != 0 && "unreachable basic block found"); 568#endif 569 570 delete[] PhysRegInfo; 571 delete[] PhysRegUsed; 572 delete[] PhysRegPartUse; 573 delete[] PhysRegPartDef; 574 delete[] PHIVarInfo; 575 576 return false; 577} 578 579/// instructionChanged - When the address of an instruction changes, this 580/// method should be called so that live variables can update its internal 581/// data structures. This removes the records for OldMI, transfering them to 582/// the records for NewMI. 583void LiveVariables::instructionChanged(MachineInstr *OldMI, 584 MachineInstr *NewMI) { 585 // If the instruction defines any virtual registers, update the VarInfo, 586 // kill and dead information for the instruction. 587 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { 588 MachineOperand &MO = OldMI->getOperand(i); 589 if (MO.isRegister() && MO.getReg() && 590 MRegisterInfo::isVirtualRegister(MO.getReg())) { 591 unsigned Reg = MO.getReg(); 592 VarInfo &VI = getVarInfo(Reg); 593 if (MO.isDef()) { 594 if (MO.isDead()) { 595 MO.unsetIsDead(); 596 addVirtualRegisterDead(Reg, NewMI); 597 } 598 // Update the defining instruction. 599 if (VI.DefInst == OldMI) 600 VI.DefInst = NewMI; 601 } 602 if (MO.isKill()) { 603 MO.unsetIsKill(); 604 addVirtualRegisterKilled(Reg, NewMI); 605 } 606 // If this is a kill of the value, update the VI kills list. 607 if (VI.removeKill(OldMI)) 608 VI.Kills.push_back(NewMI); // Yes, there was a kill of it 609 } 610 } 611} 612 613/// removeVirtualRegistersKilled - Remove all killed info for the specified 614/// instruction. 615void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { 616 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 617 MachineOperand &MO = MI->getOperand(i); 618 if (MO.isReg() && MO.isKill()) { 619 MO.unsetIsKill(); 620 unsigned Reg = MO.getReg(); 621 if (MRegisterInfo::isVirtualRegister(Reg)) { 622 bool removed = getVarInfo(Reg).removeKill(MI); 623 assert(removed && "kill not in register's VarInfo?"); 624 } 625 } 626 } 627} 628 629/// removeVirtualRegistersDead - Remove all of the dead registers for the 630/// specified instruction from the live variable information. 631void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { 632 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 633 MachineOperand &MO = MI->getOperand(i); 634 if (MO.isReg() && MO.isDead()) { 635 MO.unsetIsDead(); 636 unsigned Reg = MO.getReg(); 637 if (MRegisterInfo::isVirtualRegister(Reg)) { 638 bool removed = getVarInfo(Reg).removeKill(MI); 639 assert(removed && "kill not in register's VarInfo?"); 640 } 641 } 642 } 643} 644 645/// analyzePHINodes - Gather information about the PHI nodes in here. In 646/// particular, we want to map the variable information of a virtual 647/// register which is used in a PHI node. We map that to the BB the vreg is 648/// coming from. 649/// 650void LiveVariables::analyzePHINodes(const MachineFunction& Fn) { 651 for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end(); 652 I != E; ++I) 653 for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); 654 BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) 655 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) 656 PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()]. 657 push_back(BBI->getOperand(i).getReg()); 658} 659