LiveVariables.cpp revision 73ff5120eb8b8c0ccbfed8a17f1024c67a75f319
1//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===// 2// 3// This file implements the LiveVariable analysis pass. For each machine 4// instruction in the function, this pass calculates the set of registers that 5// are immediately dead after the instruction (i.e., the instruction calculates 6// the value, but it is never used) and the set of registers that are used by 7// the instruction, but are never used after the instruction (i.e., they are 8// killed). 9// 10// This class computes live variables using are sparse implementation based on 11// the machine code SSA form. This class computes live variable information for 12// each virtual and _register allocatable_ physical register in a function. It 13// uses the dominance properties of SSA form to efficiently compute live 14// variables for virtual registers, and assumes that physical registers are only 15// live within a single basic block (allowing it to do a single local analysis 16// to resolve physical register lifetimes in each basic block). If a physical 17// register is not register allocatable, it is not tracked. This is useful for 18// things like the stack pointer and condition codes. 19// 20//===----------------------------------------------------------------------===// 21 22#include "llvm/CodeGen/LiveVariables.h" 23#include "llvm/CodeGen/MachineInstr.h" 24#include "llvm/Target/TargetInstrInfo.h" 25#include "llvm/Target/TargetMachine.h" 26#include "llvm/Support/CFG.h" 27#include "Support/DepthFirstIterator.h" 28 29static RegisterAnalysis<LiveVariables> X("livevars", "Live Variable Analysis"); 30 31const std::pair<MachineBasicBlock*, unsigned> & 32LiveVariables::getMachineBasicBlockInfo(MachineBasicBlock *MBB) const{ 33 return BBMap.find(MBB->getBasicBlock())->second; 34} 35 36LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { 37 assert(RegIdx >= MRegisterInfo::FirstVirtualRegister && 38 "getVarInfo: not a virtual register!"); 39 RegIdx -= MRegisterInfo::FirstVirtualRegister; 40 if (RegIdx >= VirtRegInfo.size()) { 41 if (RegIdx >= 2*VirtRegInfo.size()) 42 VirtRegInfo.resize(RegIdx*2); 43 else 44 VirtRegInfo.resize(2*VirtRegInfo.size()); 45 } 46 return VirtRegInfo[RegIdx]; 47} 48 49 50 51void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, 52 const BasicBlock *BB) { 53 const std::pair<MachineBasicBlock*,unsigned> &Info = BBMap.find(BB)->second; 54 MachineBasicBlock *MBB = Info.first; 55 unsigned BBNum = Info.second; 56 57 // Check to see if this basic block is one of the killing blocks. If so, 58 // remove it... 59 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 60 if (VRInfo.Kills[i].first == MBB) { 61 VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry 62 break; 63 } 64 65 if (MBB == VRInfo.DefBlock) return; // Terminate recursion 66 67 if (VRInfo.AliveBlocks.size() <= BBNum) 68 VRInfo.AliveBlocks.resize(BBNum+1); // Make space... 69 70 if (VRInfo.AliveBlocks[BBNum]) 71 return; // We already know the block is live 72 73 // Mark the variable known alive in this bb 74 VRInfo.AliveBlocks[BBNum] = true; 75 76 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) 77 MarkVirtRegAliveInBlock(VRInfo, *PI); 78} 79 80void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, 81 MachineInstr *MI) { 82 // Check to see if this basic block is already a kill block... 83 if (!VRInfo.Kills.empty() && VRInfo.Kills.back().first == MBB) { 84 // Yes, this register is killed in this basic block already. Increase the 85 // live range by updating the kill instruction. 86 VRInfo.Kills.back().second = MI; 87 return; 88 } 89 90#ifndef NDEBUG 91 for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i) 92 assert(VRInfo.Kills[i].first != MBB && "entry should be at end!"); 93#endif 94 95 assert(MBB != VRInfo.DefBlock && "Should have kill for defblock!"); 96 97 // Add a new kill entry for this basic block. 98 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); 99 100 // Update all dominating blocks to mark them known live. 101 const BasicBlock *BB = MBB->getBasicBlock(); 102 for (pred_const_iterator PI = pred_begin(BB), E = pred_end(BB); 103 PI != E; ++PI) 104 MarkVirtRegAliveInBlock(VRInfo, *PI); 105} 106 107void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { 108 if (PhysRegInfo[Reg]) { 109 PhysRegInfo[Reg] = MI; 110 PhysRegUsed[Reg] = true; 111 } else { 112 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); 113 *AliasSet; ++AliasSet) { 114 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) { 115 PhysRegInfo[*AliasSet] = MI; 116 PhysRegUsed[*AliasSet] = true; 117 } 118 } 119 } 120} 121 122void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { 123 // Does this kill a previous version of this register? 124 if (MachineInstr *LastUse = PhysRegInfo[Reg]) { 125 if (PhysRegUsed[Reg]) 126 RegistersKilled.insert(std::make_pair(LastUse, Reg)); 127 else 128 RegistersDead.insert(std::make_pair(LastUse, Reg)); 129 } else { 130 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); 131 *AliasSet; ++AliasSet) { 132 if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) { 133 if (PhysRegUsed[*AliasSet]) 134 RegistersKilled.insert(std::make_pair(LastUse, *AliasSet)); 135 else 136 RegistersDead.insert(std::make_pair(LastUse, *AliasSet)); 137 PhysRegInfo[*AliasSet] = 0; // Kill the aliased register 138 } 139 } 140 } 141 PhysRegInfo[Reg] = MI; 142 PhysRegUsed[Reg] = false; 143} 144 145bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { 146 // First time though, initialize AllocatablePhysicalRegisters for the target 147 if (AllocatablePhysicalRegisters.empty()) { 148 const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); 149 assert(&MRI && "Target doesn't have register information?"); 150 151 // Make space, initializing to false... 152 AllocatablePhysicalRegisters.resize(MRegisterInfo::FirstVirtualRegister); 153 154 // Loop over all of the register classes... 155 for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(), 156 E = MRI.regclass_end(); RCI != E; ++RCI) 157 // Loop over all of the allocatable registers in the function... 158 for (TargetRegisterClass::iterator I = (*RCI)->allocation_order_begin(MF), 159 E = (*RCI)->allocation_order_end(MF); I != E; ++I) 160 AllocatablePhysicalRegisters[*I] = true; // The reg is allocatable! 161 } 162 163 // Build BBMap... 164 unsigned BBNum = 0; 165 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 166 BBMap[I->getBasicBlock()] = std::make_pair(I, BBNum++); 167 168 // PhysRegInfo - Keep track of which instruction was the last use of a 169 // physical register. This is a purely local property, because all physical 170 // register references as presumed dead across basic blocks. 171 // 172 MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister]; 173 bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister]; 174 std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister, 175 (MachineInstr*)0); 176 PhysRegInfo = PhysRegInfoA; 177 PhysRegUsed = PhysRegUsedA; 178 179 const TargetInstrInfo &TII = MF.getTarget().getInstrInfo(); 180 RegInfo = MF.getTarget().getRegisterInfo(); 181 182 /// Get some space for a respectable number of registers... 183 VirtRegInfo.resize(64); 184 185 // Calculate live variable information in depth first order on the CFG of the 186 // function. This guarantees that we will see the definition of a virtual 187 // register before its uses due to dominance properties of SSA (except for PHI 188 // nodes, which are treated as a special case). 189 // 190 const BasicBlock *Entry = MF.getFunction()->begin(); 191 for (df_iterator<const BasicBlock*> DFI = df_begin(Entry), E = df_end(Entry); 192 DFI != E; ++DFI) { 193 const BasicBlock *BB = *DFI; 194 std::pair<MachineBasicBlock*, unsigned> &BBRec = BBMap.find(BB)->second; 195 MachineBasicBlock *MBB = BBRec.first; 196 unsigned BBNum = BBRec.second; 197 198 // Loop over all of the instructions, processing them. 199 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 200 I != E; ++I) { 201 MachineInstr *MI = *I; 202 const TargetInstrDescriptor &MID = TII.get(MI->getOpcode()); 203 204 // Process all of the operands of the instruction... 205 unsigned NumOperandsToProcess = MI->getNumOperands(); 206 207 // Unless it is a PHI node. In this case, ONLY process the DEF, not any 208 // of the uses. They will be handled in other basic blocks. 209 if (MI->getOpcode() == TargetInstrInfo::PHI) 210 NumOperandsToProcess = 1; 211 212 // Loop over implicit uses, using them. 213 for (const unsigned *ImplicitUses = MID.ImplicitUses; 214 *ImplicitUses; ++ImplicitUses) 215 HandlePhysRegUse(*ImplicitUses, MI); 216 217 // Process all explicit uses... 218 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 219 MachineOperand &MO = MI->getOperand(i); 220 if (MO.opIsUse() || MO.opIsDefAndUse()) { 221 if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) { 222 HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); 223 } else if (MO.isPhysicalRegister() && 224 AllocatablePhysicalRegisters[MO.getReg()]) { 225 HandlePhysRegUse(MO.getReg(), MI); 226 } 227 } 228 } 229 230 // Loop over implicit defs, defining them. 231 if (const unsigned *ImplicitDefs = MID.ImplicitDefs) 232 for (unsigned i = 0; ImplicitDefs[i]; ++i) 233 HandlePhysRegDef(ImplicitDefs[i], MI); 234 235 // Process all explicit defs... 236 for (unsigned i = 0; i != NumOperandsToProcess; ++i) { 237 MachineOperand &MO = MI->getOperand(i); 238 if (MO.opIsDefOnly() || MO.opIsDefAndUse()) { 239 if (MO.isVirtualRegister()) { 240 VarInfo &VRInfo = getVarInfo(MO.getReg()); 241 242 assert(VRInfo.DefBlock == 0 && "Variable multiply defined!"); 243 VRInfo.DefBlock = MBB; // Created here... 244 VRInfo.DefInst = MI; 245 VRInfo.Kills.push_back(std::make_pair(MBB, MI)); // Defaults to dead 246 } else if (MO.isPhysicalRegister() && 247 AllocatablePhysicalRegisters[MO.getReg()]) { 248 HandlePhysRegDef(MO.getReg(), MI); 249 } 250 } 251 } 252 } 253 254 // Handle any virtual assignments from PHI nodes which might be at the 255 // bottom of this basic block. We check all of our successor blocks to see 256 // if they have PHI nodes, and if so, we simulate an assignment at the end 257 // of the current block. 258 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); 259 SI != E; ++SI) { 260 MachineBasicBlock *Succ = BBMap.find(*SI)->second.first; 261 262 // PHI nodes are guaranteed to be at the top of the block... 263 for (MachineBasicBlock::iterator I = Succ->begin(), E = Succ->end(); 264 I != E && (*I)->getOpcode() == TargetInstrInfo::PHI; ++I) { 265 MachineInstr *MI = *I; 266 for (unsigned i = 1; ; i += 2) 267 if (MI->getOperand(i+1).getMachineBasicBlock() == MBB) { 268 MachineOperand &MO = MI->getOperand(i); 269 if (!MO.getVRegValueOrNull()) { 270 VarInfo &VRInfo = getVarInfo(MO.getReg()); 271 272 // Only mark it alive only in the block we are representing... 273 MarkVirtRegAliveInBlock(VRInfo, BB); 274 break; // Found the PHI entry for this block... 275 } 276 } 277 } 278 } 279 280 // Loop over PhysRegInfo, killing any registers that are available at the 281 // end of the basic block. This also resets the PhysRegInfo map. 282 for (unsigned i = 0, e = MRegisterInfo::FirstVirtualRegister; i != e; ++i) 283 if (PhysRegInfo[i]) 284 HandlePhysRegDef(i, 0); 285 } 286 287 // Convert the information we have gathered into VirtRegInfo and transform it 288 // into a form usable by RegistersKilled. 289 // 290 for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i) 291 for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) { 292 if (VirtRegInfo[i].Kills[j].second == VirtRegInfo[i].DefInst) 293 RegistersDead.insert(std::make_pair(VirtRegInfo[i].Kills[j].second, 294 i + MRegisterInfo::FirstVirtualRegister)); 295 296 else 297 RegistersKilled.insert(std::make_pair(VirtRegInfo[i].Kills[j].second, 298 i + MRegisterInfo::FirstVirtualRegister)); 299 } 300 301 return false; 302} 303