MachineInstr.cpp revision 10cb79b48430ea7679e83ae045aaeadea04a0cc5 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//===----------------------------------------------------------------------===//
4
5#include "llvm/CodeGen/MachineInstr.h"
6#include "llvm/CodeGen/MachineBasicBlock.h"
7#include "llvm/Value.h"
8#include "llvm/Target/TargetMachine.h"
9#include "llvm/Target/MachineInstrInfo.h"
10#include "llvm/Target/MRegisterInfo.h"
11using std::cerr;
12
13// Global variable holding an array of descriptors for machine instructions.
14// The actual object needs to be created separately for each target machine.
15// This variable is initialized and reset by class MachineInstrInfo.
16//
17// FIXME: This should be a property of the target so that more than one target
18// at a time can be active...
19//
20extern const MachineInstrDescriptor *TargetInstrDescriptors;
21
22// Constructor for instructions with fixed #operands (nearly all)
23MachineInstr::MachineInstr(MachineOpCode _opCode)
24  : opCode(_opCode),
25    operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()),
26    numImplicitRefs(0)
27{
28  assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
29}
30
31// Constructor for instructions with variable #operands
32MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned  numOperands)
33  : opCode(OpCode),
34    operands(numOperands, MachineOperand()),
35    numImplicitRefs(0)
36{
37}
38
39/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
40/// not a resize for them.  It is expected that if you use this that you call
41/// add* methods below to fill up the operands, instead of the Set methods.
42/// Eventually, the "resizing" ctors will be phased out.
43///
44MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
45                           bool XX, bool YY)
46  : opCode(Opcode),
47    numImplicitRefs(0)
48{
49  operands.reserve(numOperands);
50}
51
52/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
53/// MachineInstr is created and added to the end of the specified basic block.
54///
55MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
56                           unsigned numOperands)
57  : opCode(Opcode),
58    numImplicitRefs(0)
59{
60  assert(MBB && "Cannot use inserting ctor with null basic block!");
61  operands.reserve(numOperands);
62  MBB->push_back(this);  // Add instruction to end of basic block!
63}
64
65
66// OperandComplete - Return true if it's illegal to add a new operand
67bool MachineInstr::OperandsComplete() const
68{
69  int NumOperands = TargetInstrDescriptors[opCode].numOperands;
70  if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
71    return true;  // Broken!
72  return false;
73}
74
75
76//
77// Support for replacing opcode and operands of a MachineInstr in place.
78// This only resets the size of the operand vector and initializes it.
79// The new operands must be set explicitly later.
80//
81void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
82{
83  assert(getNumImplicitRefs() == 0 &&
84         "This is probably broken because implicit refs are going to be lost.");
85  opCode = Opcode;
86  operands.clear();
87  operands.resize(numOperands, MachineOperand());
88}
89
90void
91MachineInstr::SetMachineOperandVal(unsigned i,
92                                   MachineOperand::MachineOperandType opType,
93                                   Value* V,
94                                   bool isdef,
95                                   bool isDefAndUse)
96{
97  assert(i < operands.size());          // may be explicit or implicit op
98  operands[i].opType = opType;
99  operands[i].value = V;
100  operands[i].regNum = -1;
101
102  if (isDefAndUse)
103    operands[i].flags = MachineOperand::DEFUSEFLAG;
104  else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
105    operands[i].flags = MachineOperand::DEFFLAG;
106  else
107    operands[i].flags = 0;
108}
109
110void
111MachineInstr::SetMachineOperandConst(unsigned i,
112				MachineOperand::MachineOperandType operandType,
113                                     int64_t intValue)
114{
115  assert(i < getNumOperands());          // must be explicit op
116  assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
117         "immed. constant cannot be defined");
118
119  operands[i].opType = operandType;
120  operands[i].value = NULL;
121  operands[i].immedVal = intValue;
122  operands[i].regNum = -1;
123  operands[i].flags = 0;
124}
125
126void
127MachineInstr::SetMachineOperandReg(unsigned i,
128                                   int regNum,
129                                   bool isdef) {
130  assert(i < getNumOperands());          // must be explicit op
131
132  operands[i].opType = MachineOperand::MO_MachineRegister;
133  operands[i].value = NULL;
134  operands[i].regNum = regNum;
135
136  if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
137    operands[i].flags = MachineOperand::DEFFLAG;
138  else
139    operands[i].flags = 0;
140
141  insertUsedReg(regNum);
142}
143
144void
145MachineInstr::SetRegForOperand(unsigned i, int regNum)
146{
147  assert(i < getNumOperands());          // must be explicit op
148  operands[i].setRegForValue(regNum);
149  insertUsedReg(regNum);
150}
151
152
153// Subsitute all occurrences of Value* oldVal with newVal in all operands
154// and all implicit refs.  If defsOnly == true, substitute defs only.
155unsigned
156MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
157{
158  unsigned numSubst = 0;
159
160  // Subsitute operands
161  for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
162    if (*O == oldVal)
163      if (!defsOnly || O.isDef())
164        {
165          O.getMachineOperand().value = newVal;
166          ++numSubst;
167        }
168
169  // Subsitute implicit refs
170  for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
171    if (getImplicitRef(i) == oldVal)
172      if (!defsOnly || implicitRefIsDefined(i))
173        {
174          getImplicitOp(i).value = newVal;
175          ++numSubst;
176        }
177
178  return numSubst;
179}
180
181
182void
183MachineInstr::dump() const
184{
185  cerr << "  " << *this;
186}
187
188static inline std::ostream&
189OutputValue(std::ostream &os, const Value* val)
190{
191  os << "(val ";
192  if (val && val->hasName())
193    return os << val->getName() << ")";
194  else
195    return os << (void*) val << ")";              // print address only
196}
197
198static inline void OutputReg(std::ostream &os, unsigned RegNo,
199                             const MRegisterInfo *MRI = 0) {
200  if (MRI) {
201    if (RegNo < MRegisterInfo::FirstVirtualRegister)
202      os << "%" << MRI->get(RegNo).Name;
203    else
204      os << "%reg" << RegNo;
205  } else
206    os << "%mreg(" << RegNo << ")";
207}
208
209static void print(const MachineOperand &MO, std::ostream &OS,
210                  const TargetMachine &TM) {
211  const MRegisterInfo *MRI = TM.getRegisterInfo();
212  bool CloseParen = true;
213  if (MO.opHiBits32())
214    OS << "%lm(";
215  else if (MO.opLoBits32())
216    OS << "%lo(";
217  else if (MO.opHiBits64())
218    OS << "%hh(";
219  else if (MO.opLoBits64())
220    OS << "%hm(";
221  else
222    CloseParen = false;
223
224  switch (MO.getType()) {
225  case MachineOperand::MO_VirtualRegister:
226    if (MO.getVRegValue()) {
227      OS << "%reg";
228      OutputValue(OS, MO.getVRegValue());
229      if (MO.hasAllocatedReg())
230        OS << "==";
231    }
232    if (MO.hasAllocatedReg())
233      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
234    break;
235  case MachineOperand::MO_CCRegister:
236    OS << "%ccreg";
237    OutputValue(OS, MO.getVRegValue());
238    if (MO.hasAllocatedReg()) {
239      OS << "==";
240      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
241    }
242    break;
243  case MachineOperand::MO_MachineRegister:
244    OutputReg(OS, MO.getMachineRegNum(), MRI);
245    break;
246  case MachineOperand::MO_SignExtendedImmed:
247    OS << (long)MO.getImmedValue();
248    break;
249  case MachineOperand::MO_UnextendedImmed:
250    OS << (long)MO.getImmedValue();
251    break;
252  case MachineOperand::MO_PCRelativeDisp: {
253    const Value* opVal = MO.getVRegValue();
254    bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
255    OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
256    if (opVal->hasName())
257      OS << opVal->getName();
258    else
259      OS << (const void*) opVal;
260    OS << ")";
261    break;
262  }
263  case MachineOperand::MO_MachineBasicBlock:
264    OS << "bb<"
265       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
266       << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
267    break;
268  case MachineOperand::MO_FrameIndex:
269    OS << "<fi#" << MO.getFrameIndex() << ">";
270    break;
271  default:
272    assert(0 && "Unrecognized operand type");
273  }
274
275  if (CloseParen)
276    OS << ")";
277}
278
279void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
280  unsigned StartOp = 0;
281
282   // Specialize printing if op#0 is definition
283  if (getNumOperands() && operandIsDefined(0)) {
284    ::print(getOperand(0), OS, TM);
285    OS << " = ";
286    ++StartOp;   // Don't print this operand again!
287  }
288  OS << TM.getInstrInfo().getName(getOpcode());
289
290  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
291    if (i != StartOp)
292      OS << ",";
293    OS << " ";
294    ::print(getOperand(i), OS, TM);
295
296    if (operandIsDefinedAndUsed(i))
297      OS << "<def&use>";
298    else if (operandIsDefined(i))
299      OS << "<def>";
300  }
301
302  // code for printing implict references
303  if (getNumImplicitRefs()) {
304    OS << "\tImplicitRefs: ";
305    for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
306      OS << "\t";
307      OutputValue(OS, getImplicitRef(i));
308      if (implicitRefIsDefinedAndUsed(i))
309        OS << "<def&use>";
310      else if (implicitRefIsDefined(i))
311        OS << "<def>";
312    }
313  }
314
315  OS << "\n";
316}
317
318
319std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
320{
321  os << TargetInstrDescriptors[minstr.opCode].Name;
322
323  for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
324    os << "\t" << minstr.getOperand(i);
325    if( minstr.operandIsDefined(i) )
326      os << "*";
327    if( minstr.operandIsDefinedAndUsed(i) )
328      os << "*";
329  }
330
331  // code for printing implict references
332  unsigned NumOfImpRefs =  minstr.getNumImplicitRefs();
333  if(  NumOfImpRefs > 0 ) {
334    os << "\tImplicit: ";
335    for(unsigned z=0; z < NumOfImpRefs; z++) {
336      OutputValue(os, minstr.getImplicitRef(z));
337      if( minstr.implicitRefIsDefined(z)) os << "*";
338      if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
339      os << "\t";
340    }
341  }
342
343  return os << "\n";
344}
345
346std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
347{
348  if (MO.opHiBits32())
349    OS << "%lm(";
350  else if (MO.opLoBits32())
351    OS << "%lo(";
352  else if (MO.opHiBits64())
353    OS << "%hh(";
354  else if (MO.opLoBits64())
355    OS << "%hm(";
356
357  switch (MO.getType())
358    {
359    case MachineOperand::MO_VirtualRegister:
360      OS << "%reg";
361      OutputValue(OS, MO.getVRegValue());
362      if (MO.hasAllocatedReg()) {
363        OS << "==";
364        OutputReg(OS, MO.getAllocatedRegNum());
365      }
366      break;
367    case MachineOperand::MO_CCRegister:
368      OS << "%ccreg";
369      OutputValue(OS, MO.getVRegValue());
370      if (MO.hasAllocatedReg()) {
371        OS << "==";
372        OutputReg(OS, MO.getAllocatedRegNum());
373      }
374      break;
375    case MachineOperand::MO_MachineRegister:
376      OutputReg(OS, MO.getMachineRegNum());
377      break;
378    case MachineOperand::MO_SignExtendedImmed:
379      OS << (long)MO.getImmedValue();
380      break;
381    case MachineOperand::MO_UnextendedImmed:
382      OS << (long)MO.getImmedValue();
383      break;
384    case MachineOperand::MO_PCRelativeDisp:
385      {
386        const Value* opVal = MO.getVRegValue();
387        bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
388        OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
389        if (opVal->hasName())
390          OS << opVal->getName();
391        else
392          OS << (const void*) opVal;
393        OS << ")";
394        break;
395      }
396    case MachineOperand::MO_MachineBasicBlock:
397      OS << "bb<"
398         << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
399         << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">";
400      break;
401    case MachineOperand::MO_FrameIndex:
402      OS << "<fi#" << MO.getFrameIndex() << ">";
403      break;
404    default:
405      assert(0 && "Unrecognized operand type");
406      break;
407    }
408
409  if (MO.flags &
410      (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
411       MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
412    OS << ")";
413
414  return OS;
415}
416