MachineInstr.cpp revision 10f3597c4e0c13ecf0272b7ca0be741a91ade48c 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12// FIXME: Now that MachineInstrs have parent pointers, they should always
13// print themselves using their MachineFunction's TargetMachine.
14//
15//===----------------------------------------------------------------------===//
16
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/Value.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/MRegisterInfo.h"
23#include "llvm/Support/LeakDetector.h"
24#include <iostream>
25
26using namespace llvm;
27
28// Global variable holding an array of descriptors for machine instructions.
29// The actual object needs to be created separately for each target machine.
30// This variable is initialized and reset by class TargetInstrInfo.
31//
32// FIXME: This should be a property of the target so that more than one target
33// at a time can be active...
34//
35namespace llvm {
36  extern const TargetInstrDescriptor *TargetInstrDescriptors;
37}
38
39// Constructor for instructions with variable #operands
40MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41  : Opcode(opcode),
42    operands(numOperands, MachineOperand()),
43    parent(0) {
44  // Make sure that we get added to a machine basicblock
45  LeakDetector::addGarbageObject(this);
46}
47
48/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
49/// not a resize for them.  It is expected that if you use this that you call
50/// add* methods below to fill up the operands, instead of the Set methods.
51/// Eventually, the "resizing" ctors will be phased out.
52///
53MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
54  : Opcode(opcode), parent(0) {
55  operands.reserve(numOperands);
56  // Make sure that we get added to a machine basicblock
57  LeakDetector::addGarbageObject(this);
58}
59
60/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
61/// MachineInstr is created and added to the end of the specified basic block.
62///
63MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
64                           unsigned numOperands)
65  : Opcode(opcode), parent(0) {
66  assert(MBB && "Cannot use inserting ctor with null basic block!");
67  operands.reserve(numOperands);
68  // Make sure that we get added to a machine basicblock
69  LeakDetector::addGarbageObject(this);
70  MBB->push_back(this);  // Add instruction to end of basic block!
71}
72
73/// MachineInstr ctor - Copies MachineInstr arg exactly
74///
75MachineInstr::MachineInstr(const MachineInstr &MI) {
76  Opcode = MI.getOpcode();
77  operands.reserve(MI.getNumOperands());
78
79  // Add operands
80  for (unsigned i = 0; i < MI.getNumOperands(); ++i)
81    operands.push_back(MachineOperand(MI.getOperand(i)));
82
83  // Set parent, next, and prev to null
84  parent = 0;
85  prev = 0;
86  next = 0;
87}
88
89
90MachineInstr::~MachineInstr() {
91  LeakDetector::removeGarbageObject(this);
92}
93
94/// clone - Create a copy of 'this' instruction that is identical in all ways
95/// except the following: the new instruction has no parent and it has no name
96///
97MachineInstr* MachineInstr::clone() const {
98  return new MachineInstr(*this);
99}
100
101/// removeFromParent - This method unlinks 'this' from the containing basic
102/// block, and returns it, but does not delete it.
103MachineInstr *MachineInstr::removeFromParent() {
104  assert(getParent() && "Not embedded in a basic block!");
105  getParent()->remove(this);
106  return this;
107}
108
109
110/// OperandComplete - Return true if it's illegal to add a new operand
111///
112bool MachineInstr::OperandsComplete() const {
113  int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
114  if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
115    return true;  // Broken: we have all the operands of this instruction!
116  return false;
117}
118
119void MachineInstr::SetMachineOperandVal(unsigned i,
120                                        MachineOperand::MachineOperandType opTy,
121                                        Value* V) {
122  assert(i < operands.size());          // may be explicit or implicit op
123  operands[i].opType = opTy;
124  operands[i].contents.value = V;
125  operands[i].extra.regNum = -1;
126}
127
128void
129MachineInstr::SetMachineOperandConst(unsigned i,
130                                     MachineOperand::MachineOperandType opTy,
131                                     int intValue) {
132  assert(i < getNumOperands());          // must be explicit op
133
134  operands[i].opType = opTy;
135  operands[i].contents.value = NULL;
136  operands[i].contents.immedVal = intValue;
137  operands[i].extra.regNum = -1;
138  operands[i].flags = 0;
139}
140
141void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
142  assert(i < getNumOperands());          // must be explicit op
143
144  operands[i].opType = MachineOperand::MO_MachineRegister;
145  operands[i].contents.value = NULL;
146  operands[i].extra.regNum = regNum;
147}
148
149void MachineInstr::dump() const {
150  std::cerr << "  " << *this;
151}
152
153static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
154  os << "(val ";
155  os << (void*) val;                // print address always
156  if (val && val->hasName())
157    os << " " << val->getName();    // print name also, if available
158  os << ")";
159  return os;
160}
161
162static inline void OutputReg(std::ostream &os, unsigned RegNo,
163                             const MRegisterInfo *MRI = 0) {
164  if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
165    if (MRI)
166      os << "%" << MRI->get(RegNo).Name;
167    else
168      os << "%mreg(" << RegNo << ")";
169  } else
170    os << "%reg" << RegNo;
171}
172
173static void print(const MachineOperand &MO, std::ostream &OS,
174                  const TargetMachine *TM) {
175  const MRegisterInfo *MRI = 0;
176
177  if (TM) MRI = TM->getRegisterInfo();
178
179  bool CloseParen = true;
180  if (MO.isHiBits32())
181    OS << "%lm(";
182  else if (MO.isLoBits32())
183    OS << "%lo(";
184  else if (MO.isHiBits64())
185    OS << "%hh(";
186  else if (MO.isLoBits64())
187    OS << "%hm(";
188  else
189    CloseParen = false;
190
191  switch (MO.getType()) {
192  case MachineOperand::MO_VirtualRegister:
193    if (MO.getVRegValue()) {
194      OS << "%reg";
195      OutputValue(OS, MO.getVRegValue());
196      if (MO.hasAllocatedReg())
197        OS << "==";
198    }
199    if (MO.hasAllocatedReg())
200      OutputReg(OS, MO.getReg(), MRI);
201    break;
202  case MachineOperand::MO_MachineRegister:
203    OutputReg(OS, MO.getMachineRegNum(), MRI);
204    break;
205  case MachineOperand::MO_SignExtendedImmed:
206    OS << (long)MO.getImmedValue();
207    break;
208  case MachineOperand::MO_UnextendedImmed:
209    OS << (long)MO.getImmedValue();
210    break;
211  case MachineOperand::MO_MachineBasicBlock:
212    OS << "mbb<"
213       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
214       << "," << (void*)MO.getMachineBasicBlock() << ">";
215    break;
216  case MachineOperand::MO_FrameIndex:
217    OS << "<fi#" << MO.getFrameIndex() << ">";
218    break;
219  case MachineOperand::MO_ConstantPoolIndex:
220    OS << "<cp#" << MO.getConstantPoolIndex() << ">";
221    break;
222  case MachineOperand::MO_JumpTableIndex:
223    OS << "<jt#" << MO.getJumpTableIndex() << ">";
224    break;
225  case MachineOperand::MO_GlobalAddress:
226    OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
227    if (MO.getOffset()) OS << "+" << MO.getOffset();
228    OS << ">";
229    break;
230  case MachineOperand::MO_ExternalSymbol:
231    OS << "<es:" << MO.getSymbolName();
232    if (MO.getOffset()) OS << "+" << MO.getOffset();
233    OS << ">";
234    break;
235  default:
236    assert(0 && "Unrecognized operand type");
237  }
238
239  if (CloseParen)
240    OS << ")";
241}
242
243void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
244  unsigned StartOp = 0;
245
246   // Specialize printing if op#0 is definition
247  if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
248    ::print(getOperand(0), OS, TM);
249    OS << " = ";
250    ++StartOp;   // Don't print this operand again!
251  }
252
253  // Must check if Target machine is not null because machine BB could not
254  // be attached to a Machine function yet
255  if (TM)
256    OS << TM->getInstrInfo()->getName(getOpcode());
257
258  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
259    const MachineOperand& mop = getOperand(i);
260    if (i != StartOp)
261      OS << ",";
262    OS << " ";
263    ::print(mop, OS, TM);
264
265    if (mop.isDef())
266      if (mop.isUse())
267        OS << "<def&use>";
268      else
269        OS << "<def>";
270  }
271
272  OS << "\n";
273}
274
275namespace llvm {
276std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
277  // If the instruction is embedded into a basic block, we can find the target
278  // info for the instruction.
279  if (const MachineBasicBlock *MBB = MI.getParent()) {
280    const MachineFunction *MF = MBB->getParent();
281    if (MF)
282      MI.print(os, &MF->getTarget());
283    else
284      MI.print(os, 0);
285    return os;
286  }
287
288  // Otherwise, print it out in the "raw" format without symbolic register names
289  // and such.
290  os << TargetInstrDescriptors[MI.getOpcode()].Name;
291
292  for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
293    os << "\t" << MI.getOperand(i);
294    if (MI.getOperand(i).isDef())
295      if (MI.getOperand(i).isUse())
296        os << "<d&u>";
297      else
298        os << "<d>";
299  }
300
301  return os << "\n";
302}
303
304std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
305  if (MO.isHiBits32())
306    OS << "%lm(";
307  else if (MO.isLoBits32())
308    OS << "%lo(";
309  else if (MO.isHiBits64())
310    OS << "%hh(";
311  else if (MO.isLoBits64())
312    OS << "%hm(";
313
314  switch (MO.getType()) {
315  case MachineOperand::MO_VirtualRegister:
316    if (MO.hasAllocatedReg())
317      OutputReg(OS, MO.getReg());
318
319    if (MO.getVRegValue()) {
320      if (MO.hasAllocatedReg()) OS << "==";
321      OS << "%vreg";
322      OutputValue(OS, MO.getVRegValue());
323    }
324    break;
325  case MachineOperand::MO_MachineRegister:
326    OutputReg(OS, MO.getMachineRegNum());
327    break;
328  case MachineOperand::MO_SignExtendedImmed:
329    OS << (long)MO.getImmedValue();
330    break;
331  case MachineOperand::MO_UnextendedImmed:
332    OS << (long)MO.getImmedValue();
333    break;
334  case MachineOperand::MO_MachineBasicBlock:
335    OS << "<mbb:"
336       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
337       << "@" << (void*)MO.getMachineBasicBlock() << ">";
338    break;
339  case MachineOperand::MO_FrameIndex:
340    OS << "<fi#" << MO.getFrameIndex() << ">";
341    break;
342  case MachineOperand::MO_ConstantPoolIndex:
343    OS << "<cp#" << MO.getConstantPoolIndex() << ">";
344    break;
345  case MachineOperand::MO_JumpTableIndex:
346    OS << "<jt#" << MO.getJumpTableIndex() << ">";
347    break;
348  case MachineOperand::MO_GlobalAddress:
349    OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
350    break;
351  case MachineOperand::MO_ExternalSymbol:
352    OS << "<es:" << MO.getSymbolName() << ">";
353    break;
354  default:
355    assert(0 && "Unrecognized operand type");
356    break;
357  }
358
359  if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
360    OS << ")";
361
362  return OS;
363}
364
365}
366