MachineInstr.cpp revision 181eb737b28628adc4376b973610a02039385026 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/CodeGen/SelectionDAGNodes.h"
21#include "llvm/Target/TargetMachine.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Target/TargetInstrDesc.h"
24#include "llvm/Target/TargetRegisterInfo.h"
25#include "llvm/Support/LeakDetector.h"
26#include "llvm/Support/Streams.h"
27#include <ostream>
28using namespace llvm;
29
30//===----------------------------------------------------------------------===//
31// MachineOperand Implementation
32//===----------------------------------------------------------------------===//
33
34/// AddRegOperandToRegInfo - Add this register operand to the specified
35/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
36/// explicitly nulled out.
37void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
38  assert(isReg() && "Can only add reg operand to use lists");
39
40  // If the reginfo pointer is null, just explicitly null out or next/prev
41  // pointers, to ensure they are not garbage.
42  if (RegInfo == 0) {
43    Contents.Reg.Prev = 0;
44    Contents.Reg.Next = 0;
45    return;
46  }
47
48  // Otherwise, add this operand to the head of the registers use/def list.
49  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
50
51  // For SSA values, we prefer to keep the definition at the start of the list.
52  // we do this by skipping over the definition if it is at the head of the
53  // list.
54  if (*Head && (*Head)->isDef())
55    Head = &(*Head)->Contents.Reg.Next;
56
57  Contents.Reg.Next = *Head;
58  if (Contents.Reg.Next) {
59    assert(getReg() == Contents.Reg.Next->getReg() &&
60           "Different regs on the same list!");
61    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
62  }
63
64  Contents.Reg.Prev = Head;
65  *Head = this;
66}
67
68void MachineOperand::setReg(unsigned Reg) {
69  if (getReg() == Reg) return; // No change.
70
71  // Otherwise, we have to change the register.  If this operand is embedded
72  // into a machine function, we need to update the old and new register's
73  // use/def lists.
74  if (MachineInstr *MI = getParent())
75    if (MachineBasicBlock *MBB = MI->getParent())
76      if (MachineFunction *MF = MBB->getParent()) {
77        RemoveRegOperandFromRegInfo();
78        Contents.Reg.RegNo = Reg;
79        AddRegOperandToRegInfo(&MF->getRegInfo());
80        return;
81      }
82
83  // Otherwise, just change the register, no problem.  :)
84  Contents.Reg.RegNo = Reg;
85}
86
87/// ChangeToImmediate - Replace this operand with a new immediate operand of
88/// the specified value.  If an operand is known to be an immediate already,
89/// the setImm method should be used.
90void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
91  // If this operand is currently a register operand, and if this is in a
92  // function, deregister the operand from the register's use/def list.
93  if (isReg() && getParent() && getParent()->getParent() &&
94      getParent()->getParent()->getParent())
95    RemoveRegOperandFromRegInfo();
96
97  OpKind = MO_Immediate;
98  Contents.ImmVal = ImmVal;
99}
100
101/// ChangeToRegister - Replace this operand with a new register operand of
102/// the specified value.  If an operand is known to be an register already,
103/// the setReg method should be used.
104void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
105                                      bool isKill, bool isDead) {
106  // If this operand is already a register operand, use setReg to update the
107  // register's use/def lists.
108  if (isReg()) {
109    setReg(Reg);
110  } else {
111    // Otherwise, change this to a register and set the reg#.
112    OpKind = MO_Register;
113    Contents.Reg.RegNo = Reg;
114
115    // If this operand is embedded in a function, add the operand to the
116    // register's use/def list.
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          AddRegOperandToRegInfo(&MF->getRegInfo());
121  }
122
123  IsDef = isDef;
124  IsImp = isImp;
125  IsKill = isKill;
126  IsDead = isDead;
127  SubReg = 0;
128}
129
130/// isIdenticalTo - Return true if this operand is identical to the specified
131/// operand.
132bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
133  if (getType() != Other.getType()) return false;
134
135  switch (getType()) {
136  default: assert(0 && "Unrecognized operand type");
137  case MachineOperand::MO_Register:
138    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
139           getSubReg() == Other.getSubReg();
140  case MachineOperand::MO_Immediate:
141    return getImm() == Other.getImm();
142  case MachineOperand::MO_FPImmediate:
143    return getFPImm() == Other.getFPImm();
144  case MachineOperand::MO_MachineBasicBlock:
145    return getMBB() == Other.getMBB();
146  case MachineOperand::MO_FrameIndex:
147    return getIndex() == Other.getIndex();
148  case MachineOperand::MO_ConstantPoolIndex:
149    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
150  case MachineOperand::MO_JumpTableIndex:
151    return getIndex() == Other.getIndex();
152  case MachineOperand::MO_GlobalAddress:
153    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
154  case MachineOperand::MO_ExternalSymbol:
155    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
156           getOffset() == Other.getOffset();
157  }
158}
159
160/// print - Print the specified machine operand.
161///
162void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
163  switch (getType()) {
164  case MachineOperand::MO_Register:
165    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
166      OS << "%reg" << getReg();
167    } else {
168      // If the instruction is embedded into a basic block, we can find the
169      // target info for the instruction.
170      if (TM == 0)
171        if (const MachineInstr *MI = getParent())
172          if (const MachineBasicBlock *MBB = MI->getParent())
173            if (const MachineFunction *MF = MBB->getParent())
174              TM = &MF->getTarget();
175
176      if (TM)
177        OS << "%" << TM->getRegisterInfo()->get(getReg()).PrintableName;
178      else
179        OS << "%mreg" << getReg();
180    }
181
182    if (isDef() || isKill() || isDead() || isImplicit()) {
183      OS << "<";
184      bool NeedComma = false;
185      if (isImplicit()) {
186        OS << (isDef() ? "imp-def" : "imp-use");
187        NeedComma = true;
188      } else if (isDef()) {
189        OS << "def";
190        NeedComma = true;
191      }
192      if (isKill() || isDead()) {
193        if (NeedComma) OS << ",";
194        if (isKill())  OS << "kill";
195        if (isDead())  OS << "dead";
196      }
197      OS << ">";
198    }
199    break;
200  case MachineOperand::MO_Immediate:
201    OS << getImm();
202    break;
203  case MachineOperand::MO_FPImmediate:
204    if (getFPImm()->getType() == Type::FloatTy) {
205      OS << getFPImm()->getValueAPF().convertToFloat();
206    } else {
207      OS << getFPImm()->getValueAPF().convertToDouble();
208    }
209    break;
210  case MachineOperand::MO_MachineBasicBlock:
211    OS << "mbb<"
212       << ((Value*)getMBB()->getBasicBlock())->getName()
213       << "," << (void*)getMBB() << ">";
214    break;
215  case MachineOperand::MO_FrameIndex:
216    OS << "<fi#" << getIndex() << ">";
217    break;
218  case MachineOperand::MO_ConstantPoolIndex:
219    OS << "<cp#" << getIndex();
220    if (getOffset()) OS << "+" << getOffset();
221    OS << ">";
222    break;
223  case MachineOperand::MO_JumpTableIndex:
224    OS << "<jt#" << getIndex() << ">";
225    break;
226  case MachineOperand::MO_GlobalAddress:
227    OS << "<ga:" << ((Value*)getGlobal())->getName();
228    if (getOffset()) OS << "+" << getOffset();
229    OS << ">";
230    break;
231  case MachineOperand::MO_ExternalSymbol:
232    OS << "<es:" << getSymbolName();
233    if (getOffset()) OS << "+" << getOffset();
234    OS << ">";
235    break;
236  default:
237    assert(0 && "Unrecognized operand type");
238  }
239}
240
241//===----------------------------------------------------------------------===//
242// MachineInstr Implementation
243//===----------------------------------------------------------------------===//
244
245/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
246/// TID NULL and no operands.
247MachineInstr::MachineInstr()
248  : TID(0), NumImplicitOps(0), Parent(0) {
249  // Make sure that we get added to a machine basicblock
250  LeakDetector::addGarbageObject(this);
251}
252
253void MachineInstr::addImplicitDefUseOperands() {
254  if (TID->ImplicitDefs)
255    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
256      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
257  if (TID->ImplicitUses)
258    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
259      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
260}
261
262/// MachineInstr ctor - This constructor create a MachineInstr and add the
263/// implicit operands. It reserves space for number of operands specified by
264/// TargetInstrDesc or the numOperands if it is not zero. (for
265/// instructions with variable number of operands).
266MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
267  : TID(&tid), NumImplicitOps(0), Parent(0) {
268  if (!NoImp && TID->getImplicitDefs())
269    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
270      NumImplicitOps++;
271  if (!NoImp && TID->getImplicitUses())
272    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
273      NumImplicitOps++;
274  Operands.reserve(NumImplicitOps + TID->getNumOperands());
275  if (!NoImp)
276    addImplicitDefUseOperands();
277  // Make sure that we get added to a machine basicblock
278  LeakDetector::addGarbageObject(this);
279}
280
281/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
282/// MachineInstr is created and added to the end of the specified basic block.
283///
284MachineInstr::MachineInstr(MachineBasicBlock *MBB,
285                           const TargetInstrDesc &tid)
286  : TID(&tid), NumImplicitOps(0), Parent(0) {
287  assert(MBB && "Cannot use inserting ctor with null basic block!");
288  if (TID->ImplicitDefs)
289    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
290      NumImplicitOps++;
291  if (TID->ImplicitUses)
292    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
293      NumImplicitOps++;
294  Operands.reserve(NumImplicitOps + TID->getNumOperands());
295  addImplicitDefUseOperands();
296  // Make sure that we get added to a machine basicblock
297  LeakDetector::addGarbageObject(this);
298  MBB->push_back(this);  // Add instruction to end of basic block!
299}
300
301/// MachineInstr ctor - Copies MachineInstr arg exactly
302///
303MachineInstr::MachineInstr(const MachineInstr &MI) {
304  TID = &MI.getDesc();
305  NumImplicitOps = MI.NumImplicitOps;
306  Operands.reserve(MI.getNumOperands());
307  MemOperands = MI.MemOperands;
308
309  // Add operands
310  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
311    Operands.push_back(MI.getOperand(i));
312    Operands.back().ParentMI = this;
313  }
314
315  // Set parent, next, and prev to null
316  Parent = 0;
317  Prev = 0;
318  Next = 0;
319}
320
321
322MachineInstr::~MachineInstr() {
323  LeakDetector::removeGarbageObject(this);
324#ifndef NDEBUG
325  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
326    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
327    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
328           "Reg operand def/use list corrupted");
329  }
330#endif
331}
332
333/// getOpcode - Returns the opcode of this MachineInstr.
334///
335int MachineInstr::getOpcode() const {
336  return TID->Opcode;
337}
338
339/// getRegInfo - If this instruction is embedded into a MachineFunction,
340/// return the MachineRegisterInfo object for the current function, otherwise
341/// return null.
342MachineRegisterInfo *MachineInstr::getRegInfo() {
343  if (MachineBasicBlock *MBB = getParent())
344    if (MachineFunction *MF = MBB->getParent())
345      return &MF->getRegInfo();
346  return 0;
347}
348
349/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
350/// this instruction from their respective use lists.  This requires that the
351/// operands already be on their use lists.
352void MachineInstr::RemoveRegOperandsFromUseLists() {
353  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
354    if (Operands[i].isReg())
355      Operands[i].RemoveRegOperandFromRegInfo();
356  }
357}
358
359/// AddRegOperandsToUseLists - Add all of the register operands in
360/// this instruction from their respective use lists.  This requires that the
361/// operands not be on their use lists yet.
362void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
363  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
364    if (Operands[i].isReg())
365      Operands[i].AddRegOperandToRegInfo(&RegInfo);
366  }
367}
368
369
370/// addOperand - Add the specified operand to the instruction.  If it is an
371/// implicit operand, it is added to the end of the operand list.  If it is
372/// an explicit operand it is added at the end of the explicit operand list
373/// (before the first implicit operand).
374void MachineInstr::addOperand(const MachineOperand &Op) {
375  bool isImpReg = Op.isReg() && Op.isImplicit();
376  assert((isImpReg || !OperandsComplete()) &&
377         "Trying to add an operand to a machine instr that is already done!");
378
379  // If we are adding the operand to the end of the list, our job is simpler.
380  // This is true most of the time, so this is a reasonable optimization.
381  if (isImpReg || NumImplicitOps == 0) {
382    // We can only do this optimization if we know that the operand list won't
383    // reallocate.
384    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
385      Operands.push_back(Op);
386
387      // Set the parent of the operand.
388      Operands.back().ParentMI = this;
389
390      // If the operand is a register, update the operand's use list.
391      if (Op.isReg())
392        Operands.back().AddRegOperandToRegInfo(getRegInfo());
393      return;
394    }
395  }
396
397  // Otherwise, we have to insert a real operand before any implicit ones.
398  unsigned OpNo = Operands.size()-NumImplicitOps;
399
400  MachineRegisterInfo *RegInfo = getRegInfo();
401
402  // If this instruction isn't embedded into a function, then we don't need to
403  // update any operand lists.
404  if (RegInfo == 0) {
405    // Simple insertion, no reginfo update needed for other register operands.
406    Operands.insert(Operands.begin()+OpNo, Op);
407    Operands[OpNo].ParentMI = this;
408
409    // Do explicitly set the reginfo for this operand though, to ensure the
410    // next/prev fields are properly nulled out.
411    if (Operands[OpNo].isReg())
412      Operands[OpNo].AddRegOperandToRegInfo(0);
413
414  } else if (Operands.size()+1 <= Operands.capacity()) {
415    // Otherwise, we have to remove register operands from their register use
416    // list, add the operand, then add the register operands back to their use
417    // list.  This also must handle the case when the operand list reallocates
418    // to somewhere else.
419
420    // If insertion of this operand won't cause reallocation of the operand
421    // list, just remove the implicit operands, add the operand, then re-add all
422    // the rest of the operands.
423    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
424      assert(Operands[i].isReg() && "Should only be an implicit reg!");
425      Operands[i].RemoveRegOperandFromRegInfo();
426    }
427
428    // Add the operand.  If it is a register, add it to the reg list.
429    Operands.insert(Operands.begin()+OpNo, Op);
430    Operands[OpNo].ParentMI = this;
431
432    if (Operands[OpNo].isReg())
433      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
434
435    // Re-add all the implicit ops.
436    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
437      assert(Operands[i].isReg() && "Should only be an implicit reg!");
438      Operands[i].AddRegOperandToRegInfo(RegInfo);
439    }
440  } else {
441    // Otherwise, we will be reallocating the operand list.  Remove all reg
442    // operands from their list, then readd them after the operand list is
443    // reallocated.
444    RemoveRegOperandsFromUseLists();
445
446    Operands.insert(Operands.begin()+OpNo, Op);
447    Operands[OpNo].ParentMI = this;
448
449    // Re-add all the operands.
450    AddRegOperandsToUseLists(*RegInfo);
451  }
452}
453
454/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
455/// fewer operand than it started with.
456///
457void MachineInstr::RemoveOperand(unsigned OpNo) {
458  assert(OpNo < Operands.size() && "Invalid operand number");
459
460  // Special case removing the last one.
461  if (OpNo == Operands.size()-1) {
462    // If needed, remove from the reg def/use list.
463    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
464      Operands.back().RemoveRegOperandFromRegInfo();
465
466    Operands.pop_back();
467    return;
468  }
469
470  // Otherwise, we are removing an interior operand.  If we have reginfo to
471  // update, remove all operands that will be shifted down from their reg lists,
472  // move everything down, then re-add them.
473  MachineRegisterInfo *RegInfo = getRegInfo();
474  if (RegInfo) {
475    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
476      if (Operands[i].isReg())
477        Operands[i].RemoveRegOperandFromRegInfo();
478    }
479  }
480
481  Operands.erase(Operands.begin()+OpNo);
482
483  if (RegInfo) {
484    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
485      if (Operands[i].isReg())
486        Operands[i].AddRegOperandToRegInfo(RegInfo);
487    }
488  }
489}
490
491
492/// removeFromParent - This method unlinks 'this' from the containing basic
493/// block, and returns it, but does not delete it.
494MachineInstr *MachineInstr::removeFromParent() {
495  assert(getParent() && "Not embedded in a basic block!");
496  getParent()->remove(this);
497  return this;
498}
499
500
501/// OperandComplete - Return true if it's illegal to add a new operand
502///
503bool MachineInstr::OperandsComplete() const {
504  unsigned short NumOperands = TID->getNumOperands();
505  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
506    return true;  // Broken: we have all the operands of this instruction!
507  return false;
508}
509
510/// getNumExplicitOperands - Returns the number of non-implicit operands.
511///
512unsigned MachineInstr::getNumExplicitOperands() const {
513  unsigned NumOperands = TID->getNumOperands();
514  if (!TID->isVariadic())
515    return NumOperands;
516
517  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
518    const MachineOperand &MO = getOperand(NumOperands);
519    if (!MO.isRegister() || !MO.isImplicit())
520      NumOperands++;
521  }
522  return NumOperands;
523}
524
525
526/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
527///
528bool MachineInstr::isDebugLabel() const {
529  return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
530}
531
532/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
533/// the specific register or -1 if it is not found. It further tightening
534/// the search criteria to a use that kills the register if isKill is true.
535int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
536  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
537    const MachineOperand &MO = getOperand(i);
538    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
539      if (!isKill || MO.isKill())
540        return i;
541  }
542  return -1;
543}
544
545/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
546/// the specific register or NULL if it is not found.
547MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
548  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
549    MachineOperand &MO = getOperand(i);
550    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
551      return &MO;
552  }
553  return NULL;
554}
555
556/// findFirstPredOperandIdx() - Find the index of the first operand in the
557/// operand list that is used to represent the predicate. It returns -1 if
558/// none is found.
559int MachineInstr::findFirstPredOperandIdx() const {
560  const TargetInstrDesc &TID = getDesc();
561  if (TID.isPredicable()) {
562    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
563      if (TID.OpInfo[i].isPredicate())
564        return i;
565  }
566
567  return -1;
568}
569
570/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
571/// to two addr elimination.
572bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
573  const TargetInstrDesc &TID = getDesc();
574  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
575    const MachineOperand &MO1 = getOperand(i);
576    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
577      for (unsigned j = i+1; j < e; ++j) {
578        const MachineOperand &MO2 = getOperand(j);
579        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
580            TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
581          return true;
582      }
583    }
584  }
585  return false;
586}
587
588/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
589///
590void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
591  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
592    const MachineOperand &MO = MI->getOperand(i);
593    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
594      continue;
595    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
596      MachineOperand &MOp = getOperand(j);
597      if (!MOp.isIdenticalTo(MO))
598        continue;
599      if (MO.isKill())
600        MOp.setIsKill();
601      else
602        MOp.setIsDead();
603      break;
604    }
605  }
606}
607
608/// copyPredicates - Copies predicate operand(s) from MI.
609void MachineInstr::copyPredicates(const MachineInstr *MI) {
610  const TargetInstrDesc &TID = MI->getDesc();
611  if (TID.isPredicable()) {
612    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
613      if (TID.OpInfo[i].isPredicate()) {
614        // Predicated operands must be last operands.
615        addOperand(MI->getOperand(i));
616      }
617    }
618  }
619}
620
621void MachineInstr::dump() const {
622  cerr << "  " << *this;
623}
624
625void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
626  // Specialize printing if op#0 is definition
627  unsigned StartOp = 0;
628  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
629    getOperand(0).print(OS, TM);
630    OS << " = ";
631    ++StartOp;   // Don't print this operand again!
632  }
633
634  OS << getDesc().getName();
635
636  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
637    if (i != StartOp)
638      OS << ",";
639    OS << " ";
640    getOperand(i).print(OS, TM);
641  }
642
643  if (getNumMemOperands() > 0) {
644    OS << ", Mem:";
645    for (unsigned i = 0; i < getNumMemOperands(); i++) {
646      const MemOperand &MRO = getMemOperand(i);
647      const Value *V = MRO.getValue();
648
649      assert((MRO.isLoad() || MRO.isStore()) &&
650             "SV has to be a load, store or both.");
651
652      if (MRO.isVolatile())
653        OS << "Volatile ";
654
655      if (MRO.isLoad())
656        OS << "LD";
657      if (MRO.isStore())
658        OS << "ST";
659
660      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
661
662      if (!V)
663        OS << "<unknown>";
664      else if (!V->getName().empty())
665        OS << V->getName();
666      else if (isa<PseudoSourceValue>(V))
667        OS << *V;
668      else
669        OS << V;
670
671      OS << " + " << MRO.getOffset() << "]";
672    }
673  }
674
675  OS << "\n";
676}
677
678bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
679                                     const TargetRegisterInfo *RegInfo,
680                                     bool AddIfNotFound) {
681  bool Found = false;
682  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
683    MachineOperand &MO = getOperand(i);
684    if (MO.isRegister() && MO.isUse()) {
685      unsigned Reg = MO.getReg();
686      if (!Reg)
687        continue;
688      if (Reg == IncomingReg) {
689        MO.setIsKill();
690        Found = true;
691        break;
692      } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
693                 TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
694                 RegInfo->isSuperRegister(IncomingReg, Reg) &&
695                 MO.isKill())
696        // A super-register kill already exists.
697        Found = true;
698    }
699  }
700
701  // If not found, this means an alias of one of the operand is killed. Add a
702  // new implicit operand if required.
703  if (!Found && AddIfNotFound) {
704    addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/,
705                                         true/*IsImp*/,true/*IsKill*/));
706    return true;
707  }
708  return Found;
709}
710
711bool MachineInstr::addRegisterDead(unsigned IncomingReg,
712                                   const TargetRegisterInfo *RegInfo,
713                                   bool AddIfNotFound) {
714  bool Found = false;
715  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
716    MachineOperand &MO = getOperand(i);
717    if (MO.isRegister() && MO.isDef()) {
718      unsigned Reg = MO.getReg();
719      if (!Reg)
720        continue;
721      if (Reg == IncomingReg) {
722        MO.setIsDead();
723        Found = true;
724        break;
725      } else if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
726                 TargetRegisterInfo::isPhysicalRegister(IncomingReg) &&
727                 RegInfo->isSuperRegister(IncomingReg, Reg) &&
728                 MO.isDead())
729        // There exists a super-register that's marked dead.
730        return true;
731    }
732  }
733
734  // If not found, this means an alias of one of the operand is dead. Add a
735  // new implicit operand.
736  if (!Found && AddIfNotFound) {
737    addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
738                                         true/*IsImp*/,false/*IsKill*/,
739                                         true/*IsDead*/));
740    return true;
741  }
742  return Found;
743}
744
745/// copyKillDeadInfo - copies killed/dead information from one instr to another
746void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI,
747                                    const TargetRegisterInfo *RegInfo) {
748  // If the instruction defines any virtual registers, update the VarInfo,
749  // kill and dead information for the instruction.
750  for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) {
751    MachineOperand &MO = OldMI->getOperand(i);
752    if (MO.isRegister() && MO.getReg() &&
753        TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
754      unsigned Reg = MO.getReg();
755      if (MO.isDef()) {
756        if (MO.isDead()) {
757          MO.setIsDead(false);
758          addRegisterDead(Reg, RegInfo);
759        }
760      }
761      if (MO.isKill()) {
762        MO.setIsKill(false);
763        addRegisterKilled(Reg, RegInfo);
764      }
765    }
766  }
767}
768