MachineInstr.cpp revision 201f2463a72f88121a3a31e7386029e99d2d75da 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/LLVMContext.h"
19#include "llvm/Metadata.h"
20#include "llvm/Module.h"
21#include "llvm/Type.h"
22#include "llvm/Value.h"
23#include "llvm/Assembly/Writer.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/Target/TargetInstrInfo.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/Analysis/DebugInfo.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/LeakDetector.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/FoldingSet.h"
43using namespace llvm;
44
45//===----------------------------------------------------------------------===//
46// MachineOperand Implementation
47//===----------------------------------------------------------------------===//
48
49/// AddRegOperandToRegInfo - Add this register operand to the specified
50/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
51/// explicitly nulled out.
52void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53  assert(isReg() && "Can only add reg operand to use lists");
54
55  // If the reginfo pointer is null, just explicitly null out or next/prev
56  // pointers, to ensure they are not garbage.
57  if (RegInfo == 0) {
58    Contents.Reg.Prev = 0;
59    Contents.Reg.Next = 0;
60    return;
61  }
62
63  // Otherwise, add this operand to the head of the registers use/def list.
64  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
65
66  // For SSA values, we prefer to keep the definition at the start of the list.
67  // we do this by skipping over the definition if it is at the head of the
68  // list.
69  if (*Head && (*Head)->isDef())
70    Head = &(*Head)->Contents.Reg.Next;
71
72  Contents.Reg.Next = *Head;
73  if (Contents.Reg.Next) {
74    assert(getReg() == Contents.Reg.Next->getReg() &&
75           "Different regs on the same list!");
76    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
77  }
78
79  Contents.Reg.Prev = Head;
80  *Head = this;
81}
82
83/// RemoveRegOperandFromRegInfo - Remove this register operand from the
84/// MachineRegisterInfo it is linked with.
85void MachineOperand::RemoveRegOperandFromRegInfo() {
86  assert(isOnRegUseList() && "Reg operand is not on a use list");
87  // Unlink this from the doubly linked list of operands.
88  MachineOperand *NextOp = Contents.Reg.Next;
89  *Contents.Reg.Prev = NextOp;
90  if (NextOp) {
91    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
93  }
94  Contents.Reg.Prev = 0;
95  Contents.Reg.Next = 0;
96}
97
98void MachineOperand::setReg(unsigned Reg) {
99  if (getReg() == Reg) return; // No change.
100
101  // Otherwise, we have to change the register.  If this operand is embedded
102  // into a machine function, we need to update the old and new register's
103  // use/def lists.
104  if (MachineInstr *MI = getParent())
105    if (MachineBasicBlock *MBB = MI->getParent())
106      if (MachineFunction *MF = MBB->getParent()) {
107        RemoveRegOperandFromRegInfo();
108        SmallContents.RegNo = Reg;
109        AddRegOperandToRegInfo(&MF->getRegInfo());
110        return;
111      }
112
113  // Otherwise, just change the register, no problem.  :)
114  SmallContents.RegNo = Reg;
115}
116
117void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118                                  const TargetRegisterInfo &TRI) {
119  assert(TargetRegisterInfo::isVirtualRegister(Reg));
120  if (SubIdx && getSubReg())
121    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
122  setReg(Reg);
123  if (SubIdx)
124    setSubReg(SubIdx);
125}
126
127void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
129  if (getSubReg()) {
130    Reg = TRI.getSubReg(Reg, getSubReg());
131    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132    // That won't happen in legal code.
133    setSubReg(0);
134  }
135  setReg(Reg);
136}
137
138/// ChangeToImmediate - Replace this operand with a new immediate operand of
139/// the specified value.  If an operand is known to be an immediate already,
140/// the setImm method should be used.
141void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142  // If this operand is currently a register operand, and if this is in a
143  // function, deregister the operand from the register's use/def list.
144  if (isReg() && getParent() && getParent()->getParent() &&
145      getParent()->getParent()->getParent())
146    RemoveRegOperandFromRegInfo();
147
148  OpKind = MO_Immediate;
149  Contents.ImmVal = ImmVal;
150}
151
152/// ChangeToRegister - Replace this operand with a new register operand of
153/// the specified value.  If an operand is known to be an register already,
154/// the setReg method should be used.
155void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156                                      bool isKill, bool isDead, bool isUndef,
157                                      bool isDebug) {
158  // If this operand is already a register operand, use setReg to update the
159  // register's use/def lists.
160  if (isReg()) {
161    assert(!isEarlyClobber());
162    setReg(Reg);
163  } else {
164    // Otherwise, change this to a register and set the reg#.
165    OpKind = MO_Register;
166    SmallContents.RegNo = Reg;
167
168    // If this operand is embedded in a function, add the operand to the
169    // register's use/def list.
170    if (MachineInstr *MI = getParent())
171      if (MachineBasicBlock *MBB = MI->getParent())
172        if (MachineFunction *MF = MBB->getParent())
173          AddRegOperandToRegInfo(&MF->getRegInfo());
174  }
175
176  IsDef = isDef;
177  IsImp = isImp;
178  IsKill = isKill;
179  IsDead = isDead;
180  IsUndef = isUndef;
181  IsEarlyClobber = false;
182  IsDebug = isDebug;
183  SubReg = 0;
184}
185
186/// isIdenticalTo - Return true if this operand is identical to the specified
187/// operand.
188bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
189  if (getType() != Other.getType() ||
190      getTargetFlags() != Other.getTargetFlags())
191    return false;
192
193  switch (getType()) {
194  default: llvm_unreachable("Unrecognized operand type");
195  case MachineOperand::MO_Register:
196    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197           getSubReg() == Other.getSubReg();
198  case MachineOperand::MO_Immediate:
199    return getImm() == Other.getImm();
200  case MachineOperand::MO_CImmediate:
201    return getCImm() == Other.getCImm();
202  case MachineOperand::MO_FPImmediate:
203    return getFPImm() == Other.getFPImm();
204  case MachineOperand::MO_MachineBasicBlock:
205    return getMBB() == Other.getMBB();
206  case MachineOperand::MO_FrameIndex:
207    return getIndex() == Other.getIndex();
208  case MachineOperand::MO_ConstantPoolIndex:
209    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210  case MachineOperand::MO_JumpTableIndex:
211    return getIndex() == Other.getIndex();
212  case MachineOperand::MO_GlobalAddress:
213    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214  case MachineOperand::MO_ExternalSymbol:
215    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216           getOffset() == Other.getOffset();
217  case MachineOperand::MO_BlockAddress:
218    return getBlockAddress() == Other.getBlockAddress();
219  case MachineOperand::MO_MCSymbol:
220    return getMCSymbol() == Other.getMCSymbol();
221  case MachineOperand::MO_Metadata:
222    return getMetadata() == Other.getMetadata();
223  }
224}
225
226/// print - Print the specified machine operand.
227///
228void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
229  // If the instruction is embedded into a basic block, we can find the
230  // target info for the instruction.
231  if (!TM)
232    if (const MachineInstr *MI = getParent())
233      if (const MachineBasicBlock *MBB = MI->getParent())
234        if (const MachineFunction *MF = MBB->getParent())
235          TM = &MF->getTarget();
236  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
237
238  switch (getType()) {
239  case MachineOperand::MO_Register:
240    OS << PrintReg(getReg(), TRI, getSubReg());
241
242    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
243        isEarlyClobber()) {
244      OS << '<';
245      bool NeedComma = false;
246      if (isDef()) {
247        if (NeedComma) OS << ',';
248        if (isEarlyClobber())
249          OS << "earlyclobber,";
250        if (isImplicit())
251          OS << "imp-";
252        OS << "def";
253        NeedComma = true;
254      } else if (isImplicit()) {
255          OS << "imp-use";
256          NeedComma = true;
257      }
258
259      if (isKill() || isDead() || isUndef()) {
260        if (NeedComma) OS << ',';
261        if (isKill())  OS << "kill";
262        if (isDead())  OS << "dead";
263        if (isUndef()) {
264          if (isKill() || isDead())
265            OS << ',';
266          OS << "undef";
267        }
268      }
269      OS << '>';
270    }
271    break;
272  case MachineOperand::MO_Immediate:
273    OS << getImm();
274    break;
275  case MachineOperand::MO_CImmediate:
276    getCImm()->getValue().print(OS, false);
277    break;
278  case MachineOperand::MO_FPImmediate:
279    if (getFPImm()->getType()->isFloatTy())
280      OS << getFPImm()->getValueAPF().convertToFloat();
281    else
282      OS << getFPImm()->getValueAPF().convertToDouble();
283    break;
284  case MachineOperand::MO_MachineBasicBlock:
285    OS << "<BB#" << getMBB()->getNumber() << ">";
286    break;
287  case MachineOperand::MO_FrameIndex:
288    OS << "<fi#" << getIndex() << '>';
289    break;
290  case MachineOperand::MO_ConstantPoolIndex:
291    OS << "<cp#" << getIndex();
292    if (getOffset()) OS << "+" << getOffset();
293    OS << '>';
294    break;
295  case MachineOperand::MO_JumpTableIndex:
296    OS << "<jt#" << getIndex() << '>';
297    break;
298  case MachineOperand::MO_GlobalAddress:
299    OS << "<ga:";
300    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
301    if (getOffset()) OS << "+" << getOffset();
302    OS << '>';
303    break;
304  case MachineOperand::MO_ExternalSymbol:
305    OS << "<es:" << getSymbolName();
306    if (getOffset()) OS << "+" << getOffset();
307    OS << '>';
308    break;
309  case MachineOperand::MO_BlockAddress:
310    OS << '<';
311    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
312    OS << '>';
313    break;
314  case MachineOperand::MO_Metadata:
315    OS << '<';
316    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
317    OS << '>';
318    break;
319  case MachineOperand::MO_MCSymbol:
320    OS << "<MCSym=" << *getMCSymbol() << '>';
321    break;
322  default:
323    llvm_unreachable("Unrecognized operand type");
324  }
325
326  if (unsigned TF = getTargetFlags())
327    OS << "[TF=" << TF << ']';
328}
329
330//===----------------------------------------------------------------------===//
331// MachineMemOperand Implementation
332//===----------------------------------------------------------------------===//
333
334/// getAddrSpace - Return the LLVM IR address space number that this pointer
335/// points into.
336unsigned MachinePointerInfo::getAddrSpace() const {
337  if (V == 0) return 0;
338  return cast<PointerType>(V->getType())->getAddressSpace();
339}
340
341/// getConstantPool - Return a MachinePointerInfo record that refers to the
342/// constant pool.
343MachinePointerInfo MachinePointerInfo::getConstantPool() {
344  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
345}
346
347/// getFixedStack - Return a MachinePointerInfo record that refers to the
348/// the specified FrameIndex.
349MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
350  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
351}
352
353MachinePointerInfo MachinePointerInfo::getJumpTable() {
354  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
355}
356
357MachinePointerInfo MachinePointerInfo::getGOT() {
358  return MachinePointerInfo(PseudoSourceValue::getGOT());
359}
360
361MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
362  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
363}
364
365MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
366                                     uint64_t s, unsigned int a,
367                                     const MDNode *TBAAInfo)
368  : PtrInfo(ptrinfo), Size(s),
369    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
370    TBAAInfo(TBAAInfo) {
371  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
372         "invalid pointer value");
373  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
374  assert((isLoad() || isStore()) && "Not a load/store!");
375}
376
377/// Profile - Gather unique data for the object.
378///
379void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
380  ID.AddInteger(getOffset());
381  ID.AddInteger(Size);
382  ID.AddPointer(getValue());
383  ID.AddInteger(Flags);
384}
385
386void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
387  // The Value and Offset may differ due to CSE. But the flags and size
388  // should be the same.
389  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
390  assert(MMO->getSize() == getSize() && "Size mismatch!");
391
392  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
393    // Update the alignment value.
394    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
395      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
396    // Also update the base and offset, because the new alignment may
397    // not be applicable with the old ones.
398    PtrInfo = MMO->PtrInfo;
399  }
400}
401
402/// getAlignment - Return the minimum known alignment in bytes of the
403/// actual memory reference.
404uint64_t MachineMemOperand::getAlignment() const {
405  return MinAlign(getBaseAlignment(), getOffset());
406}
407
408raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
409  assert((MMO.isLoad() || MMO.isStore()) &&
410         "SV has to be a load, store or both.");
411
412  if (MMO.isVolatile())
413    OS << "Volatile ";
414
415  if (MMO.isLoad())
416    OS << "LD";
417  if (MMO.isStore())
418    OS << "ST";
419  OS << MMO.getSize();
420
421  // Print the address information.
422  OS << "[";
423  if (!MMO.getValue())
424    OS << "<unknown>";
425  else
426    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
427
428  // If the alignment of the memory reference itself differs from the alignment
429  // of the base pointer, print the base alignment explicitly, next to the base
430  // pointer.
431  if (MMO.getBaseAlignment() != MMO.getAlignment())
432    OS << "(align=" << MMO.getBaseAlignment() << ")";
433
434  if (MMO.getOffset() != 0)
435    OS << "+" << MMO.getOffset();
436  OS << "]";
437
438  // Print the alignment of the reference.
439  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
440      MMO.getBaseAlignment() != MMO.getSize())
441    OS << "(align=" << MMO.getAlignment() << ")";
442
443  // Print TBAA info.
444  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
445    OS << "(tbaa=";
446    if (TBAAInfo->getNumOperands() > 0)
447      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
448    else
449      OS << "<unknown>";
450    OS << ")";
451  }
452
453  // Print nontemporal info.
454  if (MMO.isNonTemporal())
455    OS << "(nontemporal)";
456
457  return OS;
458}
459
460//===----------------------------------------------------------------------===//
461// MachineInstr Implementation
462//===----------------------------------------------------------------------===//
463
464/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
465/// MCID NULL and no operands.
466MachineInstr::MachineInstr()
467  : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
468    MemRefs(0), MemRefsEnd(0),
469    Parent(0) {
470  // Make sure that we get added to a machine basicblock
471  LeakDetector::addGarbageObject(this);
472}
473
474void MachineInstr::addImplicitDefUseOperands() {
475  if (MCID->ImplicitDefs)
476    for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
477      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
478  if (MCID->ImplicitUses)
479    for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
480      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
481}
482
483/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
484/// implicit operands. It reserves space for the number of operands specified by
485/// the MCInstrDesc.
486MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
487  : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
488    MemRefs(0), MemRefsEnd(0), Parent(0) {
489  if (!NoImp)
490    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
491  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
492  if (!NoImp)
493    addImplicitDefUseOperands();
494  // Make sure that we get added to a machine basicblock
495  LeakDetector::addGarbageObject(this);
496}
497
498/// MachineInstr ctor - As above, but with a DebugLoc.
499MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
500                           bool NoImp)
501  : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
502    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
503  if (!NoImp)
504    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
505  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
506  if (!NoImp)
507    addImplicitDefUseOperands();
508  // Make sure that we get added to a machine basicblock
509  LeakDetector::addGarbageObject(this);
510}
511
512/// MachineInstr ctor - Work exactly the same as the ctor two above, except
513/// that the MachineInstr is created and added to the end of the specified
514/// basic block.
515MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
516  : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
517    MemRefs(0), MemRefsEnd(0), Parent(0) {
518  assert(MBB && "Cannot use inserting ctor with null basic block!");
519  NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
520  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
521  addImplicitDefUseOperands();
522  // Make sure that we get added to a machine basicblock
523  LeakDetector::addGarbageObject(this);
524  MBB->push_back(this);  // Add instruction to end of basic block!
525}
526
527/// MachineInstr ctor - As above, but with a DebugLoc.
528///
529MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
530                           const MCInstrDesc &tid)
531  : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
532    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
533  assert(MBB && "Cannot use inserting ctor with null basic block!");
534  NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
535  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
536  addImplicitDefUseOperands();
537  // Make sure that we get added to a machine basicblock
538  LeakDetector::addGarbageObject(this);
539  MBB->push_back(this);  // Add instruction to end of basic block!
540}
541
542/// MachineInstr ctor - Copies MachineInstr arg exactly
543///
544MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
545  : MCID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
546    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
547    Parent(0), debugLoc(MI.getDebugLoc()) {
548  Operands.reserve(MI.getNumOperands());
549
550  // Add operands
551  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
552    addOperand(MI.getOperand(i));
553  NumImplicitOps = MI.NumImplicitOps;
554
555  // Copy all the flags.
556  Flags = MI.Flags;
557
558  // Set parent to null.
559  Parent = 0;
560
561  LeakDetector::addGarbageObject(this);
562}
563
564MachineInstr::~MachineInstr() {
565  LeakDetector::removeGarbageObject(this);
566#ifndef NDEBUG
567  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
568    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
569    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
570           "Reg operand def/use list corrupted");
571  }
572#endif
573}
574
575/// getRegInfo - If this instruction is embedded into a MachineFunction,
576/// return the MachineRegisterInfo object for the current function, otherwise
577/// return null.
578MachineRegisterInfo *MachineInstr::getRegInfo() {
579  if (MachineBasicBlock *MBB = getParent())
580    return &MBB->getParent()->getRegInfo();
581  return 0;
582}
583
584/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
585/// this instruction from their respective use lists.  This requires that the
586/// operands already be on their use lists.
587void MachineInstr::RemoveRegOperandsFromUseLists() {
588  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
589    if (Operands[i].isReg())
590      Operands[i].RemoveRegOperandFromRegInfo();
591  }
592}
593
594/// AddRegOperandsToUseLists - Add all of the register operands in
595/// this instruction from their respective use lists.  This requires that the
596/// operands not be on their use lists yet.
597void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
598  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
599    if (Operands[i].isReg())
600      Operands[i].AddRegOperandToRegInfo(&RegInfo);
601  }
602}
603
604
605/// addOperand - Add the specified operand to the instruction.  If it is an
606/// implicit operand, it is added to the end of the operand list.  If it is
607/// an explicit operand it is added at the end of the explicit operand list
608/// (before the first implicit operand).
609void MachineInstr::addOperand(const MachineOperand &Op) {
610  bool isImpReg = Op.isReg() && Op.isImplicit();
611  assert((isImpReg || !OperandsComplete()) &&
612         "Trying to add an operand to a machine instr that is already done!");
613
614  MachineRegisterInfo *RegInfo = getRegInfo();
615
616  // If we are adding the operand to the end of the list, our job is simpler.
617  // This is true most of the time, so this is a reasonable optimization.
618  if (isImpReg || NumImplicitOps == 0) {
619    // We can only do this optimization if we know that the operand list won't
620    // reallocate.
621    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
622      Operands.push_back(Op);
623
624      // Set the parent of the operand.
625      Operands.back().ParentMI = this;
626
627      // If the operand is a register, update the operand's use list.
628      if (Op.isReg()) {
629        Operands.back().AddRegOperandToRegInfo(RegInfo);
630        // If the register operand is flagged as early, mark the operand as such
631        unsigned OpNo = Operands.size() - 1;
632        if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
633          Operands[OpNo].setIsEarlyClobber(true);
634      }
635      return;
636    }
637  }
638
639  // Otherwise, we have to insert a real operand before any implicit ones.
640  unsigned OpNo = Operands.size()-NumImplicitOps;
641
642  // If this instruction isn't embedded into a function, then we don't need to
643  // update any operand lists.
644  if (RegInfo == 0) {
645    // Simple insertion, no reginfo update needed for other register operands.
646    Operands.insert(Operands.begin()+OpNo, Op);
647    Operands[OpNo].ParentMI = this;
648
649    // Do explicitly set the reginfo for this operand though, to ensure the
650    // next/prev fields are properly nulled out.
651    if (Operands[OpNo].isReg()) {
652      Operands[OpNo].AddRegOperandToRegInfo(0);
653      // If the register operand is flagged as early, mark the operand as such
654      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
655        Operands[OpNo].setIsEarlyClobber(true);
656    }
657
658  } else if (Operands.size()+1 <= Operands.capacity()) {
659    // Otherwise, we have to remove register operands from their register use
660    // list, add the operand, then add the register operands back to their use
661    // list.  This also must handle the case when the operand list reallocates
662    // to somewhere else.
663
664    // If insertion of this operand won't cause reallocation of the operand
665    // list, just remove the implicit operands, add the operand, then re-add all
666    // the rest of the operands.
667    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
668      assert(Operands[i].isReg() && "Should only be an implicit reg!");
669      Operands[i].RemoveRegOperandFromRegInfo();
670    }
671
672    // Add the operand.  If it is a register, add it to the reg list.
673    Operands.insert(Operands.begin()+OpNo, Op);
674    Operands[OpNo].ParentMI = this;
675
676    if (Operands[OpNo].isReg()) {
677      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
678      // If the register operand is flagged as early, mark the operand as such
679      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
680        Operands[OpNo].setIsEarlyClobber(true);
681    }
682
683    // Re-add all the implicit ops.
684    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
685      assert(Operands[i].isReg() && "Should only be an implicit reg!");
686      Operands[i].AddRegOperandToRegInfo(RegInfo);
687    }
688  } else {
689    // Otherwise, we will be reallocating the operand list.  Remove all reg
690    // operands from their list, then readd them after the operand list is
691    // reallocated.
692    RemoveRegOperandsFromUseLists();
693
694    Operands.insert(Operands.begin()+OpNo, Op);
695    Operands[OpNo].ParentMI = this;
696
697    // Re-add all the operands.
698    AddRegOperandsToUseLists(*RegInfo);
699
700      // If the register operand is flagged as early, mark the operand as such
701    if (Operands[OpNo].isReg()
702        && MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
703      Operands[OpNo].setIsEarlyClobber(true);
704  }
705}
706
707/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
708/// fewer operand than it started with.
709///
710void MachineInstr::RemoveOperand(unsigned OpNo) {
711  assert(OpNo < Operands.size() && "Invalid operand number");
712
713  // Special case removing the last one.
714  if (OpNo == Operands.size()-1) {
715    // If needed, remove from the reg def/use list.
716    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
717      Operands.back().RemoveRegOperandFromRegInfo();
718
719    Operands.pop_back();
720    return;
721  }
722
723  // Otherwise, we are removing an interior operand.  If we have reginfo to
724  // update, remove all operands that will be shifted down from their reg lists,
725  // move everything down, then re-add them.
726  MachineRegisterInfo *RegInfo = getRegInfo();
727  if (RegInfo) {
728    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
729      if (Operands[i].isReg())
730        Operands[i].RemoveRegOperandFromRegInfo();
731    }
732  }
733
734  Operands.erase(Operands.begin()+OpNo);
735
736  if (RegInfo) {
737    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
738      if (Operands[i].isReg())
739        Operands[i].AddRegOperandToRegInfo(RegInfo);
740    }
741  }
742}
743
744/// addMemOperand - Add a MachineMemOperand to the machine instruction.
745/// This function should be used only occasionally. The setMemRefs function
746/// is the primary method for setting up a MachineInstr's MemRefs list.
747void MachineInstr::addMemOperand(MachineFunction &MF,
748                                 MachineMemOperand *MO) {
749  mmo_iterator OldMemRefs = MemRefs;
750  mmo_iterator OldMemRefsEnd = MemRefsEnd;
751
752  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
753  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
754  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
755
756  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
757  NewMemRefs[NewNum - 1] = MO;
758
759  MemRefs = NewMemRefs;
760  MemRefsEnd = NewMemRefsEnd;
761}
762
763bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
764                                 MICheckType Check) const {
765  // If opcodes or number of operands are not the same then the two
766  // instructions are obviously not identical.
767  if (Other->getOpcode() != getOpcode() ||
768      Other->getNumOperands() != getNumOperands())
769    return false;
770
771  // Check operands to make sure they match.
772  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
773    const MachineOperand &MO = getOperand(i);
774    const MachineOperand &OMO = Other->getOperand(i);
775    if (!MO.isReg()) {
776      if (!MO.isIdenticalTo(OMO))
777        return false;
778      continue;
779    }
780
781    // Clients may or may not want to ignore defs when testing for equality.
782    // For example, machine CSE pass only cares about finding common
783    // subexpressions, so it's safe to ignore virtual register defs.
784    if (MO.isDef()) {
785      if (Check == IgnoreDefs)
786        continue;
787      else if (Check == IgnoreVRegDefs) {
788        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
789            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
790          if (MO.getReg() != OMO.getReg())
791            return false;
792      } else {
793        if (!MO.isIdenticalTo(OMO))
794          return false;
795        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
796          return false;
797      }
798    } else {
799      if (!MO.isIdenticalTo(OMO))
800        return false;
801      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
802        return false;
803    }
804  }
805  // If DebugLoc does not match then two dbg.values are not identical.
806  if (isDebugValue())
807    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
808        && getDebugLoc() != Other->getDebugLoc())
809      return false;
810  return true;
811}
812
813/// removeFromParent - This method unlinks 'this' from the containing basic
814/// block, and returns it, but does not delete it.
815MachineInstr *MachineInstr::removeFromParent() {
816  assert(getParent() && "Not embedded in a basic block!");
817  getParent()->remove(this);
818  return this;
819}
820
821
822/// eraseFromParent - This method unlinks 'this' from the containing basic
823/// block, and deletes it.
824void MachineInstr::eraseFromParent() {
825  assert(getParent() && "Not embedded in a basic block!");
826  getParent()->erase(this);
827}
828
829
830/// OperandComplete - Return true if it's illegal to add a new operand
831///
832bool MachineInstr::OperandsComplete() const {
833  unsigned short NumOperands = MCID->getNumOperands();
834  if (!MCID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
835    return true;  // Broken: we have all the operands of this instruction!
836  return false;
837}
838
839/// getNumExplicitOperands - Returns the number of non-implicit operands.
840///
841unsigned MachineInstr::getNumExplicitOperands() const {
842  unsigned NumOperands = MCID->getNumOperands();
843  if (!MCID->isVariadic())
844    return NumOperands;
845
846  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
847    const MachineOperand &MO = getOperand(i);
848    if (!MO.isReg() || !MO.isImplicit())
849      NumOperands++;
850  }
851  return NumOperands;
852}
853
854bool MachineInstr::isStackAligningInlineAsm() const {
855  if (isInlineAsm()) {
856    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
857    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
858      return true;
859  }
860  return false;
861}
862
863/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
864/// the specific register or -1 if it is not found. It further tightens
865/// the search criteria to a use that kills the register if isKill is true.
866int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
867                                          const TargetRegisterInfo *TRI) const {
868  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
869    const MachineOperand &MO = getOperand(i);
870    if (!MO.isReg() || !MO.isUse())
871      continue;
872    unsigned MOReg = MO.getReg();
873    if (!MOReg)
874      continue;
875    if (MOReg == Reg ||
876        (TRI &&
877         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
878         TargetRegisterInfo::isPhysicalRegister(Reg) &&
879         TRI->isSubRegister(MOReg, Reg)))
880      if (!isKill || MO.isKill())
881        return i;
882  }
883  return -1;
884}
885
886/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
887/// indicating if this instruction reads or writes Reg. This also considers
888/// partial defines.
889std::pair<bool,bool>
890MachineInstr::readsWritesVirtualRegister(unsigned Reg,
891                                         SmallVectorImpl<unsigned> *Ops) const {
892  bool PartDef = false; // Partial redefine.
893  bool FullDef = false; // Full define.
894  bool Use = false;
895
896  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
897    const MachineOperand &MO = getOperand(i);
898    if (!MO.isReg() || MO.getReg() != Reg)
899      continue;
900    if (Ops)
901      Ops->push_back(i);
902    if (MO.isUse())
903      Use |= !MO.isUndef();
904    else if (MO.getSubReg() && !MO.isUndef())
905      // A partial <def,undef> doesn't count as reading the register.
906      PartDef = true;
907    else
908      FullDef = true;
909  }
910  // A partial redefine uses Reg unless there is also a full define.
911  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
912}
913
914/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
915/// the specified register or -1 if it is not found. If isDead is true, defs
916/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
917/// also checks if there is a def of a super-register.
918int
919MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
920                                        const TargetRegisterInfo *TRI) const {
921  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
922  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
923    const MachineOperand &MO = getOperand(i);
924    if (!MO.isReg() || !MO.isDef())
925      continue;
926    unsigned MOReg = MO.getReg();
927    bool Found = (MOReg == Reg);
928    if (!Found && TRI && isPhys &&
929        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
930      if (Overlap)
931        Found = TRI->regsOverlap(MOReg, Reg);
932      else
933        Found = TRI->isSubRegister(MOReg, Reg);
934    }
935    if (Found && (!isDead || MO.isDead()))
936      return i;
937  }
938  return -1;
939}
940
941/// findFirstPredOperandIdx() - Find the index of the first operand in the
942/// operand list that is used to represent the predicate. It returns -1 if
943/// none is found.
944int MachineInstr::findFirstPredOperandIdx() const {
945  const MCInstrDesc &MCID = getDesc();
946  if (MCID.isPredicable()) {
947    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
948      if (MCID.OpInfo[i].isPredicate())
949        return i;
950  }
951
952  return -1;
953}
954
955/// isRegTiedToUseOperand - Given the index of a register def operand,
956/// check if the register def is tied to a source operand, due to either
957/// two-address elimination or inline assembly constraints. Returns the
958/// first tied use operand index by reference is UseOpIdx is not null.
959bool MachineInstr::
960isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
961  if (isInlineAsm()) {
962    assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
963    const MachineOperand &MO = getOperand(DefOpIdx);
964    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
965      return false;
966    // Determine the actual operand index that corresponds to this index.
967    unsigned DefNo = 0;
968    unsigned DefPart = 0;
969    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
970         i < e; ) {
971      const MachineOperand &FMO = getOperand(i);
972      // After the normal asm operands there may be additional imp-def regs.
973      if (!FMO.isImm())
974        return false;
975      // Skip over this def.
976      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
977      unsigned PrevDef = i + 1;
978      i = PrevDef + NumOps;
979      if (i > DefOpIdx) {
980        DefPart = DefOpIdx - PrevDef;
981        break;
982      }
983      ++DefNo;
984    }
985    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
986         i != e; ++i) {
987      const MachineOperand &FMO = getOperand(i);
988      if (!FMO.isImm())
989        continue;
990      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
991        continue;
992      unsigned Idx;
993      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
994          Idx == DefNo) {
995        if (UseOpIdx)
996          *UseOpIdx = (unsigned)i + 1 + DefPart;
997        return true;
998      }
999    }
1000    return false;
1001  }
1002
1003  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
1004  const MCInstrDesc &MCID = getDesc();
1005  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
1006    const MachineOperand &MO = getOperand(i);
1007    if (MO.isReg() && MO.isUse() &&
1008        MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
1009      if (UseOpIdx)
1010        *UseOpIdx = (unsigned)i;
1011      return true;
1012    }
1013  }
1014  return false;
1015}
1016
1017/// isRegTiedToDefOperand - Return true if the operand of the specified index
1018/// is a register use and it is tied to an def operand. It also returns the def
1019/// operand index by reference.
1020bool MachineInstr::
1021isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
1022  if (isInlineAsm()) {
1023    const MachineOperand &MO = getOperand(UseOpIdx);
1024    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
1025      return false;
1026
1027    // Find the flag operand corresponding to UseOpIdx
1028    unsigned FlagIdx, NumOps=0;
1029    for (FlagIdx = InlineAsm::MIOp_FirstOperand;
1030         FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
1031      const MachineOperand &UFMO = getOperand(FlagIdx);
1032      // After the normal asm operands there may be additional imp-def regs.
1033      if (!UFMO.isImm())
1034        return false;
1035      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1036      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1037      if (UseOpIdx < FlagIdx+NumOps+1)
1038        break;
1039    }
1040    if (FlagIdx >= UseOpIdx)
1041      return false;
1042    const MachineOperand &UFMO = getOperand(FlagIdx);
1043    unsigned DefNo;
1044    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1045      if (!DefOpIdx)
1046        return true;
1047
1048      unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1049      // Remember to adjust the index. First operand is asm string, second is
1050      // the HasSideEffects and AlignStack bits, then there is a flag for each.
1051      while (DefNo) {
1052        const MachineOperand &FMO = getOperand(DefIdx);
1053        assert(FMO.isImm());
1054        // Skip over this def.
1055        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1056        --DefNo;
1057      }
1058      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1059      return true;
1060    }
1061    return false;
1062  }
1063
1064  const MCInstrDesc &MCID = getDesc();
1065  if (UseOpIdx >= MCID.getNumOperands())
1066    return false;
1067  const MachineOperand &MO = getOperand(UseOpIdx);
1068  if (!MO.isReg() || !MO.isUse())
1069    return false;
1070  int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1071  if (DefIdx == -1)
1072    return false;
1073  if (DefOpIdx)
1074    *DefOpIdx = (unsigned)DefIdx;
1075  return true;
1076}
1077
1078/// clearKillInfo - Clears kill flags on all operands.
1079///
1080void MachineInstr::clearKillInfo() {
1081  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1082    MachineOperand &MO = getOperand(i);
1083    if (MO.isReg() && MO.isUse())
1084      MO.setIsKill(false);
1085  }
1086}
1087
1088/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1089///
1090void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1091  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1092    const MachineOperand &MO = MI->getOperand(i);
1093    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1094      continue;
1095    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1096      MachineOperand &MOp = getOperand(j);
1097      if (!MOp.isIdenticalTo(MO))
1098        continue;
1099      if (MO.isKill())
1100        MOp.setIsKill();
1101      else
1102        MOp.setIsDead();
1103      break;
1104    }
1105  }
1106}
1107
1108/// copyPredicates - Copies predicate operand(s) from MI.
1109void MachineInstr::copyPredicates(const MachineInstr *MI) {
1110  const MCInstrDesc &MCID = MI->getDesc();
1111  if (!MCID.isPredicable())
1112    return;
1113  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1114    if (MCID.OpInfo[i].isPredicate()) {
1115      // Predicated operands must be last operands.
1116      addOperand(MI->getOperand(i));
1117    }
1118  }
1119}
1120
1121void MachineInstr::substituteRegister(unsigned FromReg,
1122                                      unsigned ToReg,
1123                                      unsigned SubIdx,
1124                                      const TargetRegisterInfo &RegInfo) {
1125  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1126    if (SubIdx)
1127      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1128    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1129      MachineOperand &MO = getOperand(i);
1130      if (!MO.isReg() || MO.getReg() != FromReg)
1131        continue;
1132      MO.substPhysReg(ToReg, RegInfo);
1133    }
1134  } else {
1135    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1136      MachineOperand &MO = getOperand(i);
1137      if (!MO.isReg() || MO.getReg() != FromReg)
1138        continue;
1139      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1140    }
1141  }
1142}
1143
1144/// isSafeToMove - Return true if it is safe to move this instruction. If
1145/// SawStore is set to true, it means that there is a store (or call) between
1146/// the instruction's location and its intended destination.
1147bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1148                                AliasAnalysis *AA,
1149                                bool &SawStore) const {
1150  // Ignore stuff that we obviously can't move.
1151  if (MCID->mayStore() || MCID->isCall()) {
1152    SawStore = true;
1153    return false;
1154  }
1155
1156  if (isLabel() || isDebugValue() ||
1157      MCID->isTerminator() || hasUnmodeledSideEffects())
1158    return false;
1159
1160  // See if this instruction does a load.  If so, we have to guarantee that the
1161  // loaded value doesn't change between the load and the its intended
1162  // destination. The check for isInvariantLoad gives the targe the chance to
1163  // classify the load as always returning a constant, e.g. a constant pool
1164  // load.
1165  if (MCID->mayLoad() && !isInvariantLoad(AA))
1166    // Otherwise, this is a real load.  If there is a store between the load and
1167    // end of block, or if the load is volatile, we can't move it.
1168    return !SawStore && !hasVolatileMemoryRef();
1169
1170  return true;
1171}
1172
1173/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1174/// instruction which defined the specified register instead of copying it.
1175bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1176                                 AliasAnalysis *AA,
1177                                 unsigned DstReg) const {
1178  bool SawStore = false;
1179  if (!TII->isTriviallyReMaterializable(this, AA) ||
1180      !isSafeToMove(TII, AA, SawStore))
1181    return false;
1182  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1183    const MachineOperand &MO = getOperand(i);
1184    if (!MO.isReg())
1185      continue;
1186    // FIXME: For now, do not remat any instruction with register operands.
1187    // Later on, we can loosen the restriction is the register operands have
1188    // not been modified between the def and use. Note, this is different from
1189    // MachineSink because the code is no longer in two-address form (at least
1190    // partially).
1191    if (MO.isUse())
1192      return false;
1193    else if (!MO.isDead() && MO.getReg() != DstReg)
1194      return false;
1195  }
1196  return true;
1197}
1198
1199/// hasVolatileMemoryRef - Return true if this instruction may have a
1200/// volatile memory reference, or if the information describing the
1201/// memory reference is not available. Return false if it is known to
1202/// have no volatile memory references.
1203bool MachineInstr::hasVolatileMemoryRef() const {
1204  // An instruction known never to access memory won't have a volatile access.
1205  if (!MCID->mayStore() &&
1206      !MCID->mayLoad() &&
1207      !MCID->isCall() &&
1208      !hasUnmodeledSideEffects())
1209    return false;
1210
1211  // Otherwise, if the instruction has no memory reference information,
1212  // conservatively assume it wasn't preserved.
1213  if (memoperands_empty())
1214    return true;
1215
1216  // Check the memory reference information for volatile references.
1217  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1218    if ((*I)->isVolatile())
1219      return true;
1220
1221  return false;
1222}
1223
1224/// isInvariantLoad - Return true if this instruction is loading from a
1225/// location whose value is invariant across the function.  For example,
1226/// loading a value from the constant pool or from the argument area
1227/// of a function if it does not change.  This should only return true of
1228/// *all* loads the instruction does are invariant (if it does multiple loads).
1229bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1230  // If the instruction doesn't load at all, it isn't an invariant load.
1231  if (!MCID->mayLoad())
1232    return false;
1233
1234  // If the instruction has lost its memoperands, conservatively assume that
1235  // it may not be an invariant load.
1236  if (memoperands_empty())
1237    return false;
1238
1239  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1240
1241  for (mmo_iterator I = memoperands_begin(),
1242       E = memoperands_end(); I != E; ++I) {
1243    if ((*I)->isVolatile()) return false;
1244    if ((*I)->isStore()) return false;
1245
1246    if (const Value *V = (*I)->getValue()) {
1247      // A load from a constant PseudoSourceValue is invariant.
1248      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1249        if (PSV->isConstant(MFI))
1250          continue;
1251      // If we have an AliasAnalysis, ask it whether the memory is constant.
1252      if (AA && AA->pointsToConstantMemory(
1253                      AliasAnalysis::Location(V, (*I)->getSize(),
1254                                              (*I)->getTBAAInfo())))
1255        continue;
1256    }
1257
1258    // Otherwise assume conservatively.
1259    return false;
1260  }
1261
1262  // Everything checks out.
1263  return true;
1264}
1265
1266/// isConstantValuePHI - If the specified instruction is a PHI that always
1267/// merges together the same virtual register, return the register, otherwise
1268/// return 0.
1269unsigned MachineInstr::isConstantValuePHI() const {
1270  if (!isPHI())
1271    return 0;
1272  assert(getNumOperands() >= 3 &&
1273         "It's illegal to have a PHI without source operands");
1274
1275  unsigned Reg = getOperand(1).getReg();
1276  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1277    if (getOperand(i).getReg() != Reg)
1278      return 0;
1279  return Reg;
1280}
1281
1282bool MachineInstr::hasUnmodeledSideEffects() const {
1283  if (getDesc().hasUnmodeledSideEffects())
1284    return true;
1285  if (isInlineAsm()) {
1286    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1287    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1288      return true;
1289  }
1290
1291  return false;
1292}
1293
1294/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1295///
1296bool MachineInstr::allDefsAreDead() const {
1297  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1298    const MachineOperand &MO = getOperand(i);
1299    if (!MO.isReg() || MO.isUse())
1300      continue;
1301    if (!MO.isDead())
1302      return false;
1303  }
1304  return true;
1305}
1306
1307/// copyImplicitOps - Copy implicit register operands from specified
1308/// instruction to this instruction.
1309void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1310  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1311       i != e; ++i) {
1312    const MachineOperand &MO = MI->getOperand(i);
1313    if (MO.isReg() && MO.isImplicit())
1314      addOperand(MO);
1315  }
1316}
1317
1318void MachineInstr::dump() const {
1319  dbgs() << "  " << *this;
1320}
1321
1322static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1323                         raw_ostream &CommentOS) {
1324  const LLVMContext &Ctx = MF->getFunction()->getContext();
1325  if (!DL.isUnknown()) {          // Print source line info.
1326    DIScope Scope(DL.getScope(Ctx));
1327    // Omit the directory, because it's likely to be long and uninteresting.
1328    if (Scope.Verify())
1329      CommentOS << Scope.getFilename();
1330    else
1331      CommentOS << "<unknown>";
1332    CommentOS << ':' << DL.getLine();
1333    if (DL.getCol() != 0)
1334      CommentOS << ':' << DL.getCol();
1335    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1336    if (!InlinedAtDL.isUnknown()) {
1337      CommentOS << " @[ ";
1338      printDebugLoc(InlinedAtDL, MF, CommentOS);
1339      CommentOS << " ]";
1340    }
1341  }
1342}
1343
1344void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1345  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1346  const MachineFunction *MF = 0;
1347  const MachineRegisterInfo *MRI = 0;
1348  if (const MachineBasicBlock *MBB = getParent()) {
1349    MF = MBB->getParent();
1350    if (!TM && MF)
1351      TM = &MF->getTarget();
1352    if (MF)
1353      MRI = &MF->getRegInfo();
1354  }
1355
1356  // Save a list of virtual registers.
1357  SmallVector<unsigned, 8> VirtRegs;
1358
1359  // Print explicitly defined operands on the left of an assignment syntax.
1360  unsigned StartOp = 0, e = getNumOperands();
1361  for (; StartOp < e && getOperand(StartOp).isReg() &&
1362         getOperand(StartOp).isDef() &&
1363         !getOperand(StartOp).isImplicit();
1364       ++StartOp) {
1365    if (StartOp != 0) OS << ", ";
1366    getOperand(StartOp).print(OS, TM);
1367    unsigned Reg = getOperand(StartOp).getReg();
1368    if (TargetRegisterInfo::isVirtualRegister(Reg))
1369      VirtRegs.push_back(Reg);
1370  }
1371
1372  if (StartOp != 0)
1373    OS << " = ";
1374
1375  // Print the opcode name.
1376  OS << getDesc().getName();
1377
1378  // Print the rest of the operands.
1379  bool OmittedAnyCallClobbers = false;
1380  bool FirstOp = true;
1381  unsigned AsmDescOp = ~0u;
1382  unsigned AsmOpCount = 0;
1383
1384  if (isInlineAsm()) {
1385    // Print asm string.
1386    OS << " ";
1387    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1388
1389    // Print HasSideEffects, IsAlignStack
1390    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1391    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1392      OS << " [sideeffect]";
1393    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1394      OS << " [alignstack]";
1395
1396    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1397    FirstOp = false;
1398  }
1399
1400
1401  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1402    const MachineOperand &MO = getOperand(i);
1403
1404    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1405      VirtRegs.push_back(MO.getReg());
1406
1407    // Omit call-clobbered registers which aren't used anywhere. This makes
1408    // call instructions much less noisy on targets where calls clobber lots
1409    // of registers. Don't rely on MO.isDead() because we may be called before
1410    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1411    if (MF && getDesc().isCall() &&
1412        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1413      unsigned Reg = MO.getReg();
1414      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1415        const MachineRegisterInfo &MRI = MF->getRegInfo();
1416        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1417          bool HasAliasLive = false;
1418          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1419               unsigned AliasReg = *Alias; ++Alias)
1420            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1421              HasAliasLive = true;
1422              break;
1423            }
1424          if (!HasAliasLive) {
1425            OmittedAnyCallClobbers = true;
1426            continue;
1427          }
1428        }
1429      }
1430    }
1431
1432    if (FirstOp) FirstOp = false; else OS << ",";
1433    OS << " ";
1434    if (i < getDesc().NumOperands) {
1435      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1436      if (MCOI.isPredicate())
1437        OS << "pred:";
1438      if (MCOI.isOptionalDef())
1439        OS << "opt:";
1440    }
1441    if (isDebugValue() && MO.isMetadata()) {
1442      // Pretty print DBG_VALUE instructions.
1443      const MDNode *MD = MO.getMetadata();
1444      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1445        OS << "!\"" << MDS->getString() << '\"';
1446      else
1447        MO.print(OS, TM);
1448    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1449      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1450    } else if (i == AsmDescOp && MO.isImm()) {
1451      // Pretty print the inline asm operand descriptor.
1452      OS << '$' << AsmOpCount++;
1453      unsigned Flag = MO.getImm();
1454      switch (InlineAsm::getKind(Flag)) {
1455      case InlineAsm::Kind_RegUse:             OS << ":[reguse]"; break;
1456      case InlineAsm::Kind_RegDef:             OS << ":[regdef]"; break;
1457      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec]"; break;
1458      case InlineAsm::Kind_Clobber:            OS << ":[clobber]"; break;
1459      case InlineAsm::Kind_Imm:                OS << ":[imm]"; break;
1460      case InlineAsm::Kind_Mem:                OS << ":[mem]"; break;
1461      default: OS << ":[??" << InlineAsm::getKind(Flag) << ']'; break;
1462      }
1463
1464      unsigned TiedTo = 0;
1465      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1466        OS << " [tiedto:$" << TiedTo << ']';
1467
1468      // Compute the index of the next operand descriptor.
1469      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1470    } else
1471      MO.print(OS, TM);
1472  }
1473
1474  // Briefly indicate whether any call clobbers were omitted.
1475  if (OmittedAnyCallClobbers) {
1476    if (!FirstOp) OS << ",";
1477    OS << " ...";
1478  }
1479
1480  bool HaveSemi = false;
1481  if (Flags) {
1482    if (!HaveSemi) OS << ";"; HaveSemi = true;
1483    OS << " flags: ";
1484
1485    if (Flags & FrameSetup)
1486      OS << "FrameSetup";
1487  }
1488
1489  if (!memoperands_empty()) {
1490    if (!HaveSemi) OS << ";"; HaveSemi = true;
1491
1492    OS << " mem:";
1493    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1494         i != e; ++i) {
1495      OS << **i;
1496      if (llvm::next(i) != e)
1497        OS << " ";
1498    }
1499  }
1500
1501  // Print the regclass of any virtual registers encountered.
1502  if (MRI && !VirtRegs.empty()) {
1503    if (!HaveSemi) OS << ";"; HaveSemi = true;
1504    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1505      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1506      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1507      for (unsigned j = i+1; j != VirtRegs.size();) {
1508        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1509          ++j;
1510          continue;
1511        }
1512        if (VirtRegs[i] != VirtRegs[j])
1513          OS << "," << PrintReg(VirtRegs[j]);
1514        VirtRegs.erase(VirtRegs.begin()+j);
1515      }
1516    }
1517  }
1518
1519  // Print debug location information.
1520  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1521    if (!HaveSemi) OS << ";"; HaveSemi = true;
1522    DIVariable DV(getOperand(e - 1).getMetadata());
1523    OS << " line no:" <<  DV.getLineNumber();
1524    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1525      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1526      if (!InlinedAtDL.isUnknown()) {
1527        OS << " inlined @[ ";
1528        printDebugLoc(InlinedAtDL, MF, OS);
1529        OS << " ]";
1530      }
1531    }
1532  } else if (!debugLoc.isUnknown() && MF) {
1533    if (!HaveSemi) OS << ";"; HaveSemi = true;
1534    OS << " dbg:";
1535    printDebugLoc(debugLoc, MF, OS);
1536  }
1537
1538  OS << '\n';
1539}
1540
1541bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1542                                     const TargetRegisterInfo *RegInfo,
1543                                     bool AddIfNotFound) {
1544  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1545  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1546  bool Found = false;
1547  SmallVector<unsigned,4> DeadOps;
1548  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1549    MachineOperand &MO = getOperand(i);
1550    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1551      continue;
1552    unsigned Reg = MO.getReg();
1553    if (!Reg)
1554      continue;
1555
1556    if (Reg == IncomingReg) {
1557      if (!Found) {
1558        if (MO.isKill())
1559          // The register is already marked kill.
1560          return true;
1561        if (isPhysReg && isRegTiedToDefOperand(i))
1562          // Two-address uses of physregs must not be marked kill.
1563          return true;
1564        MO.setIsKill();
1565        Found = true;
1566      }
1567    } else if (hasAliases && MO.isKill() &&
1568               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1569      // A super-register kill already exists.
1570      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1571        return true;
1572      if (RegInfo->isSubRegister(IncomingReg, Reg))
1573        DeadOps.push_back(i);
1574    }
1575  }
1576
1577  // Trim unneeded kill operands.
1578  while (!DeadOps.empty()) {
1579    unsigned OpIdx = DeadOps.back();
1580    if (getOperand(OpIdx).isImplicit())
1581      RemoveOperand(OpIdx);
1582    else
1583      getOperand(OpIdx).setIsKill(false);
1584    DeadOps.pop_back();
1585  }
1586
1587  // If not found, this means an alias of one of the operands is killed. Add a
1588  // new implicit operand if required.
1589  if (!Found && AddIfNotFound) {
1590    addOperand(MachineOperand::CreateReg(IncomingReg,
1591                                         false /*IsDef*/,
1592                                         true  /*IsImp*/,
1593                                         true  /*IsKill*/));
1594    return true;
1595  }
1596  return Found;
1597}
1598
1599bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1600                                   const TargetRegisterInfo *RegInfo,
1601                                   bool AddIfNotFound) {
1602  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1603  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1604  bool Found = false;
1605  SmallVector<unsigned,4> DeadOps;
1606  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1607    MachineOperand &MO = getOperand(i);
1608    if (!MO.isReg() || !MO.isDef())
1609      continue;
1610    unsigned Reg = MO.getReg();
1611    if (!Reg)
1612      continue;
1613
1614    if (Reg == IncomingReg) {
1615      MO.setIsDead();
1616      Found = true;
1617    } else if (hasAliases && MO.isDead() &&
1618               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1619      // There exists a super-register that's marked dead.
1620      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1621        return true;
1622      if (RegInfo->getSubRegisters(IncomingReg) &&
1623          RegInfo->getSuperRegisters(Reg) &&
1624          RegInfo->isSubRegister(IncomingReg, Reg))
1625        DeadOps.push_back(i);
1626    }
1627  }
1628
1629  // Trim unneeded dead operands.
1630  while (!DeadOps.empty()) {
1631    unsigned OpIdx = DeadOps.back();
1632    if (getOperand(OpIdx).isImplicit())
1633      RemoveOperand(OpIdx);
1634    else
1635      getOperand(OpIdx).setIsDead(false);
1636    DeadOps.pop_back();
1637  }
1638
1639  // If not found, this means an alias of one of the operands is dead. Add a
1640  // new implicit operand if required.
1641  if (Found || !AddIfNotFound)
1642    return Found;
1643
1644  addOperand(MachineOperand::CreateReg(IncomingReg,
1645                                       true  /*IsDef*/,
1646                                       true  /*IsImp*/,
1647                                       false /*IsKill*/,
1648                                       true  /*IsDead*/));
1649  return true;
1650}
1651
1652void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1653                                      const TargetRegisterInfo *RegInfo) {
1654  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1655    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1656    if (MO)
1657      return;
1658  } else {
1659    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1660      const MachineOperand &MO = getOperand(i);
1661      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1662          MO.getSubReg() == 0)
1663        return;
1664    }
1665  }
1666  addOperand(MachineOperand::CreateReg(IncomingReg,
1667                                       true  /*IsDef*/,
1668                                       true  /*IsImp*/));
1669}
1670
1671void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1672                                         const TargetRegisterInfo &TRI) {
1673  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1674    MachineOperand &MO = getOperand(i);
1675    if (!MO.isReg() || !MO.isDef()) continue;
1676    unsigned Reg = MO.getReg();
1677    if (Reg == 0) continue;
1678    bool Dead = true;
1679    for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1680         E = UsedRegs.end(); I != E; ++I)
1681      if (TRI.regsOverlap(*I, Reg)) {
1682        Dead = false;
1683        break;
1684      }
1685    // If there are no uses, including partial uses, the def is dead.
1686    if (Dead) MO.setIsDead();
1687  }
1688}
1689
1690unsigned
1691MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1692  unsigned Hash = MI->getOpcode() * 37;
1693  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1694    const MachineOperand &MO = MI->getOperand(i);
1695    uint64_t Key = (uint64_t)MO.getType() << 32;
1696    switch (MO.getType()) {
1697    default: break;
1698    case MachineOperand::MO_Register:
1699      if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1700        continue;  // Skip virtual register defs.
1701      Key |= MO.getReg();
1702      break;
1703    case MachineOperand::MO_Immediate:
1704      Key |= MO.getImm();
1705      break;
1706    case MachineOperand::MO_FrameIndex:
1707    case MachineOperand::MO_ConstantPoolIndex:
1708    case MachineOperand::MO_JumpTableIndex:
1709      Key |= MO.getIndex();
1710      break;
1711    case MachineOperand::MO_MachineBasicBlock:
1712      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1713      break;
1714    case MachineOperand::MO_GlobalAddress:
1715      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1716      break;
1717    case MachineOperand::MO_BlockAddress:
1718      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1719      break;
1720    case MachineOperand::MO_MCSymbol:
1721      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1722      break;
1723    }
1724    Key += ~(Key << 32);
1725    Key ^= (Key >> 22);
1726    Key += ~(Key << 13);
1727    Key ^= (Key >> 8);
1728    Key += (Key << 3);
1729    Key ^= (Key >> 15);
1730    Key += ~(Key << 27);
1731    Key ^= (Key >> 31);
1732    Hash = (unsigned)Key + Hash * 37;
1733  }
1734  return Hash;
1735}
1736
1737void MachineInstr::emitError(StringRef Msg) const {
1738  // Find the source location cookie.
1739  unsigned LocCookie = 0;
1740  const MDNode *LocMD = 0;
1741  for (unsigned i = getNumOperands(); i != 0; --i) {
1742    if (getOperand(i-1).isMetadata() &&
1743        (LocMD = getOperand(i-1).getMetadata()) &&
1744        LocMD->getNumOperands() != 0) {
1745      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1746        LocCookie = CI->getZExtValue();
1747        break;
1748      }
1749    }
1750  }
1751
1752  if (const MachineBasicBlock *MBB = getParent())
1753    if (const MachineFunction *MF = MBB->getParent())
1754      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1755  report_fatal_error(Msg);
1756}
1757