MachineInstr.cpp revision 228c8d1ff62ec211a56d9af228c272e56bc7ad96 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/Metadata.h"
19#include "llvm/Type.h"
20#include "llvm/Value.h"
21#include "llvm/Assembly/Writer.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetInstrDesc.h"
31#include "llvm/Target/TargetRegisterInfo.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/DebugInfo.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/FoldingSet.h"
40using namespace llvm;
41
42//===----------------------------------------------------------------------===//
43// MachineOperand Implementation
44//===----------------------------------------------------------------------===//
45
46/// AddRegOperandToRegInfo - Add this register operand to the specified
47/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
48/// explicitly nulled out.
49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50  assert(isReg() && "Can only add reg operand to use lists");
51
52  // If the reginfo pointer is null, just explicitly null out or next/prev
53  // pointers, to ensure they are not garbage.
54  if (RegInfo == 0) {
55    Contents.Reg.Prev = 0;
56    Contents.Reg.Next = 0;
57    return;
58  }
59
60  // Otherwise, add this operand to the head of the registers use/def list.
61  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
62
63  // For SSA values, we prefer to keep the definition at the start of the list.
64  // we do this by skipping over the definition if it is at the head of the
65  // list.
66  if (*Head && (*Head)->isDef())
67    Head = &(*Head)->Contents.Reg.Next;
68
69  Contents.Reg.Next = *Head;
70  if (Contents.Reg.Next) {
71    assert(getReg() == Contents.Reg.Next->getReg() &&
72           "Different regs on the same list!");
73    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
74  }
75
76  Contents.Reg.Prev = Head;
77  *Head = this;
78}
79
80/// RemoveRegOperandFromRegInfo - Remove this register operand from the
81/// MachineRegisterInfo it is linked with.
82void MachineOperand::RemoveRegOperandFromRegInfo() {
83  assert(isOnRegUseList() && "Reg operand is not on a use list");
84  // Unlink this from the doubly linked list of operands.
85  MachineOperand *NextOp = Contents.Reg.Next;
86  *Contents.Reg.Prev = NextOp;
87  if (NextOp) {
88    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90  }
91  Contents.Reg.Prev = 0;
92  Contents.Reg.Next = 0;
93}
94
95void MachineOperand::setReg(unsigned Reg) {
96  if (getReg() == Reg) return; // No change.
97
98  // Otherwise, we have to change the register.  If this operand is embedded
99  // into a machine function, we need to update the old and new register's
100  // use/def lists.
101  if (MachineInstr *MI = getParent())
102    if (MachineBasicBlock *MBB = MI->getParent())
103      if (MachineFunction *MF = MBB->getParent()) {
104        RemoveRegOperandFromRegInfo();
105        SmallContents.RegNo = Reg;
106        AddRegOperandToRegInfo(&MF->getRegInfo());
107        return;
108      }
109
110  // Otherwise, just change the register, no problem.  :)
111  SmallContents.RegNo = Reg;
112}
113
114void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115                                  const TargetRegisterInfo &TRI) {
116  assert(TargetRegisterInfo::isVirtualRegister(Reg));
117  if (SubIdx && getSubReg())
118    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
119  setReg(Reg);
120  if (SubIdx)
121    setSubReg(SubIdx);
122}
123
124void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
126  if (getSubReg()) {
127    Reg = TRI.getSubReg(Reg, getSubReg());
128    assert(Reg && "Invalid SubReg for physical register");
129    setSubReg(0);
130  }
131  setReg(Reg);
132}
133
134/// ChangeToImmediate - Replace this operand with a new immediate operand of
135/// the specified value.  If an operand is known to be an immediate already,
136/// the setImm method should be used.
137void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
138  // If this operand is currently a register operand, and if this is in a
139  // function, deregister the operand from the register's use/def list.
140  if (isReg() && getParent() && getParent()->getParent() &&
141      getParent()->getParent()->getParent())
142    RemoveRegOperandFromRegInfo();
143
144  OpKind = MO_Immediate;
145  Contents.ImmVal = ImmVal;
146}
147
148/// ChangeToRegister - Replace this operand with a new register operand of
149/// the specified value.  If an operand is known to be an register already,
150/// the setReg method should be used.
151void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
152                                      bool isKill, bool isDead, bool isUndef,
153                                      bool isDebug) {
154  // If this operand is already a register operand, use setReg to update the
155  // register's use/def lists.
156  if (isReg()) {
157    assert(!isEarlyClobber());
158    setReg(Reg);
159  } else {
160    // Otherwise, change this to a register and set the reg#.
161    OpKind = MO_Register;
162    SmallContents.RegNo = Reg;
163
164    // If this operand is embedded in a function, add the operand to the
165    // register's use/def list.
166    if (MachineInstr *MI = getParent())
167      if (MachineBasicBlock *MBB = MI->getParent())
168        if (MachineFunction *MF = MBB->getParent())
169          AddRegOperandToRegInfo(&MF->getRegInfo());
170  }
171
172  IsDef = isDef;
173  IsImp = isImp;
174  IsKill = isKill;
175  IsDead = isDead;
176  IsUndef = isUndef;
177  IsEarlyClobber = false;
178  IsDebug = isDebug;
179  SubReg = 0;
180}
181
182/// isIdenticalTo - Return true if this operand is identical to the specified
183/// operand.
184bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
185  if (getType() != Other.getType() ||
186      getTargetFlags() != Other.getTargetFlags())
187    return false;
188
189  switch (getType()) {
190  default: llvm_unreachable("Unrecognized operand type");
191  case MachineOperand::MO_Register:
192    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
193           getSubReg() == Other.getSubReg();
194  case MachineOperand::MO_Immediate:
195    return getImm() == Other.getImm();
196  case MachineOperand::MO_FPImmediate:
197    return getFPImm() == Other.getFPImm();
198  case MachineOperand::MO_MachineBasicBlock:
199    return getMBB() == Other.getMBB();
200  case MachineOperand::MO_FrameIndex:
201    return getIndex() == Other.getIndex();
202  case MachineOperand::MO_ConstantPoolIndex:
203    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
204  case MachineOperand::MO_JumpTableIndex:
205    return getIndex() == Other.getIndex();
206  case MachineOperand::MO_GlobalAddress:
207    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
208  case MachineOperand::MO_ExternalSymbol:
209    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
210           getOffset() == Other.getOffset();
211  case MachineOperand::MO_BlockAddress:
212    return getBlockAddress() == Other.getBlockAddress();
213  case MachineOperand::MO_MCSymbol:
214    return getMCSymbol() == Other.getMCSymbol();
215  case MachineOperand::MO_Metadata:
216    return getMetadata() == Other.getMetadata();
217  }
218}
219
220/// print - Print the specified machine operand.
221///
222void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
223  // If the instruction is embedded into a basic block, we can find the
224  // target info for the instruction.
225  if (!TM)
226    if (const MachineInstr *MI = getParent())
227      if (const MachineBasicBlock *MBB = MI->getParent())
228        if (const MachineFunction *MF = MBB->getParent())
229          TM = &MF->getTarget();
230
231  switch (getType()) {
232  case MachineOperand::MO_Register:
233    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
234      OS << "%reg" << getReg();
235    } else {
236      if (TM)
237        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
238      else
239        OS << "%physreg" << getReg();
240    }
241
242    if (getSubReg() != 0) {
243      if (TM)
244        OS << ':' << TM->getRegisterInfo()->getSubRegIndexName(getSubReg());
245      else
246        OS << ':' << getSubReg();
247    }
248
249    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
250        isEarlyClobber()) {
251      OS << '<';
252      bool NeedComma = false;
253      if (isDef()) {
254        if (NeedComma) OS << ',';
255        if (isEarlyClobber())
256          OS << "earlyclobber,";
257        if (isImplicit())
258          OS << "imp-";
259        OS << "def";
260        NeedComma = true;
261      } else if (isImplicit()) {
262          OS << "imp-use";
263          NeedComma = true;
264      }
265
266      if (isKill() || isDead() || isUndef()) {
267        if (NeedComma) OS << ',';
268        if (isKill())  OS << "kill";
269        if (isDead())  OS << "dead";
270        if (isUndef()) {
271          if (isKill() || isDead())
272            OS << ',';
273          OS << "undef";
274        }
275      }
276      OS << '>';
277    }
278    break;
279  case MachineOperand::MO_Immediate:
280    OS << getImm();
281    break;
282  case MachineOperand::MO_FPImmediate:
283    if (getFPImm()->getType()->isFloatTy())
284      OS << getFPImm()->getValueAPF().convertToFloat();
285    else
286      OS << getFPImm()->getValueAPF().convertToDouble();
287    break;
288  case MachineOperand::MO_MachineBasicBlock:
289    OS << "<BB#" << getMBB()->getNumber() << ">";
290    break;
291  case MachineOperand::MO_FrameIndex:
292    OS << "<fi#" << getIndex() << '>';
293    break;
294  case MachineOperand::MO_ConstantPoolIndex:
295    OS << "<cp#" << getIndex();
296    if (getOffset()) OS << "+" << getOffset();
297    OS << '>';
298    break;
299  case MachineOperand::MO_JumpTableIndex:
300    OS << "<jt#" << getIndex() << '>';
301    break;
302  case MachineOperand::MO_GlobalAddress:
303    OS << "<ga:";
304    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
305    if (getOffset()) OS << "+" << getOffset();
306    OS << '>';
307    break;
308  case MachineOperand::MO_ExternalSymbol:
309    OS << "<es:" << getSymbolName();
310    if (getOffset()) OS << "+" << getOffset();
311    OS << '>';
312    break;
313  case MachineOperand::MO_BlockAddress:
314    OS << '<';
315    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
316    OS << '>';
317    break;
318  case MachineOperand::MO_Metadata:
319    OS << '<';
320    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
321    OS << '>';
322    break;
323  case MachineOperand::MO_MCSymbol:
324    OS << "<MCSym=" << *getMCSymbol() << '>';
325    break;
326  default:
327    llvm_unreachable("Unrecognized operand type");
328  }
329
330  if (unsigned TF = getTargetFlags())
331    OS << "[TF=" << TF << ']';
332}
333
334//===----------------------------------------------------------------------===//
335// MachineMemOperand Implementation
336//===----------------------------------------------------------------------===//
337
338/// getAddrSpace - Return the LLVM IR address space number that this pointer
339/// points into.
340unsigned MachinePointerInfo::getAddrSpace() const {
341  if (V == 0) return 0;
342  return cast<PointerType>(V->getType())->getAddressSpace();
343}
344
345/// getConstantPool - Return a MachinePointerInfo record that refers to the
346/// constant pool.
347MachinePointerInfo MachinePointerInfo::getConstantPool() {
348  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
349}
350
351/// getFixedStack - Return a MachinePointerInfo record that refers to the
352/// the specified FrameIndex.
353MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
354  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
355}
356
357MachinePointerInfo MachinePointerInfo::getJumpTable() {
358  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
359}
360
361MachinePointerInfo MachinePointerInfo::getGOT() {
362  return MachinePointerInfo(PseudoSourceValue::getGOT());
363}
364
365MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
366  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
367}
368
369MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
370                                     uint64_t s, unsigned int a,
371                                     const MDNode *TBAAInfo)
372  : PtrInfo(ptrinfo), Size(s),
373    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
374    TBAAInfo(TBAAInfo) {
375  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
376         "invalid pointer value");
377  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
378  assert((isLoad() || isStore()) && "Not a load/store!");
379}
380
381/// Profile - Gather unique data for the object.
382///
383void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
384  ID.AddInteger(getOffset());
385  ID.AddInteger(Size);
386  ID.AddPointer(getValue());
387  ID.AddInteger(Flags);
388}
389
390void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
391  // The Value and Offset may differ due to CSE. But the flags and size
392  // should be the same.
393  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
394  assert(MMO->getSize() == getSize() && "Size mismatch!");
395
396  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
397    // Update the alignment value.
398    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
399      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
400    // Also update the base and offset, because the new alignment may
401    // not be applicable with the old ones.
402    PtrInfo = MMO->PtrInfo;
403  }
404}
405
406/// getAlignment - Return the minimum known alignment in bytes of the
407/// actual memory reference.
408uint64_t MachineMemOperand::getAlignment() const {
409  return MinAlign(getBaseAlignment(), getOffset());
410}
411
412raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
413  assert((MMO.isLoad() || MMO.isStore()) &&
414         "SV has to be a load, store or both.");
415
416  if (MMO.isVolatile())
417    OS << "Volatile ";
418
419  if (MMO.isLoad())
420    OS << "LD";
421  if (MMO.isStore())
422    OS << "ST";
423  OS << MMO.getSize();
424
425  // Print the address information.
426  OS << "[";
427  if (!MMO.getValue())
428    OS << "<unknown>";
429  else
430    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
431
432  // If the alignment of the memory reference itself differs from the alignment
433  // of the base pointer, print the base alignment explicitly, next to the base
434  // pointer.
435  if (MMO.getBaseAlignment() != MMO.getAlignment())
436    OS << "(align=" << MMO.getBaseAlignment() << ")";
437
438  if (MMO.getOffset() != 0)
439    OS << "+" << MMO.getOffset();
440  OS << "]";
441
442  // Print the alignment of the reference.
443  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
444      MMO.getBaseAlignment() != MMO.getSize())
445    OS << "(align=" << MMO.getAlignment() << ")";
446
447  // Print TBAA info.
448  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
449    OS << "(tbaa=";
450    if (TBAAInfo->getNumOperands() > 0)
451      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
452    else
453      OS << "<unknown>";
454    OS << ")";
455  }
456
457  return OS;
458}
459
460//===----------------------------------------------------------------------===//
461// MachineInstr Implementation
462//===----------------------------------------------------------------------===//
463
464/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
465/// TID NULL and no operands.
466MachineInstr::MachineInstr()
467  : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
468    Parent(0) {
469  // Make sure that we get added to a machine basicblock
470  LeakDetector::addGarbageObject(this);
471}
472
473void MachineInstr::addImplicitDefUseOperands() {
474  if (TID->ImplicitDefs)
475    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
476      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
477  if (TID->ImplicitUses)
478    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
479      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
480}
481
482/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
483/// implicit operands. It reserves space for the number of operands specified by
484/// the TargetInstrDesc.
485MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
486  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
487    MemRefs(0), MemRefsEnd(0), Parent(0) {
488  if (!NoImp)
489    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
490  Operands.reserve(NumImplicitOps + TID->getNumOperands());
491  if (!NoImp)
492    addImplicitDefUseOperands();
493  // Make sure that we get added to a machine basicblock
494  LeakDetector::addGarbageObject(this);
495}
496
497/// MachineInstr ctor - As above, but with a DebugLoc.
498MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
499                           bool NoImp)
500  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
501    Parent(0), debugLoc(dl) {
502  if (!NoImp)
503    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
504  Operands.reserve(NumImplicitOps + TID->getNumOperands());
505  if (!NoImp)
506    addImplicitDefUseOperands();
507  // Make sure that we get added to a machine basicblock
508  LeakDetector::addGarbageObject(this);
509}
510
511/// MachineInstr ctor - Work exactly the same as the ctor two above, except
512/// that the MachineInstr is created and added to the end of the specified
513/// basic block.
514MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
515  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
516    MemRefs(0), MemRefsEnd(0), Parent(0) {
517  assert(MBB && "Cannot use inserting ctor with null basic block!");
518  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
519  Operands.reserve(NumImplicitOps + TID->getNumOperands());
520  addImplicitDefUseOperands();
521  // Make sure that we get added to a machine basicblock
522  LeakDetector::addGarbageObject(this);
523  MBB->push_back(this);  // Add instruction to end of basic block!
524}
525
526/// MachineInstr ctor - As above, but with a DebugLoc.
527///
528MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
529                           const TargetInstrDesc &tid)
530  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
531    Parent(0), debugLoc(dl) {
532  assert(MBB && "Cannot use inserting ctor with null basic block!");
533  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
534  Operands.reserve(NumImplicitOps + TID->getNumOperands());
535  addImplicitDefUseOperands();
536  // Make sure that we get added to a machine basicblock
537  LeakDetector::addGarbageObject(this);
538  MBB->push_back(this);  // Add instruction to end of basic block!
539}
540
541/// MachineInstr ctor - Copies MachineInstr arg exactly
542///
543MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
544  : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
545    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
546    Parent(0), debugLoc(MI.getDebugLoc()) {
547  Operands.reserve(MI.getNumOperands());
548
549  // Add operands
550  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
551    addOperand(MI.getOperand(i));
552  NumImplicitOps = MI.NumImplicitOps;
553
554  // Set parent to null.
555  Parent = 0;
556
557  LeakDetector::addGarbageObject(this);
558}
559
560MachineInstr::~MachineInstr() {
561  LeakDetector::removeGarbageObject(this);
562#ifndef NDEBUG
563  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
564    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
565    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
566           "Reg operand def/use list corrupted");
567  }
568#endif
569}
570
571/// getRegInfo - If this instruction is embedded into a MachineFunction,
572/// return the MachineRegisterInfo object for the current function, otherwise
573/// return null.
574MachineRegisterInfo *MachineInstr::getRegInfo() {
575  if (MachineBasicBlock *MBB = getParent())
576    return &MBB->getParent()->getRegInfo();
577  return 0;
578}
579
580/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
581/// this instruction from their respective use lists.  This requires that the
582/// operands already be on their use lists.
583void MachineInstr::RemoveRegOperandsFromUseLists() {
584  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
585    if (Operands[i].isReg())
586      Operands[i].RemoveRegOperandFromRegInfo();
587  }
588}
589
590/// AddRegOperandsToUseLists - Add all of the register operands in
591/// this instruction from their respective use lists.  This requires that the
592/// operands not be on their use lists yet.
593void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
594  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
595    if (Operands[i].isReg())
596      Operands[i].AddRegOperandToRegInfo(&RegInfo);
597  }
598}
599
600
601/// addOperand - Add the specified operand to the instruction.  If it is an
602/// implicit operand, it is added to the end of the operand list.  If it is
603/// an explicit operand it is added at the end of the explicit operand list
604/// (before the first implicit operand).
605void MachineInstr::addOperand(const MachineOperand &Op) {
606  bool isImpReg = Op.isReg() && Op.isImplicit();
607  assert((isImpReg || !OperandsComplete()) &&
608         "Trying to add an operand to a machine instr that is already done!");
609
610  MachineRegisterInfo *RegInfo = getRegInfo();
611
612  // If we are adding the operand to the end of the list, our job is simpler.
613  // This is true most of the time, so this is a reasonable optimization.
614  if (isImpReg || NumImplicitOps == 0) {
615    // We can only do this optimization if we know that the operand list won't
616    // reallocate.
617    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
618      Operands.push_back(Op);
619
620      // Set the parent of the operand.
621      Operands.back().ParentMI = this;
622
623      // If the operand is a register, update the operand's use list.
624      if (Op.isReg()) {
625        Operands.back().AddRegOperandToRegInfo(RegInfo);
626        // If the register operand is flagged as early, mark the operand as such
627        unsigned OpNo = Operands.size() - 1;
628        if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
629          Operands[OpNo].setIsEarlyClobber(true);
630      }
631      return;
632    }
633  }
634
635  // Otherwise, we have to insert a real operand before any implicit ones.
636  unsigned OpNo = Operands.size()-NumImplicitOps;
637
638  // If this instruction isn't embedded into a function, then we don't need to
639  // update any operand lists.
640  if (RegInfo == 0) {
641    // Simple insertion, no reginfo update needed for other register operands.
642    Operands.insert(Operands.begin()+OpNo, Op);
643    Operands[OpNo].ParentMI = this;
644
645    // Do explicitly set the reginfo for this operand though, to ensure the
646    // next/prev fields are properly nulled out.
647    if (Operands[OpNo].isReg()) {
648      Operands[OpNo].AddRegOperandToRegInfo(0);
649      // If the register operand is flagged as early, mark the operand as such
650      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
651        Operands[OpNo].setIsEarlyClobber(true);
652    }
653
654  } else if (Operands.size()+1 <= Operands.capacity()) {
655    // Otherwise, we have to remove register operands from their register use
656    // list, add the operand, then add the register operands back to their use
657    // list.  This also must handle the case when the operand list reallocates
658    // to somewhere else.
659
660    // If insertion of this operand won't cause reallocation of the operand
661    // list, just remove the implicit operands, add the operand, then re-add all
662    // the rest of the operands.
663    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
664      assert(Operands[i].isReg() && "Should only be an implicit reg!");
665      Operands[i].RemoveRegOperandFromRegInfo();
666    }
667
668    // Add the operand.  If it is a register, add it to the reg list.
669    Operands.insert(Operands.begin()+OpNo, Op);
670    Operands[OpNo].ParentMI = this;
671
672    if (Operands[OpNo].isReg()) {
673      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
674      // If the register operand is flagged as early, mark the operand as such
675      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
676        Operands[OpNo].setIsEarlyClobber(true);
677    }
678
679    // Re-add all the implicit ops.
680    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
681      assert(Operands[i].isReg() && "Should only be an implicit reg!");
682      Operands[i].AddRegOperandToRegInfo(RegInfo);
683    }
684  } else {
685    // Otherwise, we will be reallocating the operand list.  Remove all reg
686    // operands from their list, then readd them after the operand list is
687    // reallocated.
688    RemoveRegOperandsFromUseLists();
689
690    Operands.insert(Operands.begin()+OpNo, Op);
691    Operands[OpNo].ParentMI = this;
692
693    // Re-add all the operands.
694    AddRegOperandsToUseLists(*RegInfo);
695
696      // If the register operand is flagged as early, mark the operand as such
697    if (Operands[OpNo].isReg()
698        && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
699      Operands[OpNo].setIsEarlyClobber(true);
700  }
701}
702
703/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
704/// fewer operand than it started with.
705///
706void MachineInstr::RemoveOperand(unsigned OpNo) {
707  assert(OpNo < Operands.size() && "Invalid operand number");
708
709  // Special case removing the last one.
710  if (OpNo == Operands.size()-1) {
711    // If needed, remove from the reg def/use list.
712    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
713      Operands.back().RemoveRegOperandFromRegInfo();
714
715    Operands.pop_back();
716    return;
717  }
718
719  // Otherwise, we are removing an interior operand.  If we have reginfo to
720  // update, remove all operands that will be shifted down from their reg lists,
721  // move everything down, then re-add them.
722  MachineRegisterInfo *RegInfo = getRegInfo();
723  if (RegInfo) {
724    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
725      if (Operands[i].isReg())
726        Operands[i].RemoveRegOperandFromRegInfo();
727    }
728  }
729
730  Operands.erase(Operands.begin()+OpNo);
731
732  if (RegInfo) {
733    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
734      if (Operands[i].isReg())
735        Operands[i].AddRegOperandToRegInfo(RegInfo);
736    }
737  }
738}
739
740/// addMemOperand - Add a MachineMemOperand to the machine instruction.
741/// This function should be used only occasionally. The setMemRefs function
742/// is the primary method for setting up a MachineInstr's MemRefs list.
743void MachineInstr::addMemOperand(MachineFunction &MF,
744                                 MachineMemOperand *MO) {
745  mmo_iterator OldMemRefs = MemRefs;
746  mmo_iterator OldMemRefsEnd = MemRefsEnd;
747
748  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
749  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
750  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
751
752  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
753  NewMemRefs[NewNum - 1] = MO;
754
755  MemRefs = NewMemRefs;
756  MemRefsEnd = NewMemRefsEnd;
757}
758
759bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
760                                 MICheckType Check) const {
761  // If opcodes or number of operands are not the same then the two
762  // instructions are obviously not identical.
763  if (Other->getOpcode() != getOpcode() ||
764      Other->getNumOperands() != getNumOperands())
765    return false;
766
767  // Check operands to make sure they match.
768  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
769    const MachineOperand &MO = getOperand(i);
770    const MachineOperand &OMO = Other->getOperand(i);
771    // Clients may or may not want to ignore defs when testing for equality.
772    // For example, machine CSE pass only cares about finding common
773    // subexpressions, so it's safe to ignore virtual register defs.
774    if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
775      if (Check == IgnoreDefs)
776        continue;
777      // Check == IgnoreVRegDefs
778      if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
779          TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
780        if (MO.getReg() != OMO.getReg())
781          return false;
782    } else if (!MO.isIdenticalTo(OMO))
783      return false;
784  }
785  return true;
786}
787
788/// removeFromParent - This method unlinks 'this' from the containing basic
789/// block, and returns it, but does not delete it.
790MachineInstr *MachineInstr::removeFromParent() {
791  assert(getParent() && "Not embedded in a basic block!");
792  getParent()->remove(this);
793  return this;
794}
795
796
797/// eraseFromParent - This method unlinks 'this' from the containing basic
798/// block, and deletes it.
799void MachineInstr::eraseFromParent() {
800  assert(getParent() && "Not embedded in a basic block!");
801  getParent()->erase(this);
802}
803
804
805/// OperandComplete - Return true if it's illegal to add a new operand
806///
807bool MachineInstr::OperandsComplete() const {
808  unsigned short NumOperands = TID->getNumOperands();
809  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
810    return true;  // Broken: we have all the operands of this instruction!
811  return false;
812}
813
814/// getNumExplicitOperands - Returns the number of non-implicit operands.
815///
816unsigned MachineInstr::getNumExplicitOperands() const {
817  unsigned NumOperands = TID->getNumOperands();
818  if (!TID->isVariadic())
819    return NumOperands;
820
821  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
822    const MachineOperand &MO = getOperand(i);
823    if (!MO.isReg() || !MO.isImplicit())
824      NumOperands++;
825  }
826  return NumOperands;
827}
828
829
830/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
831/// the specific register or -1 if it is not found. It further tightens
832/// the search criteria to a use that kills the register if isKill is true.
833int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
834                                          const TargetRegisterInfo *TRI) const {
835  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
836    const MachineOperand &MO = getOperand(i);
837    if (!MO.isReg() || !MO.isUse())
838      continue;
839    unsigned MOReg = MO.getReg();
840    if (!MOReg)
841      continue;
842    if (MOReg == Reg ||
843        (TRI &&
844         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
845         TargetRegisterInfo::isPhysicalRegister(Reg) &&
846         TRI->isSubRegister(MOReg, Reg)))
847      if (!isKill || MO.isKill())
848        return i;
849  }
850  return -1;
851}
852
853/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
854/// indicating if this instruction reads or writes Reg. This also considers
855/// partial defines.
856std::pair<bool,bool>
857MachineInstr::readsWritesVirtualRegister(unsigned Reg,
858                                         SmallVectorImpl<unsigned> *Ops) const {
859  bool PartDef = false; // Partial redefine.
860  bool FullDef = false; // Full define.
861  bool Use = false;
862
863  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
864    const MachineOperand &MO = getOperand(i);
865    if (!MO.isReg() || MO.getReg() != Reg)
866      continue;
867    if (Ops)
868      Ops->push_back(i);
869    if (MO.isUse())
870      Use |= !MO.isUndef();
871    else if (MO.getSubReg())
872      PartDef = true;
873    else
874      FullDef = true;
875  }
876  // A partial redefine uses Reg unless there is also a full define.
877  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
878}
879
880/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
881/// the specified register or -1 if it is not found. If isDead is true, defs
882/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
883/// also checks if there is a def of a super-register.
884int
885MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
886                                        const TargetRegisterInfo *TRI) const {
887  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
888  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
889    const MachineOperand &MO = getOperand(i);
890    if (!MO.isReg() || !MO.isDef())
891      continue;
892    unsigned MOReg = MO.getReg();
893    bool Found = (MOReg == Reg);
894    if (!Found && TRI && isPhys &&
895        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
896      if (Overlap)
897        Found = TRI->regsOverlap(MOReg, Reg);
898      else
899        Found = TRI->isSubRegister(MOReg, Reg);
900    }
901    if (Found && (!isDead || MO.isDead()))
902      return i;
903  }
904  return -1;
905}
906
907/// findFirstPredOperandIdx() - Find the index of the first operand in the
908/// operand list that is used to represent the predicate. It returns -1 if
909/// none is found.
910int MachineInstr::findFirstPredOperandIdx() const {
911  const TargetInstrDesc &TID = getDesc();
912  if (TID.isPredicable()) {
913    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
914      if (TID.OpInfo[i].isPredicate())
915        return i;
916  }
917
918  return -1;
919}
920
921/// isRegTiedToUseOperand - Given the index of a register def operand,
922/// check if the register def is tied to a source operand, due to either
923/// two-address elimination or inline assembly constraints. Returns the
924/// first tied use operand index by reference is UseOpIdx is not null.
925bool MachineInstr::
926isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
927  if (isInlineAsm()) {
928    assert(DefOpIdx >= 3);
929    const MachineOperand &MO = getOperand(DefOpIdx);
930    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
931      return false;
932    // Determine the actual operand index that corresponds to this index.
933    unsigned DefNo = 0;
934    unsigned DefPart = 0;
935    for (unsigned i = 2, e = getNumOperands(); i < e; ) {
936      const MachineOperand &FMO = getOperand(i);
937      // After the normal asm operands there may be additional imp-def regs.
938      if (!FMO.isImm())
939        return false;
940      // Skip over this def.
941      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
942      unsigned PrevDef = i + 1;
943      i = PrevDef + NumOps;
944      if (i > DefOpIdx) {
945        DefPart = DefOpIdx - PrevDef;
946        break;
947      }
948      ++DefNo;
949    }
950    for (unsigned i = 2, e = getNumOperands(); i != e; ++i) {
951      const MachineOperand &FMO = getOperand(i);
952      if (!FMO.isImm())
953        continue;
954      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
955        continue;
956      unsigned Idx;
957      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
958          Idx == DefNo) {
959        if (UseOpIdx)
960          *UseOpIdx = (unsigned)i + 1 + DefPart;
961        return true;
962      }
963    }
964    return false;
965  }
966
967  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
968  const TargetInstrDesc &TID = getDesc();
969  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
970    const MachineOperand &MO = getOperand(i);
971    if (MO.isReg() && MO.isUse() &&
972        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
973      if (UseOpIdx)
974        *UseOpIdx = (unsigned)i;
975      return true;
976    }
977  }
978  return false;
979}
980
981/// isRegTiedToDefOperand - Return true if the operand of the specified index
982/// is a register use and it is tied to an def operand. It also returns the def
983/// operand index by reference.
984bool MachineInstr::
985isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
986  if (isInlineAsm()) {
987    const MachineOperand &MO = getOperand(UseOpIdx);
988    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
989      return false;
990
991    // Find the flag operand corresponding to UseOpIdx
992    unsigned FlagIdx, NumOps=0;
993    for (FlagIdx = 2; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
994      const MachineOperand &UFMO = getOperand(FlagIdx);
995      // After the normal asm operands there may be additional imp-def regs.
996      if (!UFMO.isImm())
997        return false;
998      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
999      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1000      if (UseOpIdx < FlagIdx+NumOps+1)
1001        break;
1002    }
1003    if (FlagIdx >= UseOpIdx)
1004      return false;
1005    const MachineOperand &UFMO = getOperand(FlagIdx);
1006    unsigned DefNo;
1007    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1008      if (!DefOpIdx)
1009        return true;
1010
1011      unsigned DefIdx = 2;
1012      // Remember to adjust the index. First operand is asm string, second is
1013      // the AlignStack bit, then there is a flag for each.
1014      while (DefNo) {
1015        const MachineOperand &FMO = getOperand(DefIdx);
1016        assert(FMO.isImm());
1017        // Skip over this def.
1018        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1019        --DefNo;
1020      }
1021      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1022      return true;
1023    }
1024    return false;
1025  }
1026
1027  const TargetInstrDesc &TID = getDesc();
1028  if (UseOpIdx >= TID.getNumOperands())
1029    return false;
1030  const MachineOperand &MO = getOperand(UseOpIdx);
1031  if (!MO.isReg() || !MO.isUse())
1032    return false;
1033  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
1034  if (DefIdx == -1)
1035    return false;
1036  if (DefOpIdx)
1037    *DefOpIdx = (unsigned)DefIdx;
1038  return true;
1039}
1040
1041/// clearKillInfo - Clears kill flags on all operands.
1042///
1043void MachineInstr::clearKillInfo() {
1044  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1045    MachineOperand &MO = getOperand(i);
1046    if (MO.isReg() && MO.isUse())
1047      MO.setIsKill(false);
1048  }
1049}
1050
1051/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1052///
1053void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1054  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1055    const MachineOperand &MO = MI->getOperand(i);
1056    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1057      continue;
1058    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1059      MachineOperand &MOp = getOperand(j);
1060      if (!MOp.isIdenticalTo(MO))
1061        continue;
1062      if (MO.isKill())
1063        MOp.setIsKill();
1064      else
1065        MOp.setIsDead();
1066      break;
1067    }
1068  }
1069}
1070
1071/// copyPredicates - Copies predicate operand(s) from MI.
1072void MachineInstr::copyPredicates(const MachineInstr *MI) {
1073  const TargetInstrDesc &TID = MI->getDesc();
1074  if (!TID.isPredicable())
1075    return;
1076  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1077    if (TID.OpInfo[i].isPredicate()) {
1078      // Predicated operands must be last operands.
1079      addOperand(MI->getOperand(i));
1080    }
1081  }
1082}
1083
1084void MachineInstr::substituteRegister(unsigned FromReg,
1085                                      unsigned ToReg,
1086                                      unsigned SubIdx,
1087                                      const TargetRegisterInfo &RegInfo) {
1088  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1089    if (SubIdx)
1090      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1091    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1092      MachineOperand &MO = getOperand(i);
1093      if (!MO.isReg() || MO.getReg() != FromReg)
1094        continue;
1095      MO.substPhysReg(ToReg, RegInfo);
1096    }
1097  } else {
1098    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1099      MachineOperand &MO = getOperand(i);
1100      if (!MO.isReg() || MO.getReg() != FromReg)
1101        continue;
1102      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1103    }
1104  }
1105}
1106
1107/// isSafeToMove - Return true if it is safe to move this instruction. If
1108/// SawStore is set to true, it means that there is a store (or call) between
1109/// the instruction's location and its intended destination.
1110bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1111                                AliasAnalysis *AA,
1112                                bool &SawStore) const {
1113  // Ignore stuff that we obviously can't move.
1114  if (TID->mayStore() || TID->isCall()) {
1115    SawStore = true;
1116    return false;
1117  }
1118  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1119    return false;
1120
1121  // See if this instruction does a load.  If so, we have to guarantee that the
1122  // loaded value doesn't change between the load and the its intended
1123  // destination. The check for isInvariantLoad gives the targe the chance to
1124  // classify the load as always returning a constant, e.g. a constant pool
1125  // load.
1126  if (TID->mayLoad() && !isInvariantLoad(AA))
1127    // Otherwise, this is a real load.  If there is a store between the load and
1128    // end of block, or if the load is volatile, we can't move it.
1129    return !SawStore && !hasVolatileMemoryRef();
1130
1131  return true;
1132}
1133
1134/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1135/// instruction which defined the specified register instead of copying it.
1136bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1137                                 AliasAnalysis *AA,
1138                                 unsigned DstReg) const {
1139  bool SawStore = false;
1140  if (!TII->isTriviallyReMaterializable(this, AA) ||
1141      !isSafeToMove(TII, AA, SawStore))
1142    return false;
1143  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1144    const MachineOperand &MO = getOperand(i);
1145    if (!MO.isReg())
1146      continue;
1147    // FIXME: For now, do not remat any instruction with register operands.
1148    // Later on, we can loosen the restriction is the register operands have
1149    // not been modified between the def and use. Note, this is different from
1150    // MachineSink because the code is no longer in two-address form (at least
1151    // partially).
1152    if (MO.isUse())
1153      return false;
1154    else if (!MO.isDead() && MO.getReg() != DstReg)
1155      return false;
1156  }
1157  return true;
1158}
1159
1160/// hasVolatileMemoryRef - Return true if this instruction may have a
1161/// volatile memory reference, or if the information describing the
1162/// memory reference is not available. Return false if it is known to
1163/// have no volatile memory references.
1164bool MachineInstr::hasVolatileMemoryRef() const {
1165  // An instruction known never to access memory won't have a volatile access.
1166  if (!TID->mayStore() &&
1167      !TID->mayLoad() &&
1168      !TID->isCall() &&
1169      !TID->hasUnmodeledSideEffects())
1170    return false;
1171
1172  // Otherwise, if the instruction has no memory reference information,
1173  // conservatively assume it wasn't preserved.
1174  if (memoperands_empty())
1175    return true;
1176
1177  // Check the memory reference information for volatile references.
1178  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1179    if ((*I)->isVolatile())
1180      return true;
1181
1182  return false;
1183}
1184
1185/// isInvariantLoad - Return true if this instruction is loading from a
1186/// location whose value is invariant across the function.  For example,
1187/// loading a value from the constant pool or from the argument area
1188/// of a function if it does not change.  This should only return true of
1189/// *all* loads the instruction does are invariant (if it does multiple loads).
1190bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1191  // If the instruction doesn't load at all, it isn't an invariant load.
1192  if (!TID->mayLoad())
1193    return false;
1194
1195  // If the instruction has lost its memoperands, conservatively assume that
1196  // it may not be an invariant load.
1197  if (memoperands_empty())
1198    return false;
1199
1200  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1201
1202  for (mmo_iterator I = memoperands_begin(),
1203       E = memoperands_end(); I != E; ++I) {
1204    if ((*I)->isVolatile()) return false;
1205    if ((*I)->isStore()) return false;
1206
1207    if (const Value *V = (*I)->getValue()) {
1208      // A load from a constant PseudoSourceValue is invariant.
1209      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1210        if (PSV->isConstant(MFI))
1211          continue;
1212      // If we have an AliasAnalysis, ask it whether the memory is constant.
1213      if (AA && AA->pointsToConstantMemory(
1214                      AliasAnalysis::Location(V, (*I)->getSize(),
1215                                              (*I)->getTBAAInfo())))
1216        continue;
1217    }
1218
1219    // Otherwise assume conservatively.
1220    return false;
1221  }
1222
1223  // Everything checks out.
1224  return true;
1225}
1226
1227/// isConstantValuePHI - If the specified instruction is a PHI that always
1228/// merges together the same virtual register, return the register, otherwise
1229/// return 0.
1230unsigned MachineInstr::isConstantValuePHI() const {
1231  if (!isPHI())
1232    return 0;
1233  assert(getNumOperands() >= 3 &&
1234         "It's illegal to have a PHI without source operands");
1235
1236  unsigned Reg = getOperand(1).getReg();
1237  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1238    if (getOperand(i).getReg() != Reg)
1239      return 0;
1240  return Reg;
1241}
1242
1243/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1244///
1245bool MachineInstr::allDefsAreDead() const {
1246  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1247    const MachineOperand &MO = getOperand(i);
1248    if (!MO.isReg() || MO.isUse())
1249      continue;
1250    if (!MO.isDead())
1251      return false;
1252  }
1253  return true;
1254}
1255
1256void MachineInstr::dump() const {
1257  dbgs() << "  " << *this;
1258}
1259
1260static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1261                         raw_ostream &CommentOS) {
1262  const LLVMContext &Ctx = MF->getFunction()->getContext();
1263  if (!DL.isUnknown()) {          // Print source line info.
1264    DIScope Scope(DL.getScope(Ctx));
1265    // Omit the directory, because it's likely to be long and uninteresting.
1266    if (Scope.Verify())
1267      CommentOS << Scope.getFilename();
1268    else
1269      CommentOS << "<unknown>";
1270    CommentOS << ':' << DL.getLine();
1271    if (DL.getCol() != 0)
1272      CommentOS << ':' << DL.getCol();
1273    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1274    if (!InlinedAtDL.isUnknown()) {
1275      CommentOS << " @[ ";
1276      printDebugLoc(InlinedAtDL, MF, CommentOS);
1277      CommentOS << " ]";
1278    }
1279  }
1280}
1281
1282void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1283  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1284  const MachineFunction *MF = 0;
1285  const MachineRegisterInfo *MRI = 0;
1286  if (const MachineBasicBlock *MBB = getParent()) {
1287    MF = MBB->getParent();
1288    if (!TM && MF)
1289      TM = &MF->getTarget();
1290    if (MF)
1291      MRI = &MF->getRegInfo();
1292  }
1293
1294  // Save a list of virtual registers.
1295  SmallVector<unsigned, 8> VirtRegs;
1296
1297  // Print explicitly defined operands on the left of an assignment syntax.
1298  unsigned StartOp = 0, e = getNumOperands();
1299  for (; StartOp < e && getOperand(StartOp).isReg() &&
1300         getOperand(StartOp).isDef() &&
1301         !getOperand(StartOp).isImplicit();
1302       ++StartOp) {
1303    if (StartOp != 0) OS << ", ";
1304    getOperand(StartOp).print(OS, TM);
1305    unsigned Reg = getOperand(StartOp).getReg();
1306    if (Reg && TargetRegisterInfo::isVirtualRegister(Reg))
1307      VirtRegs.push_back(Reg);
1308  }
1309
1310  if (StartOp != 0)
1311    OS << " = ";
1312
1313  // Print the opcode name.
1314  OS << getDesc().getName();
1315
1316  // Print the rest of the operands.
1317  bool OmittedAnyCallClobbers = false;
1318  bool FirstOp = true;
1319  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1320    const MachineOperand &MO = getOperand(i);
1321
1322    if (MO.isReg() && MO.getReg() &&
1323        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1324      VirtRegs.push_back(MO.getReg());
1325
1326    // Omit call-clobbered registers which aren't used anywhere. This makes
1327    // call instructions much less noisy on targets where calls clobber lots
1328    // of registers. Don't rely on MO.isDead() because we may be called before
1329    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1330    if (MF && getDesc().isCall() &&
1331        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1332      unsigned Reg = MO.getReg();
1333      if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1334        const MachineRegisterInfo &MRI = MF->getRegInfo();
1335        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1336          bool HasAliasLive = false;
1337          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1338               unsigned AliasReg = *Alias; ++Alias)
1339            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1340              HasAliasLive = true;
1341              break;
1342            }
1343          if (!HasAliasLive) {
1344            OmittedAnyCallClobbers = true;
1345            continue;
1346          }
1347        }
1348      }
1349    }
1350
1351    if (FirstOp) FirstOp = false; else OS << ",";
1352    OS << " ";
1353    if (i < getDesc().NumOperands) {
1354      const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1355      if (TOI.isPredicate())
1356        OS << "pred:";
1357      if (TOI.isOptionalDef())
1358        OS << "opt:";
1359    }
1360    if (isDebugValue() && MO.isMetadata()) {
1361      // Pretty print DBG_VALUE instructions.
1362      const MDNode *MD = MO.getMetadata();
1363      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1364        OS << "!\"" << MDS->getString() << '\"';
1365      else
1366        MO.print(OS, TM);
1367    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1368      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1369    } else
1370      MO.print(OS, TM);
1371  }
1372
1373  // Briefly indicate whether any call clobbers were omitted.
1374  if (OmittedAnyCallClobbers) {
1375    if (!FirstOp) OS << ",";
1376    OS << " ...";
1377  }
1378
1379  bool HaveSemi = false;
1380  if (!memoperands_empty()) {
1381    if (!HaveSemi) OS << ";"; HaveSemi = true;
1382
1383    OS << " mem:";
1384    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1385         i != e; ++i) {
1386      OS << **i;
1387      if (llvm::next(i) != e)
1388        OS << " ";
1389    }
1390  }
1391
1392  // Print the regclass of any virtual registers encountered.
1393  if (MRI && !VirtRegs.empty()) {
1394    if (!HaveSemi) OS << ";"; HaveSemi = true;
1395    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1396      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1397      OS << " " << RC->getName() << ":%reg" << VirtRegs[i];
1398      for (unsigned j = i+1; j != VirtRegs.size();) {
1399        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1400          ++j;
1401          continue;
1402        }
1403        if (VirtRegs[i] != VirtRegs[j])
1404          OS << "," << VirtRegs[j];
1405        VirtRegs.erase(VirtRegs.begin()+j);
1406      }
1407    }
1408  }
1409
1410  if (!debugLoc.isUnknown() && MF) {
1411    if (!HaveSemi) OS << ";";
1412    OS << " dbg:";
1413    printDebugLoc(debugLoc, MF, OS);
1414  }
1415
1416  OS << "\n";
1417}
1418
1419bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1420                                     const TargetRegisterInfo *RegInfo,
1421                                     bool AddIfNotFound) {
1422  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1423  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1424  bool Found = false;
1425  SmallVector<unsigned,4> DeadOps;
1426  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1427    MachineOperand &MO = getOperand(i);
1428    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1429      continue;
1430    unsigned Reg = MO.getReg();
1431    if (!Reg)
1432      continue;
1433
1434    if (Reg == IncomingReg) {
1435      if (!Found) {
1436        if (MO.isKill())
1437          // The register is already marked kill.
1438          return true;
1439        if (isPhysReg && isRegTiedToDefOperand(i))
1440          // Two-address uses of physregs must not be marked kill.
1441          return true;
1442        MO.setIsKill();
1443        Found = true;
1444      }
1445    } else if (hasAliases && MO.isKill() &&
1446               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1447      // A super-register kill already exists.
1448      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1449        return true;
1450      if (RegInfo->isSubRegister(IncomingReg, Reg))
1451        DeadOps.push_back(i);
1452    }
1453  }
1454
1455  // Trim unneeded kill operands.
1456  while (!DeadOps.empty()) {
1457    unsigned OpIdx = DeadOps.back();
1458    if (getOperand(OpIdx).isImplicit())
1459      RemoveOperand(OpIdx);
1460    else
1461      getOperand(OpIdx).setIsKill(false);
1462    DeadOps.pop_back();
1463  }
1464
1465  // If not found, this means an alias of one of the operands is killed. Add a
1466  // new implicit operand if required.
1467  if (!Found && AddIfNotFound) {
1468    addOperand(MachineOperand::CreateReg(IncomingReg,
1469                                         false /*IsDef*/,
1470                                         true  /*IsImp*/,
1471                                         true  /*IsKill*/));
1472    return true;
1473  }
1474  return Found;
1475}
1476
1477bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1478                                   const TargetRegisterInfo *RegInfo,
1479                                   bool AddIfNotFound) {
1480  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1481  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1482  bool Found = false;
1483  SmallVector<unsigned,4> DeadOps;
1484  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1485    MachineOperand &MO = getOperand(i);
1486    if (!MO.isReg() || !MO.isDef())
1487      continue;
1488    unsigned Reg = MO.getReg();
1489    if (!Reg)
1490      continue;
1491
1492    if (Reg == IncomingReg) {
1493      if (!Found) {
1494        if (MO.isDead())
1495          // The register is already marked dead.
1496          return true;
1497        MO.setIsDead();
1498        Found = true;
1499      }
1500    } else if (hasAliases && MO.isDead() &&
1501               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1502      // There exists a super-register that's marked dead.
1503      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1504        return true;
1505      if (RegInfo->getSubRegisters(IncomingReg) &&
1506          RegInfo->getSuperRegisters(Reg) &&
1507          RegInfo->isSubRegister(IncomingReg, Reg))
1508        DeadOps.push_back(i);
1509    }
1510  }
1511
1512  // Trim unneeded dead operands.
1513  while (!DeadOps.empty()) {
1514    unsigned OpIdx = DeadOps.back();
1515    if (getOperand(OpIdx).isImplicit())
1516      RemoveOperand(OpIdx);
1517    else
1518      getOperand(OpIdx).setIsDead(false);
1519    DeadOps.pop_back();
1520  }
1521
1522  // If not found, this means an alias of one of the operands is dead. Add a
1523  // new implicit operand if required.
1524  if (Found || !AddIfNotFound)
1525    return Found;
1526
1527  addOperand(MachineOperand::CreateReg(IncomingReg,
1528                                       true  /*IsDef*/,
1529                                       true  /*IsImp*/,
1530                                       false /*IsKill*/,
1531                                       true  /*IsDead*/));
1532  return true;
1533}
1534
1535void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1536                                      const TargetRegisterInfo *RegInfo) {
1537  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1538    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1539    if (MO)
1540      return;
1541  } else {
1542    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1543      const MachineOperand &MO = getOperand(i);
1544      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1545          MO.getSubReg() == 0)
1546        return;
1547    }
1548  }
1549  addOperand(MachineOperand::CreateReg(IncomingReg,
1550                                       true  /*IsDef*/,
1551                                       true  /*IsImp*/));
1552}
1553
1554void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1555                                         const TargetRegisterInfo &TRI) {
1556  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1557    MachineOperand &MO = getOperand(i);
1558    if (!MO.isReg() || !MO.isDef()) continue;
1559    unsigned Reg = MO.getReg();
1560    if (Reg == 0) continue;
1561    bool Dead = true;
1562    for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1563         E = UsedRegs.end(); I != E; ++I)
1564      if (TRI.regsOverlap(*I, Reg)) {
1565        Dead = false;
1566        break;
1567      }
1568    // If there are no uses, including partial uses, the def is dead.
1569    if (Dead) MO.setIsDead();
1570  }
1571}
1572
1573unsigned
1574MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1575  unsigned Hash = MI->getOpcode() * 37;
1576  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1577    const MachineOperand &MO = MI->getOperand(i);
1578    uint64_t Key = (uint64_t)MO.getType() << 32;
1579    switch (MO.getType()) {
1580    default: break;
1581    case MachineOperand::MO_Register:
1582      if (MO.isDef() && MO.getReg() &&
1583          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1584        continue;  // Skip virtual register defs.
1585      Key |= MO.getReg();
1586      break;
1587    case MachineOperand::MO_Immediate:
1588      Key |= MO.getImm();
1589      break;
1590    case MachineOperand::MO_FrameIndex:
1591    case MachineOperand::MO_ConstantPoolIndex:
1592    case MachineOperand::MO_JumpTableIndex:
1593      Key |= MO.getIndex();
1594      break;
1595    case MachineOperand::MO_MachineBasicBlock:
1596      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1597      break;
1598    case MachineOperand::MO_GlobalAddress:
1599      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1600      break;
1601    case MachineOperand::MO_BlockAddress:
1602      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1603      break;
1604    case MachineOperand::MO_MCSymbol:
1605      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1606      break;
1607    }
1608    Key += ~(Key << 32);
1609    Key ^= (Key >> 22);
1610    Key += ~(Key << 13);
1611    Key ^= (Key >> 8);
1612    Key += (Key << 3);
1613    Key ^= (Key >> 15);
1614    Key += ~(Key << 27);
1615    Key ^= (Key >> 31);
1616    Hash = (unsigned)Key + Hash * 37;
1617  }
1618  return Hash;
1619}
1620