MachineInstr.cpp revision 261a7d983d38edd2f1ee6ff2cd0c12a2c2a8b044 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/Value.h"
19#include "llvm/Assembly/Writer.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/PseudoSourceValue.h"
24#include "llvm/Target/TargetMachine.h"
25#include "llvm/Target/TargetInstrInfo.h"
26#include "llvm/Target/TargetInstrDesc.h"
27#include "llvm/Target/TargetRegisterInfo.h"
28#include "llvm/Analysis/AliasAnalysis.h"
29#include "llvm/Analysis/DebugInfo.h"
30#include "llvm/Support/ErrorHandling.h"
31#include "llvm/Support/LeakDetector.h"
32#include "llvm/Support/MathExtras.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/ADT/FoldingSet.h"
35using namespace llvm;
36
37//===----------------------------------------------------------------------===//
38// MachineOperand Implementation
39//===----------------------------------------------------------------------===//
40
41/// AddRegOperandToRegInfo - Add this register operand to the specified
42/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
43/// explicitly nulled out.
44void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
45  assert(isReg() && "Can only add reg operand to use lists");
46
47  // If the reginfo pointer is null, just explicitly null out or next/prev
48  // pointers, to ensure they are not garbage.
49  if (RegInfo == 0) {
50    Contents.Reg.Prev = 0;
51    Contents.Reg.Next = 0;
52    return;
53  }
54
55  // Otherwise, add this operand to the head of the registers use/def list.
56  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
57
58  // For SSA values, we prefer to keep the definition at the start of the list.
59  // we do this by skipping over the definition if it is at the head of the
60  // list.
61  if (*Head && (*Head)->isDef())
62    Head = &(*Head)->Contents.Reg.Next;
63
64  Contents.Reg.Next = *Head;
65  if (Contents.Reg.Next) {
66    assert(getReg() == Contents.Reg.Next->getReg() &&
67           "Different regs on the same list!");
68    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
69  }
70
71  Contents.Reg.Prev = Head;
72  *Head = this;
73}
74
75/// RemoveRegOperandFromRegInfo - Remove this register operand from the
76/// MachineRegisterInfo it is linked with.
77void MachineOperand::RemoveRegOperandFromRegInfo() {
78  assert(isOnRegUseList() && "Reg operand is not on a use list");
79  // Unlink this from the doubly linked list of operands.
80  MachineOperand *NextOp = Contents.Reg.Next;
81  *Contents.Reg.Prev = NextOp;
82  if (NextOp) {
83    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
84    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
85  }
86  Contents.Reg.Prev = 0;
87  Contents.Reg.Next = 0;
88}
89
90void MachineOperand::setReg(unsigned Reg) {
91  if (getReg() == Reg) return; // No change.
92
93  // Otherwise, we have to change the register.  If this operand is embedded
94  // into a machine function, we need to update the old and new register's
95  // use/def lists.
96  if (MachineInstr *MI = getParent())
97    if (MachineBasicBlock *MBB = MI->getParent())
98      if (MachineFunction *MF = MBB->getParent()) {
99        RemoveRegOperandFromRegInfo();
100        Contents.Reg.RegNo = Reg;
101        AddRegOperandToRegInfo(&MF->getRegInfo());
102        return;
103      }
104
105  // Otherwise, just change the register, no problem.  :)
106  Contents.Reg.RegNo = Reg;
107}
108
109/// ChangeToImmediate - Replace this operand with a new immediate operand of
110/// the specified value.  If an operand is known to be an immediate already,
111/// the setImm method should be used.
112void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
113  // If this operand is currently a register operand, and if this is in a
114  // function, deregister the operand from the register's use/def list.
115  if (isReg() && getParent() && getParent()->getParent() &&
116      getParent()->getParent()->getParent())
117    RemoveRegOperandFromRegInfo();
118
119  OpKind = MO_Immediate;
120  Contents.ImmVal = ImmVal;
121}
122
123/// ChangeToRegister - Replace this operand with a new register operand of
124/// the specified value.  If an operand is known to be an register already,
125/// the setReg method should be used.
126void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
127                                      bool isKill, bool isDead, bool isUndef) {
128  // If this operand is already a register operand, use setReg to update the
129  // register's use/def lists.
130  if (isReg()) {
131    assert(!isEarlyClobber());
132    setReg(Reg);
133  } else {
134    // Otherwise, change this to a register and set the reg#.
135    OpKind = MO_Register;
136    Contents.Reg.RegNo = Reg;
137
138    // If this operand is embedded in a function, add the operand to the
139    // register's use/def list.
140    if (MachineInstr *MI = getParent())
141      if (MachineBasicBlock *MBB = MI->getParent())
142        if (MachineFunction *MF = MBB->getParent())
143          AddRegOperandToRegInfo(&MF->getRegInfo());
144  }
145
146  IsDef = isDef;
147  IsImp = isImp;
148  IsKill = isKill;
149  IsDead = isDead;
150  IsUndef = isUndef;
151  IsEarlyClobber = false;
152  SubReg = 0;
153}
154
155/// isIdenticalTo - Return true if this operand is identical to the specified
156/// operand.
157bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
158  if (getType() != Other.getType() ||
159      getTargetFlags() != Other.getTargetFlags())
160    return false;
161
162  switch (getType()) {
163  default: llvm_unreachable("Unrecognized operand type");
164  case MachineOperand::MO_Register:
165    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
166           getSubReg() == Other.getSubReg();
167  case MachineOperand::MO_Immediate:
168    return getImm() == Other.getImm();
169  case MachineOperand::MO_FPImmediate:
170    return getFPImm() == Other.getFPImm();
171  case MachineOperand::MO_MachineBasicBlock:
172    return getMBB() == Other.getMBB();
173  case MachineOperand::MO_FrameIndex:
174    return getIndex() == Other.getIndex();
175  case MachineOperand::MO_ConstantPoolIndex:
176    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
177  case MachineOperand::MO_JumpTableIndex:
178    return getIndex() == Other.getIndex();
179  case MachineOperand::MO_GlobalAddress:
180    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
181  case MachineOperand::MO_ExternalSymbol:
182    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
183           getOffset() == Other.getOffset();
184  case MachineOperand::MO_BlockAddress:
185    return getBlockAddress() == Other.getBlockAddress();
186  }
187}
188
189/// print - Print the specified machine operand.
190///
191void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
192  // If the instruction is embedded into a basic block, we can find the
193  // target info for the instruction.
194  if (!TM)
195    if (const MachineInstr *MI = getParent())
196      if (const MachineBasicBlock *MBB = MI->getParent())
197        if (const MachineFunction *MF = MBB->getParent())
198          TM = &MF->getTarget();
199
200  switch (getType()) {
201  case MachineOperand::MO_Register:
202    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
203      OS << "%reg" << getReg();
204    } else {
205      if (TM)
206        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
207      else
208        OS << "%physreg" << getReg();
209    }
210
211    if (getSubReg() != 0)
212      OS << ':' << getSubReg();
213
214    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
215        isEarlyClobber()) {
216      OS << '<';
217      bool NeedComma = false;
218      if (isDef()) {
219        if (NeedComma) OS << ',';
220        if (isEarlyClobber())
221          OS << "earlyclobber,";
222        if (isImplicit())
223          OS << "imp-";
224        OS << "def";
225        NeedComma = true;
226      } else if (isImplicit()) {
227          OS << "imp-use";
228          NeedComma = true;
229      }
230
231      if (isKill() || isDead() || isUndef()) {
232        if (NeedComma) OS << ',';
233        if (isKill())  OS << "kill";
234        if (isDead())  OS << "dead";
235        if (isUndef()) {
236          if (isKill() || isDead())
237            OS << ',';
238          OS << "undef";
239        }
240      }
241      OS << '>';
242    }
243    break;
244  case MachineOperand::MO_Immediate:
245    OS << getImm();
246    break;
247  case MachineOperand::MO_FPImmediate:
248    if (getFPImm()->getType()->isFloatTy())
249      OS << getFPImm()->getValueAPF().convertToFloat();
250    else
251      OS << getFPImm()->getValueAPF().convertToDouble();
252    break;
253  case MachineOperand::MO_MachineBasicBlock:
254    OS << "<BB#" << getMBB()->getNumber() << ">";
255    break;
256  case MachineOperand::MO_FrameIndex:
257    OS << "<fi#" << getIndex() << '>';
258    break;
259  case MachineOperand::MO_ConstantPoolIndex:
260    OS << "<cp#" << getIndex();
261    if (getOffset()) OS << "+" << getOffset();
262    OS << '>';
263    break;
264  case MachineOperand::MO_JumpTableIndex:
265    OS << "<jt#" << getIndex() << '>';
266    break;
267  case MachineOperand::MO_GlobalAddress:
268    OS << "<ga:";
269    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
270    if (getOffset()) OS << "+" << getOffset();
271    OS << '>';
272    break;
273  case MachineOperand::MO_ExternalSymbol:
274    OS << "<es:" << getSymbolName();
275    if (getOffset()) OS << "+" << getOffset();
276    OS << '>';
277    break;
278  case MachineOperand::MO_BlockAddress:
279    OS << "<";
280    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
281    OS << '>';
282    break;
283  default:
284    llvm_unreachable("Unrecognized operand type");
285  }
286
287  if (unsigned TF = getTargetFlags())
288    OS << "[TF=" << TF << ']';
289}
290
291//===----------------------------------------------------------------------===//
292// MachineMemOperand Implementation
293//===----------------------------------------------------------------------===//
294
295MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
296                                     int64_t o, uint64_t s, unsigned int a)
297  : Offset(o), Size(s), V(v),
298    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
299  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
300  assert((isLoad() || isStore()) && "Not a load/store!");
301}
302
303/// Profile - Gather unique data for the object.
304///
305void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
306  ID.AddInteger(Offset);
307  ID.AddInteger(Size);
308  ID.AddPointer(V);
309  ID.AddInteger(Flags);
310}
311
312void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
313  // The Value and Offset may differ due to CSE. But the flags and size
314  // should be the same.
315  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
316  assert(MMO->getSize() == getSize() && "Size mismatch!");
317
318  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
319    // Update the alignment value.
320    Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3);
321    // Also update the base and offset, because the new alignment may
322    // not be applicable with the old ones.
323    V = MMO->getValue();
324    Offset = MMO->getOffset();
325  }
326}
327
328/// getAlignment - Return the minimum known alignment in bytes of the
329/// actual memory reference.
330uint64_t MachineMemOperand::getAlignment() const {
331  return MinAlign(getBaseAlignment(), getOffset());
332}
333
334raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
335  assert((MMO.isLoad() || MMO.isStore()) &&
336         "SV has to be a load, store or both.");
337
338  if (MMO.isVolatile())
339    OS << "Volatile ";
340
341  if (MMO.isLoad())
342    OS << "LD";
343  if (MMO.isStore())
344    OS << "ST";
345  OS << MMO.getSize();
346
347  // Print the address information.
348  OS << "[";
349  if (!MMO.getValue())
350    OS << "<unknown>";
351  else
352    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
353
354  // If the alignment of the memory reference itself differs from the alignment
355  // of the base pointer, print the base alignment explicitly, next to the base
356  // pointer.
357  if (MMO.getBaseAlignment() != MMO.getAlignment())
358    OS << "(align=" << MMO.getBaseAlignment() << ")";
359
360  if (MMO.getOffset() != 0)
361    OS << "+" << MMO.getOffset();
362  OS << "]";
363
364  // Print the alignment of the reference.
365  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
366      MMO.getBaseAlignment() != MMO.getSize())
367    OS << "(align=" << MMO.getAlignment() << ")";
368
369  return OS;
370}
371
372//===----------------------------------------------------------------------===//
373// MachineInstr Implementation
374//===----------------------------------------------------------------------===//
375
376/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
377/// TID NULL and no operands.
378MachineInstr::MachineInstr()
379  : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
380    Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
381  // Make sure that we get added to a machine basicblock
382  LeakDetector::addGarbageObject(this);
383}
384
385void MachineInstr::addImplicitDefUseOperands() {
386  if (TID->ImplicitDefs)
387    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
388      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
389  if (TID->ImplicitUses)
390    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
391      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
392}
393
394/// MachineInstr ctor - This constructor create a MachineInstr and add the
395/// implicit operands. It reserves space for number of operands specified by
396/// TargetInstrDesc or the numOperands if it is not zero. (for
397/// instructions with variable number of operands).
398MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
399  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
400    MemRefs(0), MemRefsEnd(0), Parent(0),
401    debugLoc(DebugLoc::getUnknownLoc()) {
402  if (!NoImp && TID->getImplicitDefs())
403    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
404      NumImplicitOps++;
405  if (!NoImp && TID->getImplicitUses())
406    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
407      NumImplicitOps++;
408  Operands.reserve(NumImplicitOps + TID->getNumOperands());
409  if (!NoImp)
410    addImplicitDefUseOperands();
411  // Make sure that we get added to a machine basicblock
412  LeakDetector::addGarbageObject(this);
413}
414
415/// MachineInstr ctor - As above, but with a DebugLoc.
416MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
417                           bool NoImp)
418  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
419    Parent(0), debugLoc(dl) {
420  if (!NoImp && TID->getImplicitDefs())
421    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
422      NumImplicitOps++;
423  if (!NoImp && TID->getImplicitUses())
424    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
425      NumImplicitOps++;
426  Operands.reserve(NumImplicitOps + TID->getNumOperands());
427  if (!NoImp)
428    addImplicitDefUseOperands();
429  // Make sure that we get added to a machine basicblock
430  LeakDetector::addGarbageObject(this);
431}
432
433/// MachineInstr ctor - Work exactly the same as the ctor two above, except
434/// that the MachineInstr is created and added to the end of the specified
435/// basic block.
436///
437MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
438  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
439    MemRefs(0), MemRefsEnd(0), Parent(0),
440    debugLoc(DebugLoc::getUnknownLoc()) {
441  assert(MBB && "Cannot use inserting ctor with null basic block!");
442  if (TID->ImplicitDefs)
443    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
444      NumImplicitOps++;
445  if (TID->ImplicitUses)
446    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
447      NumImplicitOps++;
448  Operands.reserve(NumImplicitOps + TID->getNumOperands());
449  addImplicitDefUseOperands();
450  // Make sure that we get added to a machine basicblock
451  LeakDetector::addGarbageObject(this);
452  MBB->push_back(this);  // Add instruction to end of basic block!
453}
454
455/// MachineInstr ctor - As above, but with a DebugLoc.
456///
457MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
458                           const TargetInstrDesc &tid)
459  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
460    Parent(0), debugLoc(dl) {
461  assert(MBB && "Cannot use inserting ctor with null basic block!");
462  if (TID->ImplicitDefs)
463    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
464      NumImplicitOps++;
465  if (TID->ImplicitUses)
466    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
467      NumImplicitOps++;
468  Operands.reserve(NumImplicitOps + TID->getNumOperands());
469  addImplicitDefUseOperands();
470  // Make sure that we get added to a machine basicblock
471  LeakDetector::addGarbageObject(this);
472  MBB->push_back(this);  // Add instruction to end of basic block!
473}
474
475/// MachineInstr ctor - Copies MachineInstr arg exactly
476///
477MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
478  : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
479    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
480    Parent(0), debugLoc(MI.getDebugLoc()) {
481  Operands.reserve(MI.getNumOperands());
482
483  // Add operands
484  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
485    addOperand(MI.getOperand(i));
486  NumImplicitOps = MI.NumImplicitOps;
487
488  // Set parent to null.
489  Parent = 0;
490
491  LeakDetector::addGarbageObject(this);
492}
493
494MachineInstr::~MachineInstr() {
495  LeakDetector::removeGarbageObject(this);
496#ifndef NDEBUG
497  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
498    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
499    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
500           "Reg operand def/use list corrupted");
501  }
502#endif
503}
504
505/// getRegInfo - If this instruction is embedded into a MachineFunction,
506/// return the MachineRegisterInfo object for the current function, otherwise
507/// return null.
508MachineRegisterInfo *MachineInstr::getRegInfo() {
509  if (MachineBasicBlock *MBB = getParent())
510    return &MBB->getParent()->getRegInfo();
511  return 0;
512}
513
514/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
515/// this instruction from their respective use lists.  This requires that the
516/// operands already be on their use lists.
517void MachineInstr::RemoveRegOperandsFromUseLists() {
518  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
519    if (Operands[i].isReg())
520      Operands[i].RemoveRegOperandFromRegInfo();
521  }
522}
523
524/// AddRegOperandsToUseLists - Add all of the register operands in
525/// this instruction from their respective use lists.  This requires that the
526/// operands not be on their use lists yet.
527void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
528  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
529    if (Operands[i].isReg())
530      Operands[i].AddRegOperandToRegInfo(&RegInfo);
531  }
532}
533
534
535/// addOperand - Add the specified operand to the instruction.  If it is an
536/// implicit operand, it is added to the end of the operand list.  If it is
537/// an explicit operand it is added at the end of the explicit operand list
538/// (before the first implicit operand).
539void MachineInstr::addOperand(const MachineOperand &Op) {
540  bool isImpReg = Op.isReg() && Op.isImplicit();
541  assert((isImpReg || !OperandsComplete()) &&
542         "Trying to add an operand to a machine instr that is already done!");
543
544  MachineRegisterInfo *RegInfo = getRegInfo();
545
546  // If we are adding the operand to the end of the list, our job is simpler.
547  // This is true most of the time, so this is a reasonable optimization.
548  if (isImpReg || NumImplicitOps == 0) {
549    // We can only do this optimization if we know that the operand list won't
550    // reallocate.
551    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
552      Operands.push_back(Op);
553
554      // Set the parent of the operand.
555      Operands.back().ParentMI = this;
556
557      // If the operand is a register, update the operand's use list.
558      if (Op.isReg())
559        Operands.back().AddRegOperandToRegInfo(RegInfo);
560      return;
561    }
562  }
563
564  // Otherwise, we have to insert a real operand before any implicit ones.
565  unsigned OpNo = Operands.size()-NumImplicitOps;
566
567  // If this instruction isn't embedded into a function, then we don't need to
568  // update any operand lists.
569  if (RegInfo == 0) {
570    // Simple insertion, no reginfo update needed for other register operands.
571    Operands.insert(Operands.begin()+OpNo, Op);
572    Operands[OpNo].ParentMI = this;
573
574    // Do explicitly set the reginfo for this operand though, to ensure the
575    // next/prev fields are properly nulled out.
576    if (Operands[OpNo].isReg())
577      Operands[OpNo].AddRegOperandToRegInfo(0);
578
579  } else if (Operands.size()+1 <= Operands.capacity()) {
580    // Otherwise, we have to remove register operands from their register use
581    // list, add the operand, then add the register operands back to their use
582    // list.  This also must handle the case when the operand list reallocates
583    // to somewhere else.
584
585    // If insertion of this operand won't cause reallocation of the operand
586    // list, just remove the implicit operands, add the operand, then re-add all
587    // the rest of the operands.
588    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
589      assert(Operands[i].isReg() && "Should only be an implicit reg!");
590      Operands[i].RemoveRegOperandFromRegInfo();
591    }
592
593    // Add the operand.  If it is a register, add it to the reg list.
594    Operands.insert(Operands.begin()+OpNo, Op);
595    Operands[OpNo].ParentMI = this;
596
597    if (Operands[OpNo].isReg())
598      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
599
600    // Re-add all the implicit ops.
601    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
602      assert(Operands[i].isReg() && "Should only be an implicit reg!");
603      Operands[i].AddRegOperandToRegInfo(RegInfo);
604    }
605  } else {
606    // Otherwise, we will be reallocating the operand list.  Remove all reg
607    // operands from their list, then readd them after the operand list is
608    // reallocated.
609    RemoveRegOperandsFromUseLists();
610
611    Operands.insert(Operands.begin()+OpNo, Op);
612    Operands[OpNo].ParentMI = this;
613
614    // Re-add all the operands.
615    AddRegOperandsToUseLists(*RegInfo);
616  }
617}
618
619/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
620/// fewer operand than it started with.
621///
622void MachineInstr::RemoveOperand(unsigned OpNo) {
623  assert(OpNo < Operands.size() && "Invalid operand number");
624
625  // Special case removing the last one.
626  if (OpNo == Operands.size()-1) {
627    // If needed, remove from the reg def/use list.
628    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
629      Operands.back().RemoveRegOperandFromRegInfo();
630
631    Operands.pop_back();
632    return;
633  }
634
635  // Otherwise, we are removing an interior operand.  If we have reginfo to
636  // update, remove all operands that will be shifted down from their reg lists,
637  // move everything down, then re-add them.
638  MachineRegisterInfo *RegInfo = getRegInfo();
639  if (RegInfo) {
640    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
641      if (Operands[i].isReg())
642        Operands[i].RemoveRegOperandFromRegInfo();
643    }
644  }
645
646  Operands.erase(Operands.begin()+OpNo);
647
648  if (RegInfo) {
649    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
650      if (Operands[i].isReg())
651        Operands[i].AddRegOperandToRegInfo(RegInfo);
652    }
653  }
654}
655
656/// addMemOperand - Add a MachineMemOperand to the machine instruction.
657/// This function should be used only occasionally. The setMemRefs function
658/// is the primary method for setting up a MachineInstr's MemRefs list.
659void MachineInstr::addMemOperand(MachineFunction &MF,
660                                 MachineMemOperand *MO) {
661  mmo_iterator OldMemRefs = MemRefs;
662  mmo_iterator OldMemRefsEnd = MemRefsEnd;
663
664  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
665  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
666  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
667
668  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
669  NewMemRefs[NewNum - 1] = MO;
670
671  MemRefs = NewMemRefs;
672  MemRefsEnd = NewMemRefsEnd;
673}
674
675/// removeFromParent - This method unlinks 'this' from the containing basic
676/// block, and returns it, but does not delete it.
677MachineInstr *MachineInstr::removeFromParent() {
678  assert(getParent() && "Not embedded in a basic block!");
679  getParent()->remove(this);
680  return this;
681}
682
683
684/// eraseFromParent - This method unlinks 'this' from the containing basic
685/// block, and deletes it.
686void MachineInstr::eraseFromParent() {
687  assert(getParent() && "Not embedded in a basic block!");
688  getParent()->erase(this);
689}
690
691
692/// OperandComplete - Return true if it's illegal to add a new operand
693///
694bool MachineInstr::OperandsComplete() const {
695  unsigned short NumOperands = TID->getNumOperands();
696  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
697    return true;  // Broken: we have all the operands of this instruction!
698  return false;
699}
700
701/// getNumExplicitOperands - Returns the number of non-implicit operands.
702///
703unsigned MachineInstr::getNumExplicitOperands() const {
704  unsigned NumOperands = TID->getNumOperands();
705  if (!TID->isVariadic())
706    return NumOperands;
707
708  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
709    const MachineOperand &MO = getOperand(i);
710    if (!MO.isReg() || !MO.isImplicit())
711      NumOperands++;
712  }
713  return NumOperands;
714}
715
716
717/// isLabel - Returns true if the MachineInstr represents a label.
718///
719bool MachineInstr::isLabel() const {
720  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
721         getOpcode() == TargetInstrInfo::EH_LABEL ||
722         getOpcode() == TargetInstrInfo::GC_LABEL;
723}
724
725/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
726///
727bool MachineInstr::isDebugLabel() const {
728  return getOpcode() == TargetInstrInfo::DBG_LABEL;
729}
730
731/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
732/// the specific register or -1 if it is not found. It further tightens
733/// the search criteria to a use that kills the register if isKill is true.
734int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
735                                          const TargetRegisterInfo *TRI) const {
736  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
737    const MachineOperand &MO = getOperand(i);
738    if (!MO.isReg() || !MO.isUse())
739      continue;
740    unsigned MOReg = MO.getReg();
741    if (!MOReg)
742      continue;
743    if (MOReg == Reg ||
744        (TRI &&
745         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
746         TargetRegisterInfo::isPhysicalRegister(Reg) &&
747         TRI->isSubRegister(MOReg, Reg)))
748      if (!isKill || MO.isKill())
749        return i;
750  }
751  return -1;
752}
753
754/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
755/// the specified register or -1 if it is not found. If isDead is true, defs
756/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
757/// also checks if there is a def of a super-register.
758int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
759                                          const TargetRegisterInfo *TRI) const {
760  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
761    const MachineOperand &MO = getOperand(i);
762    if (!MO.isReg() || !MO.isDef())
763      continue;
764    unsigned MOReg = MO.getReg();
765    if (MOReg == Reg ||
766        (TRI &&
767         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
768         TargetRegisterInfo::isPhysicalRegister(Reg) &&
769         TRI->isSubRegister(MOReg, Reg)))
770      if (!isDead || MO.isDead())
771        return i;
772  }
773  return -1;
774}
775
776/// findFirstPredOperandIdx() - Find the index of the first operand in the
777/// operand list that is used to represent the predicate. It returns -1 if
778/// none is found.
779int MachineInstr::findFirstPredOperandIdx() const {
780  const TargetInstrDesc &TID = getDesc();
781  if (TID.isPredicable()) {
782    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
783      if (TID.OpInfo[i].isPredicate())
784        return i;
785  }
786
787  return -1;
788}
789
790/// isRegTiedToUseOperand - Given the index of a register def operand,
791/// check if the register def is tied to a source operand, due to either
792/// two-address elimination or inline assembly constraints. Returns the
793/// first tied use operand index by reference is UseOpIdx is not null.
794bool MachineInstr::
795isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
796  if (getOpcode() == TargetInstrInfo::INLINEASM) {
797    assert(DefOpIdx >= 2);
798    const MachineOperand &MO = getOperand(DefOpIdx);
799    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
800      return false;
801    // Determine the actual operand index that corresponds to this index.
802    unsigned DefNo = 0;
803    unsigned DefPart = 0;
804    for (unsigned i = 1, e = getNumOperands(); i < e; ) {
805      const MachineOperand &FMO = getOperand(i);
806      // After the normal asm operands there may be additional imp-def regs.
807      if (!FMO.isImm())
808        return false;
809      // Skip over this def.
810      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
811      unsigned PrevDef = i + 1;
812      i = PrevDef + NumOps;
813      if (i > DefOpIdx) {
814        DefPart = DefOpIdx - PrevDef;
815        break;
816      }
817      ++DefNo;
818    }
819    for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
820      const MachineOperand &FMO = getOperand(i);
821      if (!FMO.isImm())
822        continue;
823      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
824        continue;
825      unsigned Idx;
826      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
827          Idx == DefNo) {
828        if (UseOpIdx)
829          *UseOpIdx = (unsigned)i + 1 + DefPart;
830        return true;
831      }
832    }
833    return false;
834  }
835
836  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
837  const TargetInstrDesc &TID = getDesc();
838  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
839    const MachineOperand &MO = getOperand(i);
840    if (MO.isReg() && MO.isUse() &&
841        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
842      if (UseOpIdx)
843        *UseOpIdx = (unsigned)i;
844      return true;
845    }
846  }
847  return false;
848}
849
850/// isRegTiedToDefOperand - Return true if the operand of the specified index
851/// is a register use and it is tied to an def operand. It also returns the def
852/// operand index by reference.
853bool MachineInstr::
854isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
855  if (getOpcode() == TargetInstrInfo::INLINEASM) {
856    const MachineOperand &MO = getOperand(UseOpIdx);
857    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
858      return false;
859
860    // Find the flag operand corresponding to UseOpIdx
861    unsigned FlagIdx, NumOps=0;
862    for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
863      const MachineOperand &UFMO = getOperand(FlagIdx);
864      // After the normal asm operands there may be additional imp-def regs.
865      if (!UFMO.isImm())
866        return false;
867      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
868      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
869      if (UseOpIdx < FlagIdx+NumOps+1)
870        break;
871    }
872    if (FlagIdx >= UseOpIdx)
873      return false;
874    const MachineOperand &UFMO = getOperand(FlagIdx);
875    unsigned DefNo;
876    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
877      if (!DefOpIdx)
878        return true;
879
880      unsigned DefIdx = 1;
881      // Remember to adjust the index. First operand is asm string, then there
882      // is a flag for each.
883      while (DefNo) {
884        const MachineOperand &FMO = getOperand(DefIdx);
885        assert(FMO.isImm());
886        // Skip over this def.
887        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
888        --DefNo;
889      }
890      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
891      return true;
892    }
893    return false;
894  }
895
896  const TargetInstrDesc &TID = getDesc();
897  if (UseOpIdx >= TID.getNumOperands())
898    return false;
899  const MachineOperand &MO = getOperand(UseOpIdx);
900  if (!MO.isReg() || !MO.isUse())
901    return false;
902  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
903  if (DefIdx == -1)
904    return false;
905  if (DefOpIdx)
906    *DefOpIdx = (unsigned)DefIdx;
907  return true;
908}
909
910/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
911///
912void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
913  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
914    const MachineOperand &MO = MI->getOperand(i);
915    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
916      continue;
917    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
918      MachineOperand &MOp = getOperand(j);
919      if (!MOp.isIdenticalTo(MO))
920        continue;
921      if (MO.isKill())
922        MOp.setIsKill();
923      else
924        MOp.setIsDead();
925      break;
926    }
927  }
928}
929
930/// copyPredicates - Copies predicate operand(s) from MI.
931void MachineInstr::copyPredicates(const MachineInstr *MI) {
932  const TargetInstrDesc &TID = MI->getDesc();
933  if (!TID.isPredicable())
934    return;
935  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
936    if (TID.OpInfo[i].isPredicate()) {
937      // Predicated operands must be last operands.
938      addOperand(MI->getOperand(i));
939    }
940  }
941}
942
943/// isSafeToMove - Return true if it is safe to move this instruction. If
944/// SawStore is set to true, it means that there is a store (or call) between
945/// the instruction's location and its intended destination.
946bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
947                                bool &SawStore,
948                                AliasAnalysis *AA) const {
949  // Ignore stuff that we obviously can't move.
950  if (TID->mayStore() || TID->isCall()) {
951    SawStore = true;
952    return false;
953  }
954  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
955    return false;
956
957  // See if this instruction does a load.  If so, we have to guarantee that the
958  // loaded value doesn't change between the load and the its intended
959  // destination. The check for isInvariantLoad gives the targe the chance to
960  // classify the load as always returning a constant, e.g. a constant pool
961  // load.
962  if (TID->mayLoad() && !isInvariantLoad(AA))
963    // Otherwise, this is a real load.  If there is a store between the load and
964    // end of block, or if the load is volatile, we can't move it.
965    return !SawStore && !hasVolatileMemoryRef();
966
967  return true;
968}
969
970/// isSafeToReMat - Return true if it's safe to rematerialize the specified
971/// instruction which defined the specified register instead of copying it.
972bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
973                                 unsigned DstReg,
974                                 AliasAnalysis *AA) const {
975  bool SawStore = false;
976  if (!TII->isTriviallyReMaterializable(this, AA) ||
977      !isSafeToMove(TII, SawStore, AA))
978    return false;
979  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
980    const MachineOperand &MO = getOperand(i);
981    if (!MO.isReg())
982      continue;
983    // FIXME: For now, do not remat any instruction with register operands.
984    // Later on, we can loosen the restriction is the register operands have
985    // not been modified between the def and use. Note, this is different from
986    // MachineSink because the code is no longer in two-address form (at least
987    // partially).
988    if (MO.isUse())
989      return false;
990    else if (!MO.isDead() && MO.getReg() != DstReg)
991      return false;
992  }
993  return true;
994}
995
996/// hasVolatileMemoryRef - Return true if this instruction may have a
997/// volatile memory reference, or if the information describing the
998/// memory reference is not available. Return false if it is known to
999/// have no volatile memory references.
1000bool MachineInstr::hasVolatileMemoryRef() const {
1001  // An instruction known never to access memory won't have a volatile access.
1002  if (!TID->mayStore() &&
1003      !TID->mayLoad() &&
1004      !TID->isCall() &&
1005      !TID->hasUnmodeledSideEffects())
1006    return false;
1007
1008  // Otherwise, if the instruction has no memory reference information,
1009  // conservatively assume it wasn't preserved.
1010  if (memoperands_empty())
1011    return true;
1012
1013  // Check the memory reference information for volatile references.
1014  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1015    if ((*I)->isVolatile())
1016      return true;
1017
1018  return false;
1019}
1020
1021/// isInvariantLoad - Return true if this instruction is loading from a
1022/// location whose value is invariant across the function.  For example,
1023/// loading a value from the constant pool or from from the argument area
1024/// of a function if it does not change.  This should only return true of
1025/// *all* loads the instruction does are invariant (if it does multiple loads).
1026bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1027  // If the instruction doesn't load at all, it isn't an invariant load.
1028  if (!TID->mayLoad())
1029    return false;
1030
1031  // If the instruction has lost its memoperands, conservatively assume that
1032  // it may not be an invariant load.
1033  if (memoperands_empty())
1034    return false;
1035
1036  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1037
1038  for (mmo_iterator I = memoperands_begin(),
1039       E = memoperands_end(); I != E; ++I) {
1040    if ((*I)->isVolatile()) return false;
1041    if ((*I)->isStore()) return false;
1042
1043    if (const Value *V = (*I)->getValue()) {
1044      // A load from a constant PseudoSourceValue is invariant.
1045      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1046        if (PSV->isConstant(MFI))
1047          continue;
1048      // If we have an AliasAnalysis, ask it whether the memory is constant.
1049      if (AA && AA->pointsToConstantMemory(V))
1050        continue;
1051    }
1052
1053    // Otherwise assume conservatively.
1054    return false;
1055  }
1056
1057  // Everything checks out.
1058  return true;
1059}
1060
1061void MachineInstr::dump() const {
1062  errs() << "  " << *this;
1063}
1064
1065void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1066  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1067  const MachineFunction *MF = 0;
1068  if (const MachineBasicBlock *MBB = getParent()) {
1069    MF = MBB->getParent();
1070    if (!TM && MF)
1071      TM = &MF->getTarget();
1072  }
1073
1074  // Print explicitly defined operands on the left of an assignment syntax.
1075  unsigned StartOp = 0, e = getNumOperands();
1076  for (; StartOp < e && getOperand(StartOp).isReg() &&
1077         getOperand(StartOp).isDef() &&
1078         !getOperand(StartOp).isImplicit();
1079       ++StartOp) {
1080    if (StartOp != 0) OS << ", ";
1081    getOperand(StartOp).print(OS, TM);
1082  }
1083
1084  if (StartOp != 0)
1085    OS << " = ";
1086
1087  // Print the opcode name.
1088  OS << getDesc().getName();
1089
1090  // Print the rest of the operands.
1091  bool OmittedAnyCallClobbers = false;
1092  bool FirstOp = true;
1093  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1094    const MachineOperand &MO = getOperand(i);
1095
1096    // Omit call-clobbered registers which aren't used anywhere. This makes
1097    // call instructions much less noisy on targets where calls clobber lots
1098    // of registers. Don't rely on MO.isDead() because we may be called before
1099    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1100    if (MF && getDesc().isCall() &&
1101        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1102      unsigned Reg = MO.getReg();
1103      if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1104        const MachineRegisterInfo &MRI = MF->getRegInfo();
1105        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1106          bool HasAliasLive = false;
1107          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1108               unsigned AliasReg = *Alias; ++Alias)
1109            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1110              HasAliasLive = true;
1111              break;
1112            }
1113          if (!HasAliasLive) {
1114            OmittedAnyCallClobbers = true;
1115            continue;
1116          }
1117        }
1118      }
1119    }
1120
1121    if (FirstOp) FirstOp = false; else OS << ",";
1122    OS << " ";
1123    MO.print(OS, TM);
1124  }
1125
1126  // Briefly indicate whether any call clobbers were omitted.
1127  if (OmittedAnyCallClobbers) {
1128    if (FirstOp) FirstOp = false; else OS << ",";
1129    OS << " ...";
1130  }
1131
1132  bool HaveSemi = false;
1133  if (!memoperands_empty()) {
1134    if (!HaveSemi) OS << ";"; HaveSemi = true;
1135
1136    OS << " mem:";
1137    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1138         i != e; ++i) {
1139      OS << **i;
1140      if (next(i) != e)
1141        OS << " ";
1142    }
1143  }
1144
1145  if (!debugLoc.isUnknown() && MF) {
1146    if (!HaveSemi) OS << ";"; HaveSemi = true;
1147
1148    // TODO: print InlinedAtLoc information
1149
1150    DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1151    DIScope Scope(DLT.Scope);
1152    OS << " dbg:";
1153    if (!Scope.isNull())
1154      OS << Scope.getDirectory() << ':' << Scope.getFilename() << ':';
1155    OS << DLT.Line << ":" << DLT.Col;
1156  }
1157
1158  OS << "\n";
1159}
1160
1161bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1162                                     const TargetRegisterInfo *RegInfo,
1163                                     bool AddIfNotFound) {
1164  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1165  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1166  bool Found = false;
1167  SmallVector<unsigned,4> DeadOps;
1168  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1169    MachineOperand &MO = getOperand(i);
1170    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1171      continue;
1172    unsigned Reg = MO.getReg();
1173    if (!Reg)
1174      continue;
1175
1176    if (Reg == IncomingReg) {
1177      if (!Found) {
1178        if (MO.isKill())
1179          // The register is already marked kill.
1180          return true;
1181        if (isPhysReg && isRegTiedToDefOperand(i))
1182          // Two-address uses of physregs must not be marked kill.
1183          return true;
1184        MO.setIsKill();
1185        Found = true;
1186      }
1187    } else if (hasAliases && MO.isKill() &&
1188               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1189      // A super-register kill already exists.
1190      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1191        return true;
1192      if (RegInfo->isSubRegister(IncomingReg, Reg))
1193        DeadOps.push_back(i);
1194    }
1195  }
1196
1197  // Trim unneeded kill operands.
1198  while (!DeadOps.empty()) {
1199    unsigned OpIdx = DeadOps.back();
1200    if (getOperand(OpIdx).isImplicit())
1201      RemoveOperand(OpIdx);
1202    else
1203      getOperand(OpIdx).setIsKill(false);
1204    DeadOps.pop_back();
1205  }
1206
1207  // If not found, this means an alias of one of the operands is killed. Add a
1208  // new implicit operand if required.
1209  if (!Found && AddIfNotFound) {
1210    addOperand(MachineOperand::CreateReg(IncomingReg,
1211                                         false /*IsDef*/,
1212                                         true  /*IsImp*/,
1213                                         true  /*IsKill*/));
1214    return true;
1215  }
1216  return Found;
1217}
1218
1219bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1220                                   const TargetRegisterInfo *RegInfo,
1221                                   bool AddIfNotFound) {
1222  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1223  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1224  bool Found = false;
1225  SmallVector<unsigned,4> DeadOps;
1226  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1227    MachineOperand &MO = getOperand(i);
1228    if (!MO.isReg() || !MO.isDef())
1229      continue;
1230    unsigned Reg = MO.getReg();
1231    if (!Reg)
1232      continue;
1233
1234    if (Reg == IncomingReg) {
1235      if (!Found) {
1236        if (MO.isDead())
1237          // The register is already marked dead.
1238          return true;
1239        MO.setIsDead();
1240        Found = true;
1241      }
1242    } else if (hasAliases && MO.isDead() &&
1243               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1244      // There exists a super-register that's marked dead.
1245      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1246        return true;
1247      if (RegInfo->getSubRegisters(IncomingReg) &&
1248          RegInfo->getSuperRegisters(Reg) &&
1249          RegInfo->isSubRegister(IncomingReg, Reg))
1250        DeadOps.push_back(i);
1251    }
1252  }
1253
1254  // Trim unneeded dead operands.
1255  while (!DeadOps.empty()) {
1256    unsigned OpIdx = DeadOps.back();
1257    if (getOperand(OpIdx).isImplicit())
1258      RemoveOperand(OpIdx);
1259    else
1260      getOperand(OpIdx).setIsDead(false);
1261    DeadOps.pop_back();
1262  }
1263
1264  // If not found, this means an alias of one of the operands is dead. Add a
1265  // new implicit operand if required.
1266  if (Found || !AddIfNotFound)
1267    return Found;
1268
1269  addOperand(MachineOperand::CreateReg(IncomingReg,
1270                                       true  /*IsDef*/,
1271                                       true  /*IsImp*/,
1272                                       false /*IsKill*/,
1273                                       true  /*IsDead*/));
1274  return true;
1275}
1276