MachineInstr.cpp revision 2a79a0927c479b69316aa275c1f79c74d20e8040 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//===----------------------------------------------------------------------===//
4
5#include "llvm/CodeGen/MachineInstr.h"
6#include "llvm/CodeGen/MachineBasicBlock.h"
7#include "llvm/Value.h"
8#include "llvm/Target/MachineInstrInfo.h"  // FIXME: shouldn't need this!
9#include "llvm/Target/TargetMachine.h"
10#include "llvm/Target/MRegisterInfo.h"
11using std::cerr;
12
13// Global variable holding an array of descriptors for machine instructions.
14// The actual object needs to be created separately for each target machine.
15// This variable is initialized and reset by class MachineInstrInfo.
16//
17// FIXME: This should be a property of the target so that more than one target
18// at a time can be active...
19//
20extern const MachineInstrDescriptor *TargetInstrDescriptors;
21
22// Constructor for instructions with fixed #operands (nearly all)
23MachineInstr::MachineInstr(MachineOpCode _opCode)
24  : opCode(_opCode),
25    operands(TargetInstrDescriptors[_opCode].numOperands, MachineOperand()),
26    numImplicitRefs(0)
27{
28  assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
29}
30
31// Constructor for instructions with variable #operands
32MachineInstr::MachineInstr(MachineOpCode OpCode, unsigned  numOperands)
33  : opCode(OpCode),
34    operands(numOperands, MachineOperand()),
35    numImplicitRefs(0)
36{
37}
38
39/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
40/// not a resize for them.  It is expected that if you use this that you call
41/// add* methods below to fill up the operands, instead of the Set methods.
42/// Eventually, the "resizing" ctors will be phased out.
43///
44MachineInstr::MachineInstr(MachineOpCode Opcode, unsigned numOperands,
45                           bool XX, bool YY)
46  : opCode(Opcode),
47    numImplicitRefs(0)
48{
49  operands.reserve(numOperands);
50}
51
52/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
53/// MachineInstr is created and added to the end of the specified basic block.
54///
55MachineInstr::MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode,
56                           unsigned numOperands)
57  : opCode(Opcode),
58    numImplicitRefs(0)
59{
60  assert(MBB && "Cannot use inserting ctor with null basic block!");
61  operands.reserve(numOperands);
62  MBB->push_back(this);  // Add instruction to end of basic block!
63}
64
65
66// OperandComplete - Return true if it's illegal to add a new operand
67bool MachineInstr::OperandsComplete() const
68{
69  int NumOperands = TargetInstrDescriptors[opCode].numOperands;
70  if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
71    return true;  // Broken!
72  return false;
73}
74
75
76//
77// Support for replacing opcode and operands of a MachineInstr in place.
78// This only resets the size of the operand vector and initializes it.
79// The new operands must be set explicitly later.
80//
81void MachineInstr::replace(MachineOpCode Opcode, unsigned numOperands)
82{
83  assert(getNumImplicitRefs() == 0 &&
84         "This is probably broken because implicit refs are going to be lost.");
85  opCode = Opcode;
86  operands.clear();
87  operands.resize(numOperands, MachineOperand());
88}
89
90void
91MachineInstr::SetMachineOperandVal(unsigned i,
92                                   MachineOperand::MachineOperandType opType,
93                                   Value* V,
94                                   bool isdef,
95                                   bool isDefAndUse)
96{
97  assert(i < operands.size());          // may be explicit or implicit op
98  operands[i].opType = opType;
99  operands[i].value = V;
100  operands[i].regNum = -1;
101  operands[i].flags = 0;
102
103  if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
104    operands[i].markDef();
105  if (isDefAndUse)
106    operands[i].markDefAndUse();
107}
108
109void
110MachineInstr::SetMachineOperandConst(unsigned i,
111				MachineOperand::MachineOperandType operandType,
112                                     int64_t intValue)
113{
114  assert(i < getNumOperands());          // must be explicit op
115  assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
116         "immed. constant cannot be defined");
117
118  operands[i].opType = operandType;
119  operands[i].value = NULL;
120  operands[i].immedVal = intValue;
121  operands[i].regNum = -1;
122  operands[i].flags = 0;
123}
124
125void
126MachineInstr::SetMachineOperandReg(unsigned i,
127                                   int regNum,
128                                   bool isdef) {
129  assert(i < getNumOperands());          // must be explicit op
130
131  operands[i].opType = MachineOperand::MO_MachineRegister;
132  operands[i].value = NULL;
133  operands[i].regNum = regNum;
134  operands[i].flags = 0;
135
136  if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
137    operands[i].markDef();
138  insertUsedReg(regNum);
139}
140
141void
142MachineInstr::SetRegForOperand(unsigned i, int regNum)
143{
144  assert(i < getNumOperands());          // must be explicit op
145  operands[i].setRegForValue(regNum);
146  insertUsedReg(regNum);
147}
148
149
150// Subsitute all occurrences of Value* oldVal with newVal in all operands
151// and all implicit refs.  If defsOnly == true, substitute defs only.
152unsigned
153MachineInstr::substituteValue(const Value* oldVal, Value* newVal, bool defsOnly)
154{
155  unsigned numSubst = 0;
156
157  // Subsitute operands
158  for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
159    if (*O == oldVal)
160      if (!defsOnly || O.isDef())
161        {
162          O.getMachineOperand().value = newVal;
163          ++numSubst;
164        }
165
166  // Subsitute implicit refs
167  for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
168    if (getImplicitRef(i) == oldVal)
169      if (!defsOnly || implicitRefIsDefined(i))
170        {
171          getImplicitOp(i).value = newVal;
172          ++numSubst;
173        }
174
175  return numSubst;
176}
177
178
179void
180MachineInstr::dump() const
181{
182  cerr << "  " << *this;
183}
184
185static inline std::ostream&
186OutputValue(std::ostream &os, const Value* val)
187{
188  os << "(val ";
189  if (val && val->hasName())
190    return os << val->getName() << ")";
191  else
192    return os << (void*) val << ")";              // print address only
193}
194
195static inline void OutputReg(std::ostream &os, unsigned RegNo,
196                             const MRegisterInfo *MRI = 0) {
197  if (MRI) {
198    if (RegNo < MRegisterInfo::FirstVirtualRegister)
199      os << "%" << MRI->get(RegNo).Name;
200    else
201      os << "%reg" << RegNo;
202  } else
203    os << "%mreg(" << RegNo << ")";
204}
205
206static void print(const MachineOperand &MO, std::ostream &OS,
207                  const TargetMachine &TM) {
208  const MRegisterInfo *MRI = TM.getRegisterInfo();
209  bool CloseParen = true;
210  if (MO.opHiBits32())
211    OS << "%lm(";
212  else if (MO.opLoBits32())
213    OS << "%lo(";
214  else if (MO.opHiBits64())
215    OS << "%hh(";
216  else if (MO.opLoBits64())
217    OS << "%hm(";
218  else
219    CloseParen = false;
220
221  switch (MO.getType()) {
222  case MachineOperand::MO_VirtualRegister:
223    if (MO.getVRegValue()) {
224      OS << "%reg";
225      OutputValue(OS, MO.getVRegValue());
226      if (MO.hasAllocatedReg())
227        OS << "==";
228    }
229    if (MO.hasAllocatedReg())
230      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
231    break;
232  case MachineOperand::MO_CCRegister:
233    OS << "%ccreg";
234    OutputValue(OS, MO.getVRegValue());
235    if (MO.hasAllocatedReg()) {
236      OS << "==";
237      OutputReg(OS, MO.getAllocatedRegNum(), MRI);
238    }
239    break;
240  case MachineOperand::MO_MachineRegister:
241    OutputReg(OS, MO.getMachineRegNum(), MRI);
242    break;
243  case MachineOperand::MO_SignExtendedImmed:
244    OS << (long)MO.getImmedValue();
245    break;
246  case MachineOperand::MO_UnextendedImmed:
247    OS << (long)MO.getImmedValue();
248    break;
249  case MachineOperand::MO_PCRelativeDisp: {
250    const Value* opVal = MO.getVRegValue();
251    bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
252    OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
253    if (opVal->hasName())
254      OS << opVal->getName();
255    else
256      OS << (const void*) opVal;
257    OS << ")";
258    break;
259  }
260  default:
261    assert(0 && "Unrecognized operand type");
262  }
263
264  if (CloseParen)
265    OS << ")";
266}
267
268void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) {
269  OS << TM.getInstrInfo().getName(getOpcode());
270  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
271    OS << "\t";
272    ::print(getOperand(i), OS, TM);
273
274    if (operandIsDefinedAndUsed(i))
275      OS << "<def&use>";
276    else if (operandIsDefined(i))
277      OS << "<def>";
278  }
279
280  // code for printing implict references
281  if (getNumImplicitRefs()) {
282    OS << "\tImplicitRefs: ";
283    for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
284      OS << "\t";
285      OutputValue(OS, getImplicitRef(i));
286      if (implicitRefIsDefinedAndUsed(i))
287        OS << "<def&use>";
288      else if (implicitRefIsDefined(i))
289        OS << "<def>";
290    }
291  }
292
293  OS << "\n";
294}
295
296
297std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
298{
299  os << TargetInstrDescriptors[minstr.opCode].Name;
300
301  for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
302    os << "\t" << minstr.getOperand(i);
303    if( minstr.operandIsDefined(i) )
304      os << "*";
305    if( minstr.operandIsDefinedAndUsed(i) )
306      os << "*";
307  }
308
309  // code for printing implict references
310  unsigned NumOfImpRefs =  minstr.getNumImplicitRefs();
311  if(  NumOfImpRefs > 0 ) {
312    os << "\tImplicit: ";
313    for(unsigned z=0; z < NumOfImpRefs; z++) {
314      OutputValue(os, minstr.getImplicitRef(z));
315      if( minstr.implicitRefIsDefined(z)) os << "*";
316      if( minstr.implicitRefIsDefinedAndUsed(z)) os << "*";
317      os << "\t";
318    }
319  }
320
321  return os << "\n";
322}
323
324std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
325{
326  if (mop.opHiBits32())
327    os << "%lm(";
328  else if (mop.opLoBits32())
329    os << "%lo(";
330  else if (mop.opHiBits64())
331    os << "%hh(";
332  else if (mop.opLoBits64())
333    os << "%hm(";
334
335  switch (mop.getType())
336    {
337    case MachineOperand::MO_VirtualRegister:
338      os << "%reg";
339      OutputValue(os, mop.getVRegValue());
340      if (mop.hasAllocatedReg()) {
341        os << "==";
342        OutputReg(os, mop.getAllocatedRegNum());
343      }
344      break;
345    case MachineOperand::MO_CCRegister:
346      os << "%ccreg";
347      OutputValue(os, mop.getVRegValue());
348      if (mop.hasAllocatedReg()) {
349        os << "==";
350        OutputReg(os, mop.getAllocatedRegNum());
351      }
352      break;
353    case MachineOperand::MO_MachineRegister:
354      OutputReg(os, mop.getMachineRegNum());
355      break;
356    case MachineOperand::MO_SignExtendedImmed:
357      os << (long)mop.getImmedValue();
358      break;
359    case MachineOperand::MO_UnextendedImmed:
360      os << (long)mop.getImmedValue();
361      break;
362    case MachineOperand::MO_PCRelativeDisp:
363      {
364        const Value* opVal = mop.getVRegValue();
365        bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
366        os << "%disp(" << (isLabel? "label " : "addr-of-val ");
367        if (opVal->hasName())
368          os << opVal->getName();
369        else
370          os << (const void*) opVal;
371        os << ")";
372        break;
373      }
374    default:
375      assert(0 && "Unrecognized operand type");
376      break;
377    }
378
379  if (mop.flags &
380      (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
381       MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
382    os << ")";
383
384  return os;
385}
386