MachineInstr.cpp revision 2fcbc7e8303dfee61147d76bbf16ed0297133c77 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetInstrDesc.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Support/LeakDetector.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/Streams.h"
27#include <ostream>
28using namespace llvm;
29
30//===----------------------------------------------------------------------===//
31// MachineOperand Implementation
32//===----------------------------------------------------------------------===//
33
34/// AddRegOperandToRegInfo - Add this register operand to the specified
35/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
36/// explicitly nulled out.
37void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
38  assert(isReg() && "Can only add reg operand to use lists");
39
40  // If the reginfo pointer is null, just explicitly null out or next/prev
41  // pointers, to ensure they are not garbage.
42  if (RegInfo == 0) {
43    Contents.Reg.Prev = 0;
44    Contents.Reg.Next = 0;
45    return;
46  }
47
48  // Otherwise, add this operand to the head of the registers use/def list.
49  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
50
51  // For SSA values, we prefer to keep the definition at the start of the list.
52  // we do this by skipping over the definition if it is at the head of the
53  // list.
54  if (*Head && (*Head)->isDef())
55    Head = &(*Head)->Contents.Reg.Next;
56
57  Contents.Reg.Next = *Head;
58  if (Contents.Reg.Next) {
59    assert(getReg() == Contents.Reg.Next->getReg() &&
60           "Different regs on the same list!");
61    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
62  }
63
64  Contents.Reg.Prev = Head;
65  *Head = this;
66}
67
68void MachineOperand::setReg(unsigned Reg) {
69  if (getReg() == Reg) return; // No change.
70
71  // Otherwise, we have to change the register.  If this operand is embedded
72  // into a machine function, we need to update the old and new register's
73  // use/def lists.
74  if (MachineInstr *MI = getParent())
75    if (MachineBasicBlock *MBB = MI->getParent())
76      if (MachineFunction *MF = MBB->getParent()) {
77        RemoveRegOperandFromRegInfo();
78        Contents.Reg.RegNo = Reg;
79        AddRegOperandToRegInfo(&MF->getRegInfo());
80        return;
81      }
82
83  // Otherwise, just change the register, no problem.  :)
84  Contents.Reg.RegNo = Reg;
85}
86
87/// ChangeToImmediate - Replace this operand with a new immediate operand of
88/// the specified value.  If an operand is known to be an immediate already,
89/// the setImm method should be used.
90void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
91  // If this operand is currently a register operand, and if this is in a
92  // function, deregister the operand from the register's use/def list.
93  if (isReg() && getParent() && getParent()->getParent() &&
94      getParent()->getParent()->getParent())
95    RemoveRegOperandFromRegInfo();
96
97  OpKind = MO_Immediate;
98  Contents.ImmVal = ImmVal;
99}
100
101/// ChangeToRegister - Replace this operand with a new register operand of
102/// the specified value.  If an operand is known to be an register already,
103/// the setReg method should be used.
104void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
105                                      bool isKill, bool isDead) {
106  // If this operand is already a register operand, use setReg to update the
107  // register's use/def lists.
108  if (isReg()) {
109    setReg(Reg);
110  } else {
111    // Otherwise, change this to a register and set the reg#.
112    OpKind = MO_Register;
113    Contents.Reg.RegNo = Reg;
114
115    // If this operand is embedded in a function, add the operand to the
116    // register's use/def list.
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          AddRegOperandToRegInfo(&MF->getRegInfo());
121  }
122
123  IsDef = isDef;
124  IsImp = isImp;
125  IsKill = isKill;
126  IsDead = isDead;
127  SubReg = 0;
128}
129
130/// isIdenticalTo - Return true if this operand is identical to the specified
131/// operand.
132bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
133  if (getType() != Other.getType()) return false;
134
135  switch (getType()) {
136  default: assert(0 && "Unrecognized operand type");
137  case MachineOperand::MO_Register:
138    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
139           getSubReg() == Other.getSubReg();
140  case MachineOperand::MO_Immediate:
141    return getImm() == Other.getImm();
142  case MachineOperand::MO_FPImmediate:
143    return getFPImm() == Other.getFPImm();
144  case MachineOperand::MO_MachineBasicBlock:
145    return getMBB() == Other.getMBB();
146  case MachineOperand::MO_FrameIndex:
147    return getIndex() == Other.getIndex();
148  case MachineOperand::MO_ConstantPoolIndex:
149    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
150  case MachineOperand::MO_JumpTableIndex:
151    return getIndex() == Other.getIndex();
152  case MachineOperand::MO_GlobalAddress:
153    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
154  case MachineOperand::MO_ExternalSymbol:
155    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
156           getOffset() == Other.getOffset();
157  }
158}
159
160/// print - Print the specified machine operand.
161///
162void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
163  switch (getType()) {
164  case MachineOperand::MO_Register:
165    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
166      OS << "%reg" << getReg();
167    } else {
168      // If the instruction is embedded into a basic block, we can find the
169      // target info for the instruction.
170      if (TM == 0)
171        if (const MachineInstr *MI = getParent())
172          if (const MachineBasicBlock *MBB = MI->getParent())
173            if (const MachineFunction *MF = MBB->getParent())
174              TM = &MF->getTarget();
175
176      if (TM)
177        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
178      else
179        OS << "%mreg" << getReg();
180    }
181
182    if (isDef() || isKill() || isDead() || isImplicit()) {
183      OS << "<";
184      bool NeedComma = false;
185      if (isImplicit()) {
186        OS << (isDef() ? "imp-def" : "imp-use");
187        NeedComma = true;
188      } else if (isDef()) {
189        OS << "def";
190        NeedComma = true;
191      }
192      if (isKill() || isDead()) {
193        if (NeedComma) OS << ",";
194        if (isKill())  OS << "kill";
195        if (isDead())  OS << "dead";
196      }
197      OS << ">";
198    }
199    break;
200  case MachineOperand::MO_Immediate:
201    OS << getImm();
202    break;
203  case MachineOperand::MO_FPImmediate:
204    if (getFPImm()->getType() == Type::FloatTy) {
205      OS << getFPImm()->getValueAPF().convertToFloat();
206    } else {
207      OS << getFPImm()->getValueAPF().convertToDouble();
208    }
209    break;
210  case MachineOperand::MO_MachineBasicBlock:
211    OS << "mbb<"
212       << ((Value*)getMBB()->getBasicBlock())->getName()
213       << "," << (void*)getMBB() << ">";
214    break;
215  case MachineOperand::MO_FrameIndex:
216    OS << "<fi#" << getIndex() << ">";
217    break;
218  case MachineOperand::MO_ConstantPoolIndex:
219    OS << "<cp#" << getIndex();
220    if (getOffset()) OS << "+" << getOffset();
221    OS << ">";
222    break;
223  case MachineOperand::MO_JumpTableIndex:
224    OS << "<jt#" << getIndex() << ">";
225    break;
226  case MachineOperand::MO_GlobalAddress:
227    OS << "<ga:" << ((Value*)getGlobal())->getName();
228    if (getOffset()) OS << "+" << getOffset();
229    OS << ">";
230    break;
231  case MachineOperand::MO_ExternalSymbol:
232    OS << "<es:" << getSymbolName();
233    if (getOffset()) OS << "+" << getOffset();
234    OS << ">";
235    break;
236  default:
237    assert(0 && "Unrecognized operand type");
238  }
239}
240
241//===----------------------------------------------------------------------===//
242// MachineMemOperand Implementation
243//===----------------------------------------------------------------------===//
244
245MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
246                                     int64_t o, uint64_t s, unsigned int a)
247  : Offset(o), Size(s), V(v),
248    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
249  assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
250  assert((isLoad() || isStore()) && "Not a load/store!");
251}
252
253//===----------------------------------------------------------------------===//
254// MachineInstr Implementation
255//===----------------------------------------------------------------------===//
256
257/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
258/// TID NULL and no operands.
259MachineInstr::MachineInstr()
260  : TID(0), NumImplicitOps(0), Parent(0) {
261  // Make sure that we get added to a machine basicblock
262  LeakDetector::addGarbageObject(this);
263}
264
265void MachineInstr::addImplicitDefUseOperands() {
266  if (TID->ImplicitDefs)
267    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
268      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
269  if (TID->ImplicitUses)
270    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
271      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
272}
273
274/// MachineInstr ctor - This constructor create a MachineInstr and add the
275/// implicit operands. It reserves space for number of operands specified by
276/// TargetInstrDesc or the numOperands if it is not zero. (for
277/// instructions with variable number of operands).
278MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
279  : TID(&tid), NumImplicitOps(0), Parent(0) {
280  if (!NoImp && TID->getImplicitDefs())
281    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
282      NumImplicitOps++;
283  if (!NoImp && TID->getImplicitUses())
284    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
285      NumImplicitOps++;
286  Operands.reserve(NumImplicitOps + TID->getNumOperands());
287  if (!NoImp)
288    addImplicitDefUseOperands();
289  // Make sure that we get added to a machine basicblock
290  LeakDetector::addGarbageObject(this);
291}
292
293/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
294/// MachineInstr is created and added to the end of the specified basic block.
295///
296MachineInstr::MachineInstr(MachineBasicBlock *MBB,
297                           const TargetInstrDesc &tid)
298  : TID(&tid), NumImplicitOps(0), Parent(0) {
299  assert(MBB && "Cannot use inserting ctor with null basic block!");
300  if (TID->ImplicitDefs)
301    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
302      NumImplicitOps++;
303  if (TID->ImplicitUses)
304    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
305      NumImplicitOps++;
306  Operands.reserve(NumImplicitOps + TID->getNumOperands());
307  addImplicitDefUseOperands();
308  // Make sure that we get added to a machine basicblock
309  LeakDetector::addGarbageObject(this);
310  MBB->push_back(this);  // Add instruction to end of basic block!
311}
312
313/// MachineInstr ctor - Copies MachineInstr arg exactly
314///
315MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
316  : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
317  Operands.reserve(MI.getNumOperands());
318
319  // Add operands
320  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
321    addOperand(MI.getOperand(i));
322  NumImplicitOps = MI.NumImplicitOps;
323
324  // Add memory operands.
325  for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
326       j = MI.memoperands_end(); i != j; ++i)
327    addMemOperand(MF, *i);
328
329  // Set parent to null.
330  Parent = 0;
331
332  LeakDetector::addGarbageObject(this);
333}
334
335MachineInstr::~MachineInstr() {
336  LeakDetector::removeGarbageObject(this);
337  assert(MemOperands.empty() &&
338         "MachineInstr being deleted with live memoperands!");
339#ifndef NDEBUG
340  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
341    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
342    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
343           "Reg operand def/use list corrupted");
344  }
345#endif
346}
347
348/// getOpcode - Returns the opcode of this MachineInstr.
349///
350int MachineInstr::getOpcode() const {
351  return TID->Opcode;
352}
353
354/// getRegInfo - If this instruction is embedded into a MachineFunction,
355/// return the MachineRegisterInfo object for the current function, otherwise
356/// return null.
357MachineRegisterInfo *MachineInstr::getRegInfo() {
358  if (MachineBasicBlock *MBB = getParent())
359    return &MBB->getParent()->getRegInfo();
360  return 0;
361}
362
363/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
364/// this instruction from their respective use lists.  This requires that the
365/// operands already be on their use lists.
366void MachineInstr::RemoveRegOperandsFromUseLists() {
367  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
368    if (Operands[i].isReg())
369      Operands[i].RemoveRegOperandFromRegInfo();
370  }
371}
372
373/// AddRegOperandsToUseLists - Add all of the register operands in
374/// this instruction from their respective use lists.  This requires that the
375/// operands not be on their use lists yet.
376void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
377  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
378    if (Operands[i].isReg())
379      Operands[i].AddRegOperandToRegInfo(&RegInfo);
380  }
381}
382
383
384/// addOperand - Add the specified operand to the instruction.  If it is an
385/// implicit operand, it is added to the end of the operand list.  If it is
386/// an explicit operand it is added at the end of the explicit operand list
387/// (before the first implicit operand).
388void MachineInstr::addOperand(const MachineOperand &Op) {
389  bool isImpReg = Op.isReg() && Op.isImplicit();
390  assert((isImpReg || !OperandsComplete()) &&
391         "Trying to add an operand to a machine instr that is already done!");
392
393  // If we are adding the operand to the end of the list, our job is simpler.
394  // This is true most of the time, so this is a reasonable optimization.
395  if (isImpReg || NumImplicitOps == 0) {
396    // We can only do this optimization if we know that the operand list won't
397    // reallocate.
398    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
399      Operands.push_back(Op);
400
401      // Set the parent of the operand.
402      Operands.back().ParentMI = this;
403
404      // If the operand is a register, update the operand's use list.
405      if (Op.isReg())
406        Operands.back().AddRegOperandToRegInfo(getRegInfo());
407      return;
408    }
409  }
410
411  // Otherwise, we have to insert a real operand before any implicit ones.
412  unsigned OpNo = Operands.size()-NumImplicitOps;
413
414  MachineRegisterInfo *RegInfo = getRegInfo();
415
416  // If this instruction isn't embedded into a function, then we don't need to
417  // update any operand lists.
418  if (RegInfo == 0) {
419    // Simple insertion, no reginfo update needed for other register operands.
420    Operands.insert(Operands.begin()+OpNo, Op);
421    Operands[OpNo].ParentMI = this;
422
423    // Do explicitly set the reginfo for this operand though, to ensure the
424    // next/prev fields are properly nulled out.
425    if (Operands[OpNo].isReg())
426      Operands[OpNo].AddRegOperandToRegInfo(0);
427
428  } else if (Operands.size()+1 <= Operands.capacity()) {
429    // Otherwise, we have to remove register operands from their register use
430    // list, add the operand, then add the register operands back to their use
431    // list.  This also must handle the case when the operand list reallocates
432    // to somewhere else.
433
434    // If insertion of this operand won't cause reallocation of the operand
435    // list, just remove the implicit operands, add the operand, then re-add all
436    // the rest of the operands.
437    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
438      assert(Operands[i].isReg() && "Should only be an implicit reg!");
439      Operands[i].RemoveRegOperandFromRegInfo();
440    }
441
442    // Add the operand.  If it is a register, add it to the reg list.
443    Operands.insert(Operands.begin()+OpNo, Op);
444    Operands[OpNo].ParentMI = this;
445
446    if (Operands[OpNo].isReg())
447      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
448
449    // Re-add all the implicit ops.
450    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
451      assert(Operands[i].isReg() && "Should only be an implicit reg!");
452      Operands[i].AddRegOperandToRegInfo(RegInfo);
453    }
454  } else {
455    // Otherwise, we will be reallocating the operand list.  Remove all reg
456    // operands from their list, then readd them after the operand list is
457    // reallocated.
458    RemoveRegOperandsFromUseLists();
459
460    Operands.insert(Operands.begin()+OpNo, Op);
461    Operands[OpNo].ParentMI = this;
462
463    // Re-add all the operands.
464    AddRegOperandsToUseLists(*RegInfo);
465  }
466}
467
468/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
469/// fewer operand than it started with.
470///
471void MachineInstr::RemoveOperand(unsigned OpNo) {
472  assert(OpNo < Operands.size() && "Invalid operand number");
473
474  // Special case removing the last one.
475  if (OpNo == Operands.size()-1) {
476    // If needed, remove from the reg def/use list.
477    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
478      Operands.back().RemoveRegOperandFromRegInfo();
479
480    Operands.pop_back();
481    return;
482  }
483
484  // Otherwise, we are removing an interior operand.  If we have reginfo to
485  // update, remove all operands that will be shifted down from their reg lists,
486  // move everything down, then re-add them.
487  MachineRegisterInfo *RegInfo = getRegInfo();
488  if (RegInfo) {
489    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
490      if (Operands[i].isReg())
491        Operands[i].RemoveRegOperandFromRegInfo();
492    }
493  }
494
495  Operands.erase(Operands.begin()+OpNo);
496
497  if (RegInfo) {
498    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
499      if (Operands[i].isReg())
500        Operands[i].AddRegOperandToRegInfo(RegInfo);
501    }
502  }
503}
504
505/// addMemOperand - Add a MachineMemOperand to the machine instruction,
506/// referencing arbitrary storage.
507void MachineInstr::addMemOperand(MachineFunction &MF,
508                                 const MachineMemOperand &MO) {
509  MemOperands.push_back(MO);
510}
511
512/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
513void MachineInstr::clearMemOperands(MachineFunction &MF) {
514  MemOperands.clear();
515}
516
517
518/// removeFromParent - This method unlinks 'this' from the containing basic
519/// block, and returns it, but does not delete it.
520MachineInstr *MachineInstr::removeFromParent() {
521  assert(getParent() && "Not embedded in a basic block!");
522  getParent()->remove(this);
523  return this;
524}
525
526
527/// eraseFromParent - This method unlinks 'this' from the containing basic
528/// block, and deletes it.
529void MachineInstr::eraseFromParent() {
530  assert(getParent() && "Not embedded in a basic block!");
531  getParent()->erase(this);
532}
533
534
535/// OperandComplete - Return true if it's illegal to add a new operand
536///
537bool MachineInstr::OperandsComplete() const {
538  unsigned short NumOperands = TID->getNumOperands();
539  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
540    return true;  // Broken: we have all the operands of this instruction!
541  return false;
542}
543
544/// getNumExplicitOperands - Returns the number of non-implicit operands.
545///
546unsigned MachineInstr::getNumExplicitOperands() const {
547  unsigned NumOperands = TID->getNumOperands();
548  if (!TID->isVariadic())
549    return NumOperands;
550
551  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
552    const MachineOperand &MO = getOperand(NumOperands);
553    if (!MO.isRegister() || !MO.isImplicit())
554      NumOperands++;
555  }
556  return NumOperands;
557}
558
559
560/// isLabel - Returns true if the MachineInstr represents a label.
561///
562bool MachineInstr::isLabel() const {
563  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
564         getOpcode() == TargetInstrInfo::EH_LABEL ||
565         getOpcode() == TargetInstrInfo::GC_LABEL;
566}
567
568/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
569///
570bool MachineInstr::isDebugLabel() const {
571  return getOpcode() == TargetInstrInfo::DBG_LABEL;
572}
573
574/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
575/// the specific register or -1 if it is not found. It further tightening
576/// the search criteria to a use that kills the register if isKill is true.
577int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
578                                          const TargetRegisterInfo *TRI) const {
579  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
580    const MachineOperand &MO = getOperand(i);
581    if (!MO.isRegister() || !MO.isUse())
582      continue;
583    unsigned MOReg = MO.getReg();
584    if (!MOReg)
585      continue;
586    if (MOReg == Reg ||
587        (TRI &&
588         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
589         TargetRegisterInfo::isPhysicalRegister(Reg) &&
590         TRI->isSubRegister(MOReg, Reg)))
591      if (!isKill || MO.isKill())
592        return i;
593  }
594  return -1;
595}
596
597/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
598/// the specified register or -1 if it is not found. If isDead is true, defs
599/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
600/// also checks if there is a def of a super-register.
601int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
602                                          const TargetRegisterInfo *TRI) const {
603  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
604    const MachineOperand &MO = getOperand(i);
605    if (!MO.isRegister() || !MO.isDef())
606      continue;
607    unsigned MOReg = MO.getReg();
608    if (MOReg == Reg ||
609        (TRI &&
610         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
611         TargetRegisterInfo::isPhysicalRegister(Reg) &&
612         TRI->isSubRegister(MOReg, Reg)))
613      if (!isDead || MO.isDead())
614        return i;
615  }
616  return -1;
617}
618
619/// findFirstPredOperandIdx() - Find the index of the first operand in the
620/// operand list that is used to represent the predicate. It returns -1 if
621/// none is found.
622int MachineInstr::findFirstPredOperandIdx() const {
623  const TargetInstrDesc &TID = getDesc();
624  if (TID.isPredicable()) {
625    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
626      if (TID.OpInfo[i].isPredicate())
627        return i;
628  }
629
630  return -1;
631}
632
633/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
634/// check if the register def is a re-definition due to two addr elimination.
635bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
636  const TargetInstrDesc &TID = getDesc();
637  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
638    const MachineOperand &MO = getOperand(i);
639    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
640        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
641      return true;
642  }
643  return false;
644}
645
646/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
647///
648void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
649  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
650    const MachineOperand &MO = MI->getOperand(i);
651    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
652      continue;
653    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
654      MachineOperand &MOp = getOperand(j);
655      if (!MOp.isIdenticalTo(MO))
656        continue;
657      if (MO.isKill())
658        MOp.setIsKill();
659      else
660        MOp.setIsDead();
661      break;
662    }
663  }
664}
665
666/// copyPredicates - Copies predicate operand(s) from MI.
667void MachineInstr::copyPredicates(const MachineInstr *MI) {
668  const TargetInstrDesc &TID = MI->getDesc();
669  if (!TID.isPredicable())
670    return;
671  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
672    if (TID.OpInfo[i].isPredicate()) {
673      // Predicated operands must be last operands.
674      addOperand(MI->getOperand(i));
675    }
676  }
677}
678
679/// isSafeToMove - Return true if it is safe to move this instruction. If
680/// SawStore is set to true, it means that there is a store (or call) between
681/// the instruction's location and its intended destination.
682bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
683  // Ignore stuff that we obviously can't move.
684  if (TID->mayStore() || TID->isCall()) {
685    SawStore = true;
686    return false;
687  }
688  if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
689    return false;
690
691  // See if this instruction does a load.  If so, we have to guarantee that the
692  // loaded value doesn't change between the load and the its intended
693  // destination. The check for isInvariantLoad gives the targe the chance to
694  // classify the load as always returning a constant, e.g. a constant pool
695  // load.
696  if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
697    // Otherwise, this is a real load.  If there is a store between the load and
698    // end of block, we can't sink the load.
699    //
700    // FIXME: we can't do this transformation until we know that the load is
701    // not volatile, and machineinstrs don't keep this info. :(
702    //
703    //if (SawStore)
704    return false;
705  }
706  return true;
707}
708
709void MachineInstr::dump() const {
710  cerr << "  " << *this;
711}
712
713void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
714  // Specialize printing if op#0 is definition
715  unsigned StartOp = 0;
716  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
717    getOperand(0).print(OS, TM);
718    OS << " = ";
719    ++StartOp;   // Don't print this operand again!
720  }
721
722  OS << getDesc().getName();
723
724  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
725    if (i != StartOp)
726      OS << ",";
727    OS << " ";
728    getOperand(i).print(OS, TM);
729  }
730
731  if (!memoperands_empty()) {
732    OS << ", Mem:";
733    for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
734         e = memoperands_end(); i != e; ++i) {
735      const MachineMemOperand &MRO = *i;
736      const Value *V = MRO.getValue();
737
738      assert((MRO.isLoad() || MRO.isStore()) &&
739             "SV has to be a load, store or both.");
740
741      if (MRO.isVolatile())
742        OS << "Volatile ";
743
744      if (MRO.isLoad())
745        OS << "LD";
746      if (MRO.isStore())
747        OS << "ST";
748
749      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
750
751      if (!V)
752        OS << "<unknown>";
753      else if (!V->getName().empty())
754        OS << V->getName();
755      else if (isa<PseudoSourceValue>(V))
756        OS << *V;
757      else
758        OS << V;
759
760      OS << " + " << MRO.getOffset() << "]";
761    }
762  }
763
764  OS << "\n";
765}
766
767bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
768                                     const TargetRegisterInfo *RegInfo,
769                                     bool AddIfNotFound) {
770  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
771  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
772  SmallVector<unsigned,4> DeadOps;
773  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
774    MachineOperand &MO = getOperand(i);
775    if (!MO.isRegister() || !MO.isUse())
776      continue;
777    unsigned Reg = MO.getReg();
778    if (!Reg)
779      continue;
780
781    if (Reg == IncomingReg) {
782      MO.setIsKill();
783      return true;
784    }
785    if (hasAliases && MO.isKill() &&
786        TargetRegisterInfo::isPhysicalRegister(Reg)) {
787      // A super-register kill already exists.
788      if (RegInfo->isSuperRegister(IncomingReg, Reg))
789        return true;
790      if (RegInfo->isSubRegister(IncomingReg, Reg))
791        DeadOps.push_back(i);
792    }
793  }
794
795  // Trim unneeded kill operands.
796  while (!DeadOps.empty()) {
797    unsigned OpIdx = DeadOps.back();
798    if (getOperand(OpIdx).isImplicit())
799      RemoveOperand(OpIdx);
800    else
801      getOperand(OpIdx).setIsKill(false);
802    DeadOps.pop_back();
803  }
804
805  // If not found, this means an alias of one of the operands is killed. Add a
806  // new implicit operand if required.
807  if (AddIfNotFound) {
808    addOperand(MachineOperand::CreateReg(IncomingReg,
809                                         false /*IsDef*/,
810                                         true  /*IsImp*/,
811                                         true  /*IsKill*/));
812    return true;
813  }
814  return false;
815}
816
817bool MachineInstr::addRegisterDead(unsigned IncomingReg,
818                                   const TargetRegisterInfo *RegInfo,
819                                   bool AddIfNotFound) {
820  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
821  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
822  SmallVector<unsigned,4> DeadOps;
823  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
824    MachineOperand &MO = getOperand(i);
825    if (!MO.isRegister() || !MO.isDef())
826      continue;
827    unsigned Reg = MO.getReg();
828    if (Reg == IncomingReg) {
829      MO.setIsDead();
830      return true;
831    }
832    if (hasAliases && MO.isDead() &&
833        TargetRegisterInfo::isPhysicalRegister(Reg)) {
834      // There exists a super-register that's marked dead.
835      if (RegInfo->isSuperRegister(IncomingReg, Reg))
836        return true;
837      if (RegInfo->isSubRegister(IncomingReg, Reg))
838        DeadOps.push_back(i);
839    }
840  }
841
842  // Trim unneeded dead operands.
843  while (!DeadOps.empty()) {
844    unsigned OpIdx = DeadOps.back();
845    if (getOperand(OpIdx).isImplicit())
846      RemoveOperand(OpIdx);
847    else
848      getOperand(OpIdx).setIsDead(false);
849    DeadOps.pop_back();
850  }
851
852  // If not found, this means an alias of one of the operand is dead. Add a
853  // new implicit operand.
854  if (AddIfNotFound) {
855    addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
856                                         true/*IsImp*/,false/*IsKill*/,
857                                         true/*IsDead*/));
858    return true;
859  }
860  return false;
861}
862