MachineInstr.cpp revision 349c4952009525b27383e2120a6b3c998f39bd09
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Value.h"
16#include "llvm/CodeGen/MachineFunction.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetInstrInfo.h"
20#include "llvm/Target/MRegisterInfo.h"
21#include "llvm/Support/LeakDetector.h"
22#include "llvm/Support/Streams.h"
23#include <ostream>
24using namespace llvm;
25
26//===----------------------------------------------------------------------===//
27// MachineOperand Implementation
28//===----------------------------------------------------------------------===//
29
30/// AddRegOperandToRegInfo - Add this register operand to the specified
31/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
32/// explicitly nulled out.
33void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
34  assert(isReg() && "Can only add reg operand to use lists");
35
36  // If the reginfo pointer is null, just explicitly null out or next/prev
37  // pointers, to ensure they are not garbage.
38  if (RegInfo == 0) {
39    Contents.Reg.Prev = 0;
40    Contents.Reg.Next = 0;
41    return;
42  }
43
44  // Otherwise, add this operand to the head of the registers use/def list.
45  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
46
47  // For SSA values, we prefer to keep the definition at the start of the list.
48  // we do this by skipping over the definition if it is at the head of the
49  // list.
50  if (*Head && (*Head)->isDef())
51    Head = &(*Head)->Contents.Reg.Next;
52
53  Contents.Reg.Next = *Head;
54  if (Contents.Reg.Next) {
55    assert(getReg() == Contents.Reg.Next->getReg() &&
56           "Different regs on the same list!");
57    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
58  }
59
60  Contents.Reg.Prev = Head;
61  *Head = this;
62}
63
64void MachineOperand::setReg(unsigned Reg) {
65  if (getReg() == Reg) return; // No change.
66
67  // Otherwise, we have to change the register.  If this operand is embedded
68  // into a machine function, we need to update the old and new register's
69  // use/def lists.
70  if (MachineInstr *MI = getParent())
71    if (MachineBasicBlock *MBB = MI->getParent())
72      if (MachineFunction *MF = MBB->getParent()) {
73        RemoveRegOperandFromRegInfo();
74        Contents.Reg.RegNo = Reg;
75        AddRegOperandToRegInfo(&MF->getRegInfo());
76        return;
77      }
78
79  // Otherwise, just change the register, no problem.  :)
80  Contents.Reg.RegNo = Reg;
81}
82
83/// ChangeToImmediate - Replace this operand with a new immediate operand of
84/// the specified value.  If an operand is known to be an immediate already,
85/// the setImm method should be used.
86void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
87  // If this operand is currently a register operand, and if this is in a
88  // function, deregister the operand from the register's use/def list.
89  if (isReg() && getParent() && getParent()->getParent() &&
90      getParent()->getParent()->getParent())
91    RemoveRegOperandFromRegInfo();
92
93  OpKind = MO_Immediate;
94  Contents.ImmVal = ImmVal;
95}
96
97/// ChangeToRegister - Replace this operand with a new register operand of
98/// the specified value.  If an operand is known to be an register already,
99/// the setReg method should be used.
100void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
101                                      bool isKill, bool isDead) {
102  // If this operand is already a register operand, use setReg to update the
103  // register's use/def lists.
104  if (isReg()) {
105    setReg(Reg);
106  } else {
107    // Otherwise, change this to a register and set the reg#.
108    OpKind = MO_Register;
109    Contents.Reg.RegNo = Reg;
110
111    // If this operand is embedded in a function, add the operand to the
112    // register's use/def list.
113    if (MachineInstr *MI = getParent())
114      if (MachineBasicBlock *MBB = MI->getParent())
115        if (MachineFunction *MF = MBB->getParent())
116          AddRegOperandToRegInfo(&MF->getRegInfo());
117  }
118
119  IsDef = isDef;
120  IsImp = isImp;
121  IsKill = isKill;
122  IsDead = isDead;
123  SubReg = 0;
124}
125
126/// isIdenticalTo - Return true if this operand is identical to the specified
127/// operand.
128bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
129  if (getType() != Other.getType()) return false;
130
131  switch (getType()) {
132  default: assert(0 && "Unrecognized operand type");
133  case MachineOperand::MO_Register:
134    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
135           getSubReg() == Other.getSubReg();
136  case MachineOperand::MO_Immediate:
137    return getImm() == Other.getImm();
138  case MachineOperand::MO_MachineBasicBlock:
139    return getMBB() == Other.getMBB();
140  case MachineOperand::MO_FrameIndex:
141    return getIndex() == Other.getIndex();
142  case MachineOperand::MO_ConstantPoolIndex:
143    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
144  case MachineOperand::MO_JumpTableIndex:
145    return getIndex() == Other.getIndex();
146  case MachineOperand::MO_GlobalAddress:
147    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
148  case MachineOperand::MO_ExternalSymbol:
149    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
150           getOffset() == Other.getOffset();
151  }
152}
153
154/// print - Print the specified machine operand.
155///
156void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
157  switch (getType()) {
158  case MachineOperand::MO_Register:
159    if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
160      OS << "%reg" << getReg();
161    } else {
162      // If the instruction is embedded into a basic block, we can find the
163      // target info for the instruction.
164      if (TM == 0)
165        if (const MachineInstr *MI = getParent())
166          if (const MachineBasicBlock *MBB = MI->getParent())
167            if (const MachineFunction *MF = MBB->getParent())
168              TM = &MF->getTarget();
169
170      if (TM)
171        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
172      else
173        OS << "%mreg" << getReg();
174    }
175
176    if (isDef() || isKill() || isDead() || isImplicit()) {
177      OS << "<";
178      bool NeedComma = false;
179      if (isImplicit()) {
180        OS << (isDef() ? "imp-def" : "imp-use");
181        NeedComma = true;
182      } else if (isDef()) {
183        OS << "def";
184        NeedComma = true;
185      }
186      if (isKill() || isDead()) {
187        if (NeedComma)    OS << ",";
188        if (isKill()) OS << "kill";
189        if (isDead()) OS << "dead";
190      }
191      OS << ">";
192    }
193    break;
194  case MachineOperand::MO_Immediate:
195    OS << getImm();
196    break;
197  case MachineOperand::MO_MachineBasicBlock:
198    OS << "mbb<"
199       << ((Value*)getMBB()->getBasicBlock())->getName()
200       << "," << (void*)getMBB() << ">";
201    break;
202  case MachineOperand::MO_FrameIndex:
203    OS << "<fi#" << getIndex() << ">";
204    break;
205  case MachineOperand::MO_ConstantPoolIndex:
206    OS << "<cp#" << getIndex();
207    if (getOffset()) OS << "+" << getOffset();
208    OS << ">";
209    break;
210  case MachineOperand::MO_JumpTableIndex:
211    OS << "<jt#" << getIndex() << ">";
212    break;
213  case MachineOperand::MO_GlobalAddress:
214    OS << "<ga:" << ((Value*)getGlobal())->getName();
215    if (getOffset()) OS << "+" << getOffset();
216    OS << ">";
217    break;
218  case MachineOperand::MO_ExternalSymbol:
219    OS << "<es:" << getSymbolName();
220    if (getOffset()) OS << "+" << getOffset();
221    OS << ">";
222    break;
223  default:
224    assert(0 && "Unrecognized operand type");
225  }
226}
227
228//===----------------------------------------------------------------------===//
229// MachineInstr Implementation
230//===----------------------------------------------------------------------===//
231
232/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
233/// TID NULL and no operands.
234MachineInstr::MachineInstr()
235  : TID(0), NumImplicitOps(0), Parent(0) {
236  // Make sure that we get added to a machine basicblock
237  LeakDetector::addGarbageObject(this);
238}
239
240void MachineInstr::addImplicitDefUseOperands() {
241  if (TID->ImplicitDefs)
242    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
243      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
244  if (TID->ImplicitUses)
245    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
246      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
247}
248
249/// MachineInstr ctor - This constructor create a MachineInstr and add the
250/// implicit operands. It reserves space for number of operands specified by
251/// TargetInstrDescriptor or the numOperands if it is not zero. (for
252/// instructions with variable number of operands).
253MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
254  : TID(&tid), NumImplicitOps(0), Parent(0) {
255  if (!NoImp && TID->getImplicitDefs())
256    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
257      NumImplicitOps++;
258  if (!NoImp && TID->getImplicitUses())
259    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
260      NumImplicitOps++;
261  Operands.reserve(NumImplicitOps + TID->getNumOperands());
262  if (!NoImp)
263    addImplicitDefUseOperands();
264  // Make sure that we get added to a machine basicblock
265  LeakDetector::addGarbageObject(this);
266}
267
268/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
269/// MachineInstr is created and added to the end of the specified basic block.
270///
271MachineInstr::MachineInstr(MachineBasicBlock *MBB,
272                           const TargetInstrDescriptor &tid)
273  : TID(&tid), NumImplicitOps(0), Parent(0) {
274  assert(MBB && "Cannot use inserting ctor with null basic block!");
275  if (TID->ImplicitDefs)
276    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
277      NumImplicitOps++;
278  if (TID->ImplicitUses)
279    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
280      NumImplicitOps++;
281  Operands.reserve(NumImplicitOps + TID->getNumOperands());
282  addImplicitDefUseOperands();
283  // Make sure that we get added to a machine basicblock
284  LeakDetector::addGarbageObject(this);
285  MBB->push_back(this);  // Add instruction to end of basic block!
286}
287
288/// MachineInstr ctor - Copies MachineInstr arg exactly
289///
290MachineInstr::MachineInstr(const MachineInstr &MI) {
291  TID = MI.getDesc();
292  NumImplicitOps = MI.NumImplicitOps;
293  Operands.reserve(MI.getNumOperands());
294
295  // Add operands
296  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
297    Operands.push_back(MI.getOperand(i));
298    Operands.back().ParentMI = this;
299  }
300
301  // Set parent, next, and prev to null
302  Parent = 0;
303  Prev = 0;
304  Next = 0;
305}
306
307
308MachineInstr::~MachineInstr() {
309  LeakDetector::removeGarbageObject(this);
310#ifndef NDEBUG
311  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
312    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
313    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
314           "Reg operand def/use list corrupted");
315  }
316#endif
317}
318
319/// getOpcode - Returns the opcode of this MachineInstr.
320///
321int MachineInstr::getOpcode() const {
322  return TID->Opcode;
323}
324
325/// getRegInfo - If this instruction is embedded into a MachineFunction,
326/// return the MachineRegisterInfo object for the current function, otherwise
327/// return null.
328MachineRegisterInfo *MachineInstr::getRegInfo() {
329  if (MachineBasicBlock *MBB = getParent())
330    if (MachineFunction *MF = MBB->getParent())
331      return &MF->getRegInfo();
332  return 0;
333}
334
335/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
336/// this instruction from their respective use lists.  This requires that the
337/// operands already be on their use lists.
338void MachineInstr::RemoveRegOperandsFromUseLists() {
339  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
340    if (Operands[i].isReg())
341      Operands[i].RemoveRegOperandFromRegInfo();
342  }
343}
344
345/// AddRegOperandsToUseLists - Add all of the register operands in
346/// this instruction from their respective use lists.  This requires that the
347/// operands not be on their use lists yet.
348void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
349  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
350    if (Operands[i].isReg())
351      Operands[i].AddRegOperandToRegInfo(&RegInfo);
352  }
353}
354
355
356/// addOperand - Add the specified operand to the instruction.  If it is an
357/// implicit operand, it is added to the end of the operand list.  If it is
358/// an explicit operand it is added at the end of the explicit operand list
359/// (before the first implicit operand).
360void MachineInstr::addOperand(const MachineOperand &Op) {
361  bool isImpReg = Op.isReg() && Op.isImplicit();
362  assert((isImpReg || !OperandsComplete()) &&
363         "Trying to add an operand to a machine instr that is already done!");
364
365  // If we are adding the operand to the end of the list, our job is simpler.
366  // This is true most of the time, so this is a reasonable optimization.
367  if (isImpReg || NumImplicitOps == 0) {
368    // We can only do this optimization if we know that the operand list won't
369    // reallocate.
370    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
371      Operands.push_back(Op);
372
373      // Set the parent of the operand.
374      Operands.back().ParentMI = this;
375
376      // If the operand is a register, update the operand's use list.
377      if (Op.isReg())
378        Operands.back().AddRegOperandToRegInfo(getRegInfo());
379      return;
380    }
381  }
382
383  // Otherwise, we have to insert a real operand before any implicit ones.
384  unsigned OpNo = Operands.size()-NumImplicitOps;
385
386  MachineRegisterInfo *RegInfo = getRegInfo();
387
388  // If this instruction isn't embedded into a function, then we don't need to
389  // update any operand lists.
390  if (RegInfo == 0) {
391    // Simple insertion, no reginfo update needed for other register operands.
392    Operands.insert(Operands.begin()+OpNo, Op);
393    Operands[OpNo].ParentMI = this;
394
395    // Do explicitly set the reginfo for this operand though, to ensure the
396    // next/prev fields are properly nulled out.
397    if (Operands[OpNo].isReg())
398      Operands[OpNo].AddRegOperandToRegInfo(0);
399
400  } else if (Operands.size()+1 <= Operands.capacity()) {
401    // Otherwise, we have to remove register operands from their register use
402    // list, add the operand, then add the register operands back to their use
403    // list.  This also must handle the case when the operand list reallocates
404    // to somewhere else.
405
406    // If insertion of this operand won't cause reallocation of the operand
407    // list, just remove the implicit operands, add the operand, then re-add all
408    // the rest of the operands.
409    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
410      assert(Operands[i].isReg() && "Should only be an implicit reg!");
411      Operands[i].RemoveRegOperandFromRegInfo();
412    }
413
414    // Add the operand.  If it is a register, add it to the reg list.
415    Operands.insert(Operands.begin()+OpNo, Op);
416    Operands[OpNo].ParentMI = this;
417
418    if (Operands[OpNo].isReg())
419      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
420
421    // Re-add all the implicit ops.
422    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
423      assert(Operands[i].isReg() && "Should only be an implicit reg!");
424      Operands[i].AddRegOperandToRegInfo(RegInfo);
425    }
426  } else {
427    // Otherwise, we will be reallocating the operand list.  Remove all reg
428    // operands from their list, then readd them after the operand list is
429    // reallocated.
430    RemoveRegOperandsFromUseLists();
431
432    Operands.insert(Operands.begin()+OpNo, Op);
433    Operands[OpNo].ParentMI = this;
434
435    // Re-add all the operands.
436    AddRegOperandsToUseLists(*RegInfo);
437  }
438}
439
440/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
441/// fewer operand than it started with.
442///
443void MachineInstr::RemoveOperand(unsigned OpNo) {
444  assert(OpNo < Operands.size() && "Invalid operand number");
445
446  // Special case removing the last one.
447  if (OpNo == Operands.size()-1) {
448    // If needed, remove from the reg def/use list.
449    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
450      Operands.back().RemoveRegOperandFromRegInfo();
451
452    Operands.pop_back();
453    return;
454  }
455
456  // Otherwise, we are removing an interior operand.  If we have reginfo to
457  // update, remove all operands that will be shifted down from their reg lists,
458  // move everything down, then re-add them.
459  MachineRegisterInfo *RegInfo = getRegInfo();
460  if (RegInfo) {
461    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
462      if (Operands[i].isReg())
463        Operands[i].RemoveRegOperandFromRegInfo();
464    }
465  }
466
467  Operands.erase(Operands.begin()+OpNo);
468
469  if (RegInfo) {
470    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
471      if (Operands[i].isReg())
472        Operands[i].AddRegOperandToRegInfo(RegInfo);
473    }
474  }
475}
476
477
478/// removeFromParent - This method unlinks 'this' from the containing basic
479/// block, and returns it, but does not delete it.
480MachineInstr *MachineInstr::removeFromParent() {
481  assert(getParent() && "Not embedded in a basic block!");
482  getParent()->remove(this);
483  return this;
484}
485
486
487/// OperandComplete - Return true if it's illegal to add a new operand
488///
489bool MachineInstr::OperandsComplete() const {
490  unsigned short NumOperands = TID->getNumOperands();
491  if (TID->hasVariableOperands() == 0 &&
492      getNumOperands()-NumImplicitOps >= NumOperands)
493    return true;  // Broken: we have all the operands of this instruction!
494  return false;
495}
496
497/// getNumExplicitOperands - Returns the number of non-implicit operands.
498///
499unsigned MachineInstr::getNumExplicitOperands() const {
500  unsigned NumOperands = TID->getNumOperands();
501  if (TID->hasVariableOperands() == 0)
502    return NumOperands;
503
504  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
505    const MachineOperand &MO = getOperand(NumOperands);
506    if (!MO.isRegister() || !MO.isImplicit())
507      NumOperands++;
508  }
509  return NumOperands;
510}
511
512
513/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
514/// the specific register or -1 if it is not found. It further tightening
515/// the search criteria to a use that kills the register if isKill is true.
516int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const {
517  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
518    const MachineOperand &MO = getOperand(i);
519    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg)
520      if (!isKill || MO.isKill())
521        return i;
522  }
523  return -1;
524}
525
526/// findRegisterDefOperand() - Returns the MachineOperand that is a def of
527/// the specific register or NULL if it is not found.
528MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) {
529  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
530    MachineOperand &MO = getOperand(i);
531    if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg)
532      return &MO;
533  }
534  return NULL;
535}
536
537/// findFirstPredOperandIdx() - Find the index of the first operand in the
538/// operand list that is used to represent the predicate. It returns -1 if
539/// none is found.
540int MachineInstr::findFirstPredOperandIdx() const {
541  const TargetInstrDescriptor *TID = getDesc();
542  if (TID->isPredicable()) {
543    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
544      if (TID->OpInfo[i].isPredicate())
545        return i;
546  }
547
548  return -1;
549}
550
551/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
552/// to two addr elimination.
553bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
554  const TargetInstrDescriptor *TID = getDesc();
555  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
556    const MachineOperand &MO1 = getOperand(i);
557    if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
558      for (unsigned j = i+1; j < e; ++j) {
559        const MachineOperand &MO2 = getOperand(j);
560        if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
561            TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
562          return true;
563      }
564    }
565  }
566  return false;
567}
568
569/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
570///
571void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
572  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
573    const MachineOperand &MO = MI->getOperand(i);
574    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
575      continue;
576    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
577      MachineOperand &MOp = getOperand(j);
578      if (!MOp.isIdenticalTo(MO))
579        continue;
580      if (MO.isKill())
581        MOp.setIsKill();
582      else
583        MOp.setIsDead();
584      break;
585    }
586  }
587}
588
589/// copyPredicates - Copies predicate operand(s) from MI.
590void MachineInstr::copyPredicates(const MachineInstr *MI) {
591  const TargetInstrDescriptor *TID = MI->getDesc();
592  if (TID->isPredicable()) {
593    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
594      if (TID->OpInfo[i].isPredicate()) {
595        // Predicated operands must be last operands.
596        addOperand(MI->getOperand(i));
597      }
598    }
599  }
600}
601
602void MachineInstr::dump() const {
603  cerr << "  " << *this;
604}
605
606void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
607  // Specialize printing if op#0 is definition
608  unsigned StartOp = 0;
609  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
610    getOperand(0).print(OS, TM);
611    OS << " = ";
612    ++StartOp;   // Don't print this operand again!
613  }
614
615  OS << getDesc()->Name;
616
617  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
618    if (i != StartOp)
619      OS << ",";
620    OS << " ";
621    getOperand(i).print(OS, TM);
622  }
623
624  OS << "\n";
625}
626
627