MachineInstr.cpp revision 36ddaf294db6fbbbac5e79ca0e2d166ea36fe187
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/Value.h" 16#include "llvm/CodeGen/MachineFunction.h" 17#include "llvm/CodeGen/MachineRegisterInfo.h" 18#include "llvm/Target/TargetMachine.h" 19#include "llvm/Target/TargetInstrInfo.h" 20#include "llvm/Target/TargetInstrDesc.h" 21#include "llvm/Target/MRegisterInfo.h" 22#include "llvm/Support/LeakDetector.h" 23#include "llvm/Support/Streams.h" 24#include <ostream> 25using namespace llvm; 26 27//===----------------------------------------------------------------------===// 28// MachineOperand Implementation 29//===----------------------------------------------------------------------===// 30 31/// AddRegOperandToRegInfo - Add this register operand to the specified 32/// MachineRegisterInfo. If it is null, then the next/prev fields should be 33/// explicitly nulled out. 34void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) { 35 assert(isReg() && "Can only add reg operand to use lists"); 36 37 // If the reginfo pointer is null, just explicitly null out or next/prev 38 // pointers, to ensure they are not garbage. 39 if (RegInfo == 0) { 40 Contents.Reg.Prev = 0; 41 Contents.Reg.Next = 0; 42 return; 43 } 44 45 // Otherwise, add this operand to the head of the registers use/def list. 46 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg()); 47 48 // For SSA values, we prefer to keep the definition at the start of the list. 49 // we do this by skipping over the definition if it is at the head of the 50 // list. 51 if (*Head && (*Head)->isDef()) 52 Head = &(*Head)->Contents.Reg.Next; 53 54 Contents.Reg.Next = *Head; 55 if (Contents.Reg.Next) { 56 assert(getReg() == Contents.Reg.Next->getReg() && 57 "Different regs on the same list!"); 58 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; 59 } 60 61 Contents.Reg.Prev = Head; 62 *Head = this; 63} 64 65void MachineOperand::setReg(unsigned Reg) { 66 if (getReg() == Reg) return; // No change. 67 68 // Otherwise, we have to change the register. If this operand is embedded 69 // into a machine function, we need to update the old and new register's 70 // use/def lists. 71 if (MachineInstr *MI = getParent()) 72 if (MachineBasicBlock *MBB = MI->getParent()) 73 if (MachineFunction *MF = MBB->getParent()) { 74 RemoveRegOperandFromRegInfo(); 75 Contents.Reg.RegNo = Reg; 76 AddRegOperandToRegInfo(&MF->getRegInfo()); 77 return; 78 } 79 80 // Otherwise, just change the register, no problem. :) 81 Contents.Reg.RegNo = Reg; 82} 83 84/// ChangeToImmediate - Replace this operand with a new immediate operand of 85/// the specified value. If an operand is known to be an immediate already, 86/// the setImm method should be used. 87void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 88 // If this operand is currently a register operand, and if this is in a 89 // function, deregister the operand from the register's use/def list. 90 if (isReg() && getParent() && getParent()->getParent() && 91 getParent()->getParent()->getParent()) 92 RemoveRegOperandFromRegInfo(); 93 94 OpKind = MO_Immediate; 95 Contents.ImmVal = ImmVal; 96} 97 98/// ChangeToRegister - Replace this operand with a new register operand of 99/// the specified value. If an operand is known to be an register already, 100/// the setReg method should be used. 101void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 102 bool isKill, bool isDead) { 103 // If this operand is already a register operand, use setReg to update the 104 // register's use/def lists. 105 if (isReg()) { 106 setReg(Reg); 107 } else { 108 // Otherwise, change this to a register and set the reg#. 109 OpKind = MO_Register; 110 Contents.Reg.RegNo = Reg; 111 112 // If this operand is embedded in a function, add the operand to the 113 // register's use/def list. 114 if (MachineInstr *MI = getParent()) 115 if (MachineBasicBlock *MBB = MI->getParent()) 116 if (MachineFunction *MF = MBB->getParent()) 117 AddRegOperandToRegInfo(&MF->getRegInfo()); 118 } 119 120 IsDef = isDef; 121 IsImp = isImp; 122 IsKill = isKill; 123 IsDead = isDead; 124 SubReg = 0; 125} 126 127/// isIdenticalTo - Return true if this operand is identical to the specified 128/// operand. 129bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 130 if (getType() != Other.getType()) return false; 131 132 switch (getType()) { 133 default: assert(0 && "Unrecognized operand type"); 134 case MachineOperand::MO_Register: 135 return getReg() == Other.getReg() && isDef() == Other.isDef() && 136 getSubReg() == Other.getSubReg(); 137 case MachineOperand::MO_Immediate: 138 return getImm() == Other.getImm(); 139 case MachineOperand::MO_MachineBasicBlock: 140 return getMBB() == Other.getMBB(); 141 case MachineOperand::MO_FrameIndex: 142 return getIndex() == Other.getIndex(); 143 case MachineOperand::MO_ConstantPoolIndex: 144 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 145 case MachineOperand::MO_JumpTableIndex: 146 return getIndex() == Other.getIndex(); 147 case MachineOperand::MO_GlobalAddress: 148 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 149 case MachineOperand::MO_ExternalSymbol: 150 return !strcmp(getSymbolName(), Other.getSymbolName()) && 151 getOffset() == Other.getOffset(); 152 } 153} 154 155/// print - Print the specified machine operand. 156/// 157void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { 158 switch (getType()) { 159 case MachineOperand::MO_Register: 160 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) { 161 OS << "%reg" << getReg(); 162 } else { 163 // If the instruction is embedded into a basic block, we can find the 164 // target info for the instruction. 165 if (TM == 0) 166 if (const MachineInstr *MI = getParent()) 167 if (const MachineBasicBlock *MBB = MI->getParent()) 168 if (const MachineFunction *MF = MBB->getParent()) 169 TM = &MF->getTarget(); 170 171 if (TM) 172 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name; 173 else 174 OS << "%mreg" << getReg(); 175 } 176 177 if (isDef() || isKill() || isDead() || isImplicit()) { 178 OS << "<"; 179 bool NeedComma = false; 180 if (isImplicit()) { 181 OS << (isDef() ? "imp-def" : "imp-use"); 182 NeedComma = true; 183 } else if (isDef()) { 184 OS << "def"; 185 NeedComma = true; 186 } 187 if (isKill() || isDead()) { 188 if (NeedComma) OS << ","; 189 if (isKill()) OS << "kill"; 190 if (isDead()) OS << "dead"; 191 } 192 OS << ">"; 193 } 194 break; 195 case MachineOperand::MO_Immediate: 196 OS << getImm(); 197 break; 198 case MachineOperand::MO_MachineBasicBlock: 199 OS << "mbb<" 200 << ((Value*)getMBB()->getBasicBlock())->getName() 201 << "," << (void*)getMBB() << ">"; 202 break; 203 case MachineOperand::MO_FrameIndex: 204 OS << "<fi#" << getIndex() << ">"; 205 break; 206 case MachineOperand::MO_ConstantPoolIndex: 207 OS << "<cp#" << getIndex(); 208 if (getOffset()) OS << "+" << getOffset(); 209 OS << ">"; 210 break; 211 case MachineOperand::MO_JumpTableIndex: 212 OS << "<jt#" << getIndex() << ">"; 213 break; 214 case MachineOperand::MO_GlobalAddress: 215 OS << "<ga:" << ((Value*)getGlobal())->getName(); 216 if (getOffset()) OS << "+" << getOffset(); 217 OS << ">"; 218 break; 219 case MachineOperand::MO_ExternalSymbol: 220 OS << "<es:" << getSymbolName(); 221 if (getOffset()) OS << "+" << getOffset(); 222 OS << ">"; 223 break; 224 default: 225 assert(0 && "Unrecognized operand type"); 226 } 227} 228 229//===----------------------------------------------------------------------===// 230// MachineInstr Implementation 231//===----------------------------------------------------------------------===// 232 233/// MachineInstr ctor - This constructor creates a dummy MachineInstr with 234/// TID NULL and no operands. 235MachineInstr::MachineInstr() 236 : TID(0), NumImplicitOps(0), Parent(0) { 237 // Make sure that we get added to a machine basicblock 238 LeakDetector::addGarbageObject(this); 239} 240 241void MachineInstr::addImplicitDefUseOperands() { 242 if (TID->ImplicitDefs) 243 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) 244 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 245 if (TID->ImplicitUses) 246 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) 247 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 248} 249 250/// MachineInstr ctor - This constructor create a MachineInstr and add the 251/// implicit operands. It reserves space for number of operands specified by 252/// TargetInstrDesc or the numOperands if it is not zero. (for 253/// instructions with variable number of operands). 254MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) 255 : TID(&tid), NumImplicitOps(0), Parent(0) { 256 if (!NoImp && TID->getImplicitDefs()) 257 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 258 NumImplicitOps++; 259 if (!NoImp && TID->getImplicitUses()) 260 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 261 NumImplicitOps++; 262 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 263 if (!NoImp) 264 addImplicitDefUseOperands(); 265 // Make sure that we get added to a machine basicblock 266 LeakDetector::addGarbageObject(this); 267} 268 269/// MachineInstr ctor - Work exactly the same as the ctor above, except that the 270/// MachineInstr is created and added to the end of the specified basic block. 271/// 272MachineInstr::MachineInstr(MachineBasicBlock *MBB, 273 const TargetInstrDesc &tid) 274 : TID(&tid), NumImplicitOps(0), Parent(0) { 275 assert(MBB && "Cannot use inserting ctor with null basic block!"); 276 if (TID->ImplicitDefs) 277 for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 278 NumImplicitOps++; 279 if (TID->ImplicitUses) 280 for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses) 281 NumImplicitOps++; 282 Operands.reserve(NumImplicitOps + TID->getNumOperands()); 283 addImplicitDefUseOperands(); 284 // Make sure that we get added to a machine basicblock 285 LeakDetector::addGarbageObject(this); 286 MBB->push_back(this); // Add instruction to end of basic block! 287} 288 289/// MachineInstr ctor - Copies MachineInstr arg exactly 290/// 291MachineInstr::MachineInstr(const MachineInstr &MI) { 292 TID = &MI.getDesc(); 293 NumImplicitOps = MI.NumImplicitOps; 294 Operands.reserve(MI.getNumOperands()); 295 296 // Add operands 297 for (unsigned i = 0; i != MI.getNumOperands(); ++i) { 298 Operands.push_back(MI.getOperand(i)); 299 Operands.back().ParentMI = this; 300 } 301 302 // Set parent, next, and prev to null 303 Parent = 0; 304 Prev = 0; 305 Next = 0; 306} 307 308 309MachineInstr::~MachineInstr() { 310 LeakDetector::removeGarbageObject(this); 311#ifndef NDEBUG 312 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 313 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 314 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 315 "Reg operand def/use list corrupted"); 316 } 317#endif 318} 319 320/// getOpcode - Returns the opcode of this MachineInstr. 321/// 322int MachineInstr::getOpcode() const { 323 return TID->Opcode; 324} 325 326/// getRegInfo - If this instruction is embedded into a MachineFunction, 327/// return the MachineRegisterInfo object for the current function, otherwise 328/// return null. 329MachineRegisterInfo *MachineInstr::getRegInfo() { 330 if (MachineBasicBlock *MBB = getParent()) 331 if (MachineFunction *MF = MBB->getParent()) 332 return &MF->getRegInfo(); 333 return 0; 334} 335 336/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 337/// this instruction from their respective use lists. This requires that the 338/// operands already be on their use lists. 339void MachineInstr::RemoveRegOperandsFromUseLists() { 340 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 341 if (Operands[i].isReg()) 342 Operands[i].RemoveRegOperandFromRegInfo(); 343 } 344} 345 346/// AddRegOperandsToUseLists - Add all of the register operands in 347/// this instruction from their respective use lists. This requires that the 348/// operands not be on their use lists yet. 349void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) { 350 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 351 if (Operands[i].isReg()) 352 Operands[i].AddRegOperandToRegInfo(&RegInfo); 353 } 354} 355 356 357/// addOperand - Add the specified operand to the instruction. If it is an 358/// implicit operand, it is added to the end of the operand list. If it is 359/// an explicit operand it is added at the end of the explicit operand list 360/// (before the first implicit operand). 361void MachineInstr::addOperand(const MachineOperand &Op) { 362 bool isImpReg = Op.isReg() && Op.isImplicit(); 363 assert((isImpReg || !OperandsComplete()) && 364 "Trying to add an operand to a machine instr that is already done!"); 365 366 // If we are adding the operand to the end of the list, our job is simpler. 367 // This is true most of the time, so this is a reasonable optimization. 368 if (isImpReg || NumImplicitOps == 0) { 369 // We can only do this optimization if we know that the operand list won't 370 // reallocate. 371 if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) { 372 Operands.push_back(Op); 373 374 // Set the parent of the operand. 375 Operands.back().ParentMI = this; 376 377 // If the operand is a register, update the operand's use list. 378 if (Op.isReg()) 379 Operands.back().AddRegOperandToRegInfo(getRegInfo()); 380 return; 381 } 382 } 383 384 // Otherwise, we have to insert a real operand before any implicit ones. 385 unsigned OpNo = Operands.size()-NumImplicitOps; 386 387 MachineRegisterInfo *RegInfo = getRegInfo(); 388 389 // If this instruction isn't embedded into a function, then we don't need to 390 // update any operand lists. 391 if (RegInfo == 0) { 392 // Simple insertion, no reginfo update needed for other register operands. 393 Operands.insert(Operands.begin()+OpNo, Op); 394 Operands[OpNo].ParentMI = this; 395 396 // Do explicitly set the reginfo for this operand though, to ensure the 397 // next/prev fields are properly nulled out. 398 if (Operands[OpNo].isReg()) 399 Operands[OpNo].AddRegOperandToRegInfo(0); 400 401 } else if (Operands.size()+1 <= Operands.capacity()) { 402 // Otherwise, we have to remove register operands from their register use 403 // list, add the operand, then add the register operands back to their use 404 // list. This also must handle the case when the operand list reallocates 405 // to somewhere else. 406 407 // If insertion of this operand won't cause reallocation of the operand 408 // list, just remove the implicit operands, add the operand, then re-add all 409 // the rest of the operands. 410 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 411 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 412 Operands[i].RemoveRegOperandFromRegInfo(); 413 } 414 415 // Add the operand. If it is a register, add it to the reg list. 416 Operands.insert(Operands.begin()+OpNo, Op); 417 Operands[OpNo].ParentMI = this; 418 419 if (Operands[OpNo].isReg()) 420 Operands[OpNo].AddRegOperandToRegInfo(RegInfo); 421 422 // Re-add all the implicit ops. 423 for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) { 424 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 425 Operands[i].AddRegOperandToRegInfo(RegInfo); 426 } 427 } else { 428 // Otherwise, we will be reallocating the operand list. Remove all reg 429 // operands from their list, then readd them after the operand list is 430 // reallocated. 431 RemoveRegOperandsFromUseLists(); 432 433 Operands.insert(Operands.begin()+OpNo, Op); 434 Operands[OpNo].ParentMI = this; 435 436 // Re-add all the operands. 437 AddRegOperandsToUseLists(*RegInfo); 438 } 439} 440 441/// RemoveOperand - Erase an operand from an instruction, leaving it with one 442/// fewer operand than it started with. 443/// 444void MachineInstr::RemoveOperand(unsigned OpNo) { 445 assert(OpNo < Operands.size() && "Invalid operand number"); 446 447 // Special case removing the last one. 448 if (OpNo == Operands.size()-1) { 449 // If needed, remove from the reg def/use list. 450 if (Operands.back().isReg() && Operands.back().isOnRegUseList()) 451 Operands.back().RemoveRegOperandFromRegInfo(); 452 453 Operands.pop_back(); 454 return; 455 } 456 457 // Otherwise, we are removing an interior operand. If we have reginfo to 458 // update, remove all operands that will be shifted down from their reg lists, 459 // move everything down, then re-add them. 460 MachineRegisterInfo *RegInfo = getRegInfo(); 461 if (RegInfo) { 462 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 463 if (Operands[i].isReg()) 464 Operands[i].RemoveRegOperandFromRegInfo(); 465 } 466 } 467 468 Operands.erase(Operands.begin()+OpNo); 469 470 if (RegInfo) { 471 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 472 if (Operands[i].isReg()) 473 Operands[i].AddRegOperandToRegInfo(RegInfo); 474 } 475 } 476} 477 478 479/// removeFromParent - This method unlinks 'this' from the containing basic 480/// block, and returns it, but does not delete it. 481MachineInstr *MachineInstr::removeFromParent() { 482 assert(getParent() && "Not embedded in a basic block!"); 483 getParent()->remove(this); 484 return this; 485} 486 487 488/// OperandComplete - Return true if it's illegal to add a new operand 489/// 490bool MachineInstr::OperandsComplete() const { 491 unsigned short NumOperands = TID->getNumOperands(); 492 if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) 493 return true; // Broken: we have all the operands of this instruction! 494 return false; 495} 496 497/// getNumExplicitOperands - Returns the number of non-implicit operands. 498/// 499unsigned MachineInstr::getNumExplicitOperands() const { 500 unsigned NumOperands = TID->getNumOperands(); 501 if (!TID->isVariadic()) 502 return NumOperands; 503 504 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) { 505 const MachineOperand &MO = getOperand(NumOperands); 506 if (!MO.isRegister() || !MO.isImplicit()) 507 NumOperands++; 508 } 509 return NumOperands; 510} 511 512 513/// isDebugLabel - Returns true if the MachineInstr represents a debug label. 514/// 515bool MachineInstr::isDebugLabel() const { 516 return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0; 517} 518 519/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 520/// the specific register or -1 if it is not found. It further tightening 521/// the search criteria to a use that kills the register if isKill is true. 522int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill) const { 523 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 524 const MachineOperand &MO = getOperand(i); 525 if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg) 526 if (!isKill || MO.isKill()) 527 return i; 528 } 529 return -1; 530} 531 532/// findRegisterDefOperand() - Returns the MachineOperand that is a def of 533/// the specific register or NULL if it is not found. 534MachineOperand *MachineInstr::findRegisterDefOperand(unsigned Reg) { 535 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 536 MachineOperand &MO = getOperand(i); 537 if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) 538 return &MO; 539 } 540 return NULL; 541} 542 543/// findFirstPredOperandIdx() - Find the index of the first operand in the 544/// operand list that is used to represent the predicate. It returns -1 if 545/// none is found. 546int MachineInstr::findFirstPredOperandIdx() const { 547 const TargetInstrDesc &TID = getDesc(); 548 if (TID.isPredicable()) { 549 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 550 if (TID.OpInfo[i].isPredicate()) 551 return i; 552 } 553 554 return -1; 555} 556 557/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due 558/// to two addr elimination. 559bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const { 560 const TargetInstrDesc &TID = getDesc(); 561 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 562 const MachineOperand &MO1 = getOperand(i); 563 if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) { 564 for (unsigned j = i+1; j < e; ++j) { 565 const MachineOperand &MO2 = getOperand(j); 566 if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg && 567 TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i) 568 return true; 569 } 570 } 571 } 572 return false; 573} 574 575/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 576/// 577void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 578 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 579 const MachineOperand &MO = MI->getOperand(i); 580 if (!MO.isRegister() || (!MO.isKill() && !MO.isDead())) 581 continue; 582 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 583 MachineOperand &MOp = getOperand(j); 584 if (!MOp.isIdenticalTo(MO)) 585 continue; 586 if (MO.isKill()) 587 MOp.setIsKill(); 588 else 589 MOp.setIsDead(); 590 break; 591 } 592 } 593} 594 595/// copyPredicates - Copies predicate operand(s) from MI. 596void MachineInstr::copyPredicates(const MachineInstr *MI) { 597 const TargetInstrDesc &TID = MI->getDesc(); 598 if (TID.isPredicable()) { 599 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 600 if (TID.OpInfo[i].isPredicate()) { 601 // Predicated operands must be last operands. 602 addOperand(MI->getOperand(i)); 603 } 604 } 605 } 606} 607 608void MachineInstr::dump() const { 609 cerr << " " << *this; 610} 611 612void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 613 // Specialize printing if op#0 is definition 614 unsigned StartOp = 0; 615 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) { 616 getOperand(0).print(OS, TM); 617 OS << " = "; 618 ++StartOp; // Don't print this operand again! 619 } 620 621 OS << getDesc().getName(); 622 623 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 624 if (i != StartOp) 625 OS << ","; 626 OS << " "; 627 getOperand(i).print(OS, TM); 628 } 629 630 OS << "\n"; 631} 632 633bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 634 const MRegisterInfo *RegInfo, 635 bool AddIfNotFound) { 636 bool Found = false; 637 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 638 MachineOperand &MO = getOperand(i); 639 if (MO.isRegister() && MO.isUse()) { 640 unsigned Reg = MO.getReg(); 641 if (!Reg) 642 continue; 643 if (Reg == IncomingReg) { 644 MO.setIsKill(); 645 Found = true; 646 break; 647 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 648 MRegisterInfo::isPhysicalRegister(IncomingReg) && 649 RegInfo->isSuperRegister(IncomingReg, Reg) && 650 MO.isKill()) 651 // A super-register kill already exists. 652 Found = true; 653 } 654 } 655 656 // If not found, this means an alias of one of the operand is killed. Add a 657 // new implicit operand if required. 658 if (!Found && AddIfNotFound) { 659 addOperand(MachineOperand::CreateReg(IncomingReg, false/*IsDef*/, 660 true/*IsImp*/,true/*IsKill*/)); 661 return true; 662 } 663 return Found; 664} 665 666bool MachineInstr::addRegisterDead(unsigned IncomingReg, 667 const MRegisterInfo *RegInfo, 668 bool AddIfNotFound) { 669 bool Found = false; 670 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 671 MachineOperand &MO = getOperand(i); 672 if (MO.isRegister() && MO.isDef()) { 673 unsigned Reg = MO.getReg(); 674 if (!Reg) 675 continue; 676 if (Reg == IncomingReg) { 677 MO.setIsDead(); 678 Found = true; 679 break; 680 } else if (MRegisterInfo::isPhysicalRegister(Reg) && 681 MRegisterInfo::isPhysicalRegister(IncomingReg) && 682 RegInfo->isSuperRegister(IncomingReg, Reg) && 683 MO.isDead()) 684 // There exists a super-register that's marked dead. 685 return true; 686 } 687 } 688 689 // If not found, this means an alias of one of the operand is dead. Add a 690 // new implicit operand. 691 if (!Found && AddIfNotFound) { 692 addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/, 693 true/*IsImp*/,false/*IsKill*/, 694 true/*IsDead*/)); 695 return true; 696 } 697 return Found; 698} 699 700/// copyKillDeadInfo - copies killed/dead information from one instr to another 701void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI, 702 const MRegisterInfo *RegInfo) { 703 // If the instruction defines any virtual registers, update the VarInfo, 704 // kill and dead information for the instruction. 705 for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { 706 MachineOperand &MO = OldMI->getOperand(i); 707 if (MO.isRegister() && MO.getReg() && 708 MRegisterInfo::isVirtualRegister(MO.getReg())) { 709 unsigned Reg = MO.getReg(); 710 if (MO.isDef()) { 711 if (MO.isDead()) { 712 MO.setIsDead(false); 713 addRegisterDead(Reg, RegInfo); 714 } 715 } 716 if (MO.isKill()) { 717 MO.setIsKill(false); 718 addRegisterKilled(Reg, RegInfo); 719 } 720 } 721 } 722} 723