MachineInstr.cpp revision 40ab164d3ae6fddb279ae49ab2f9756b466c640a 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetInstrDesc.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Support/LeakDetector.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/Streams.h"
27#include "llvm/ADT/FoldingSet.h"
28#include <ostream>
29using namespace llvm;
30
31//===----------------------------------------------------------------------===//
32// MachineOperand Implementation
33//===----------------------------------------------------------------------===//
34
35/// AddRegOperandToRegInfo - Add this register operand to the specified
36/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
37/// explicitly nulled out.
38void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
39  assert(isReg() && "Can only add reg operand to use lists");
40
41  // If the reginfo pointer is null, just explicitly null out or next/prev
42  // pointers, to ensure they are not garbage.
43  if (RegInfo == 0) {
44    Contents.Reg.Prev = 0;
45    Contents.Reg.Next = 0;
46    return;
47  }
48
49  // Otherwise, add this operand to the head of the registers use/def list.
50  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
51
52  // For SSA values, we prefer to keep the definition at the start of the list.
53  // we do this by skipping over the definition if it is at the head of the
54  // list.
55  if (*Head && (*Head)->isDef())
56    Head = &(*Head)->Contents.Reg.Next;
57
58  Contents.Reg.Next = *Head;
59  if (Contents.Reg.Next) {
60    assert(getReg() == Contents.Reg.Next->getReg() &&
61           "Different regs on the same list!");
62    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
63  }
64
65  Contents.Reg.Prev = Head;
66  *Head = this;
67}
68
69void MachineOperand::setReg(unsigned Reg) {
70  if (getReg() == Reg) return; // No change.
71
72  // Otherwise, we have to change the register.  If this operand is embedded
73  // into a machine function, we need to update the old and new register's
74  // use/def lists.
75  if (MachineInstr *MI = getParent())
76    if (MachineBasicBlock *MBB = MI->getParent())
77      if (MachineFunction *MF = MBB->getParent()) {
78        RemoveRegOperandFromRegInfo();
79        Contents.Reg.RegNo = Reg;
80        AddRegOperandToRegInfo(&MF->getRegInfo());
81        return;
82      }
83
84  // Otherwise, just change the register, no problem.  :)
85  Contents.Reg.RegNo = Reg;
86}
87
88/// ChangeToImmediate - Replace this operand with a new immediate operand of
89/// the specified value.  If an operand is known to be an immediate already,
90/// the setImm method should be used.
91void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
92  // If this operand is currently a register operand, and if this is in a
93  // function, deregister the operand from the register's use/def list.
94  if (isReg() && getParent() && getParent()->getParent() &&
95      getParent()->getParent()->getParent())
96    RemoveRegOperandFromRegInfo();
97
98  OpKind = MO_Immediate;
99  Contents.ImmVal = ImmVal;
100}
101
102/// ChangeToRegister - Replace this operand with a new register operand of
103/// the specified value.  If an operand is known to be an register already,
104/// the setReg method should be used.
105void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
106                                      bool isKill, bool isDead) {
107  // If this operand is already a register operand, use setReg to update the
108  // register's use/def lists.
109  if (isReg()) {
110    setReg(Reg);
111  } else {
112    // Otherwise, change this to a register and set the reg#.
113    OpKind = MO_Register;
114    Contents.Reg.RegNo = Reg;
115
116    // If this operand is embedded in a function, add the operand to the
117    // register's use/def list.
118    if (MachineInstr *MI = getParent())
119      if (MachineBasicBlock *MBB = MI->getParent())
120        if (MachineFunction *MF = MBB->getParent())
121          AddRegOperandToRegInfo(&MF->getRegInfo());
122  }
123
124  IsDef = isDef;
125  IsImp = isImp;
126  IsKill = isKill;
127  IsDead = isDead;
128  SubReg = 0;
129}
130
131/// isIdenticalTo - Return true if this operand is identical to the specified
132/// operand.
133bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
134  if (getType() != Other.getType()) return false;
135
136  switch (getType()) {
137  default: assert(0 && "Unrecognized operand type");
138  case MachineOperand::MO_Register:
139    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
140           getSubReg() == Other.getSubReg();
141  case MachineOperand::MO_Immediate:
142    return getImm() == Other.getImm();
143  case MachineOperand::MO_FPImmediate:
144    return getFPImm() == Other.getFPImm();
145  case MachineOperand::MO_MachineBasicBlock:
146    return getMBB() == Other.getMBB();
147  case MachineOperand::MO_FrameIndex:
148    return getIndex() == Other.getIndex();
149  case MachineOperand::MO_ConstantPoolIndex:
150    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
151  case MachineOperand::MO_JumpTableIndex:
152    return getIndex() == Other.getIndex();
153  case MachineOperand::MO_GlobalAddress:
154    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
155  case MachineOperand::MO_ExternalSymbol:
156    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
157           getOffset() == Other.getOffset();
158  }
159}
160
161/// print - Print the specified machine operand.
162///
163void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
164  switch (getType()) {
165  case MachineOperand::MO_Register:
166    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
167      OS << "%reg" << getReg();
168    } else {
169      // If the instruction is embedded into a basic block, we can find the
170      // target info for the instruction.
171      if (TM == 0)
172        if (const MachineInstr *MI = getParent())
173          if (const MachineBasicBlock *MBB = MI->getParent())
174            if (const MachineFunction *MF = MBB->getParent())
175              TM = &MF->getTarget();
176
177      if (TM)
178        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
179      else
180        OS << "%mreg" << getReg();
181    }
182
183    if (isDef() || isKill() || isDead() || isImplicit()) {
184      OS << "<";
185      bool NeedComma = false;
186      if (isImplicit()) {
187        OS << (isDef() ? "imp-def" : "imp-use");
188        NeedComma = true;
189      } else if (isDef()) {
190        OS << "def";
191        NeedComma = true;
192      }
193      if (isKill() || isDead()) {
194        if (NeedComma) OS << ",";
195        if (isKill())  OS << "kill";
196        if (isDead())  OS << "dead";
197      }
198      OS << ">";
199    }
200    break;
201  case MachineOperand::MO_Immediate:
202    OS << getImm();
203    break;
204  case MachineOperand::MO_FPImmediate:
205    if (getFPImm()->getType() == Type::FloatTy) {
206      OS << getFPImm()->getValueAPF().convertToFloat();
207    } else {
208      OS << getFPImm()->getValueAPF().convertToDouble();
209    }
210    break;
211  case MachineOperand::MO_MachineBasicBlock:
212    OS << "mbb<"
213       << ((Value*)getMBB()->getBasicBlock())->getName()
214       << "," << (void*)getMBB() << ">";
215    break;
216  case MachineOperand::MO_FrameIndex:
217    OS << "<fi#" << getIndex() << ">";
218    break;
219  case MachineOperand::MO_ConstantPoolIndex:
220    OS << "<cp#" << getIndex();
221    if (getOffset()) OS << "+" << getOffset();
222    OS << ">";
223    break;
224  case MachineOperand::MO_JumpTableIndex:
225    OS << "<jt#" << getIndex() << ">";
226    break;
227  case MachineOperand::MO_GlobalAddress:
228    OS << "<ga:" << ((Value*)getGlobal())->getName();
229    if (getOffset()) OS << "+" << getOffset();
230    OS << ">";
231    break;
232  case MachineOperand::MO_ExternalSymbol:
233    OS << "<es:" << getSymbolName();
234    if (getOffset()) OS << "+" << getOffset();
235    OS << ">";
236    break;
237  default:
238    assert(0 && "Unrecognized operand type");
239  }
240}
241
242//===----------------------------------------------------------------------===//
243// MachineMemOperand Implementation
244//===----------------------------------------------------------------------===//
245
246MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
247                                     int64_t o, uint64_t s, unsigned int a)
248  : Offset(o), Size(s), V(v),
249    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
250  assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
251  assert((isLoad() || isStore()) && "Not a load/store!");
252}
253
254/// Profile - Gather unique data for the object.
255///
256void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
257  ID.AddInteger(Offset);
258  ID.AddInteger(Size);
259  ID.AddPointer(V);
260  ID.AddInteger(Flags);
261}
262
263//===----------------------------------------------------------------------===//
264// MachineInstr Implementation
265//===----------------------------------------------------------------------===//
266
267/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
268/// TID NULL and no operands.
269MachineInstr::MachineInstr()
270  : TID(0), NumImplicitOps(0), Parent(0) {
271  // Make sure that we get added to a machine basicblock
272  LeakDetector::addGarbageObject(this);
273}
274
275void MachineInstr::addImplicitDefUseOperands() {
276  if (TID->ImplicitDefs)
277    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
278      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
279  if (TID->ImplicitUses)
280    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
281      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
282}
283
284/// MachineInstr ctor - This constructor create a MachineInstr and add the
285/// implicit operands. It reserves space for number of operands specified by
286/// TargetInstrDesc or the numOperands if it is not zero. (for
287/// instructions with variable number of operands).
288MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
289  : TID(&tid), NumImplicitOps(0), Parent(0) {
290  if (!NoImp && TID->getImplicitDefs())
291    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
292      NumImplicitOps++;
293  if (!NoImp && TID->getImplicitUses())
294    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
295      NumImplicitOps++;
296  Operands.reserve(NumImplicitOps + TID->getNumOperands());
297  if (!NoImp)
298    addImplicitDefUseOperands();
299  // Make sure that we get added to a machine basicblock
300  LeakDetector::addGarbageObject(this);
301}
302
303/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
304/// MachineInstr is created and added to the end of the specified basic block.
305///
306MachineInstr::MachineInstr(MachineBasicBlock *MBB,
307                           const TargetInstrDesc &tid)
308  : TID(&tid), NumImplicitOps(0), Parent(0) {
309  assert(MBB && "Cannot use inserting ctor with null basic block!");
310  if (TID->ImplicitDefs)
311    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
312      NumImplicitOps++;
313  if (TID->ImplicitUses)
314    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
315      NumImplicitOps++;
316  Operands.reserve(NumImplicitOps + TID->getNumOperands());
317  addImplicitDefUseOperands();
318  // Make sure that we get added to a machine basicblock
319  LeakDetector::addGarbageObject(this);
320  MBB->push_back(this);  // Add instruction to end of basic block!
321}
322
323/// MachineInstr ctor - Copies MachineInstr arg exactly
324///
325MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
326  : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
327  Operands.reserve(MI.getNumOperands());
328
329  // Add operands
330  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
331    addOperand(MI.getOperand(i));
332  NumImplicitOps = MI.NumImplicitOps;
333
334  // Add memory operands.
335  for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
336       j = MI.memoperands_end(); i != j; ++i)
337    addMemOperand(MF, *i);
338
339  // Set parent to null.
340  Parent = 0;
341
342  LeakDetector::addGarbageObject(this);
343}
344
345MachineInstr::~MachineInstr() {
346  LeakDetector::removeGarbageObject(this);
347  assert(MemOperands.empty() &&
348         "MachineInstr being deleted with live memoperands!");
349#ifndef NDEBUG
350  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
351    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
352    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
353           "Reg operand def/use list corrupted");
354  }
355#endif
356}
357
358/// getRegInfo - If this instruction is embedded into a MachineFunction,
359/// return the MachineRegisterInfo object for the current function, otherwise
360/// return null.
361MachineRegisterInfo *MachineInstr::getRegInfo() {
362  if (MachineBasicBlock *MBB = getParent())
363    return &MBB->getParent()->getRegInfo();
364  return 0;
365}
366
367/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
368/// this instruction from their respective use lists.  This requires that the
369/// operands already be on their use lists.
370void MachineInstr::RemoveRegOperandsFromUseLists() {
371  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
372    if (Operands[i].isReg())
373      Operands[i].RemoveRegOperandFromRegInfo();
374  }
375}
376
377/// AddRegOperandsToUseLists - Add all of the register operands in
378/// this instruction from their respective use lists.  This requires that the
379/// operands not be on their use lists yet.
380void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
381  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
382    if (Operands[i].isReg())
383      Operands[i].AddRegOperandToRegInfo(&RegInfo);
384  }
385}
386
387
388/// addOperand - Add the specified operand to the instruction.  If it is an
389/// implicit operand, it is added to the end of the operand list.  If it is
390/// an explicit operand it is added at the end of the explicit operand list
391/// (before the first implicit operand).
392void MachineInstr::addOperand(const MachineOperand &Op) {
393  bool isImpReg = Op.isReg() && Op.isImplicit();
394  assert((isImpReg || !OperandsComplete()) &&
395         "Trying to add an operand to a machine instr that is already done!");
396
397  // If we are adding the operand to the end of the list, our job is simpler.
398  // This is true most of the time, so this is a reasonable optimization.
399  if (isImpReg || NumImplicitOps == 0) {
400    // We can only do this optimization if we know that the operand list won't
401    // reallocate.
402    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
403      Operands.push_back(Op);
404
405      // Set the parent of the operand.
406      Operands.back().ParentMI = this;
407
408      // If the operand is a register, update the operand's use list.
409      if (Op.isReg())
410        Operands.back().AddRegOperandToRegInfo(getRegInfo());
411      return;
412    }
413  }
414
415  // Otherwise, we have to insert a real operand before any implicit ones.
416  unsigned OpNo = Operands.size()-NumImplicitOps;
417
418  MachineRegisterInfo *RegInfo = getRegInfo();
419
420  // If this instruction isn't embedded into a function, then we don't need to
421  // update any operand lists.
422  if (RegInfo == 0) {
423    // Simple insertion, no reginfo update needed for other register operands.
424    Operands.insert(Operands.begin()+OpNo, Op);
425    Operands[OpNo].ParentMI = this;
426
427    // Do explicitly set the reginfo for this operand though, to ensure the
428    // next/prev fields are properly nulled out.
429    if (Operands[OpNo].isReg())
430      Operands[OpNo].AddRegOperandToRegInfo(0);
431
432  } else if (Operands.size()+1 <= Operands.capacity()) {
433    // Otherwise, we have to remove register operands from their register use
434    // list, add the operand, then add the register operands back to their use
435    // list.  This also must handle the case when the operand list reallocates
436    // to somewhere else.
437
438    // If insertion of this operand won't cause reallocation of the operand
439    // list, just remove the implicit operands, add the operand, then re-add all
440    // the rest of the operands.
441    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
442      assert(Operands[i].isReg() && "Should only be an implicit reg!");
443      Operands[i].RemoveRegOperandFromRegInfo();
444    }
445
446    // Add the operand.  If it is a register, add it to the reg list.
447    Operands.insert(Operands.begin()+OpNo, Op);
448    Operands[OpNo].ParentMI = this;
449
450    if (Operands[OpNo].isReg())
451      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
452
453    // Re-add all the implicit ops.
454    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
455      assert(Operands[i].isReg() && "Should only be an implicit reg!");
456      Operands[i].AddRegOperandToRegInfo(RegInfo);
457    }
458  } else {
459    // Otherwise, we will be reallocating the operand list.  Remove all reg
460    // operands from their list, then readd them after the operand list is
461    // reallocated.
462    RemoveRegOperandsFromUseLists();
463
464    Operands.insert(Operands.begin()+OpNo, Op);
465    Operands[OpNo].ParentMI = this;
466
467    // Re-add all the operands.
468    AddRegOperandsToUseLists(*RegInfo);
469  }
470}
471
472/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
473/// fewer operand than it started with.
474///
475void MachineInstr::RemoveOperand(unsigned OpNo) {
476  assert(OpNo < Operands.size() && "Invalid operand number");
477
478  // Special case removing the last one.
479  if (OpNo == Operands.size()-1) {
480    // If needed, remove from the reg def/use list.
481    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
482      Operands.back().RemoveRegOperandFromRegInfo();
483
484    Operands.pop_back();
485    return;
486  }
487
488  // Otherwise, we are removing an interior operand.  If we have reginfo to
489  // update, remove all operands that will be shifted down from their reg lists,
490  // move everything down, then re-add them.
491  MachineRegisterInfo *RegInfo = getRegInfo();
492  if (RegInfo) {
493    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
494      if (Operands[i].isReg())
495        Operands[i].RemoveRegOperandFromRegInfo();
496    }
497  }
498
499  Operands.erase(Operands.begin()+OpNo);
500
501  if (RegInfo) {
502    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
503      if (Operands[i].isReg())
504        Operands[i].AddRegOperandToRegInfo(RegInfo);
505    }
506  }
507}
508
509/// addMemOperand - Add a MachineMemOperand to the machine instruction,
510/// referencing arbitrary storage.
511void MachineInstr::addMemOperand(MachineFunction &MF,
512                                 const MachineMemOperand &MO) {
513  MemOperands.push_back(MO);
514}
515
516/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
517void MachineInstr::clearMemOperands(MachineFunction &MF) {
518  MemOperands.clear();
519}
520
521
522/// removeFromParent - This method unlinks 'this' from the containing basic
523/// block, and returns it, but does not delete it.
524MachineInstr *MachineInstr::removeFromParent() {
525  assert(getParent() && "Not embedded in a basic block!");
526  getParent()->remove(this);
527  return this;
528}
529
530
531/// eraseFromParent - This method unlinks 'this' from the containing basic
532/// block, and deletes it.
533void MachineInstr::eraseFromParent() {
534  assert(getParent() && "Not embedded in a basic block!");
535  getParent()->erase(this);
536}
537
538
539/// OperandComplete - Return true if it's illegal to add a new operand
540///
541bool MachineInstr::OperandsComplete() const {
542  unsigned short NumOperands = TID->getNumOperands();
543  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
544    return true;  // Broken: we have all the operands of this instruction!
545  return false;
546}
547
548/// getNumExplicitOperands - Returns the number of non-implicit operands.
549///
550unsigned MachineInstr::getNumExplicitOperands() const {
551  unsigned NumOperands = TID->getNumOperands();
552  if (!TID->isVariadic())
553    return NumOperands;
554
555  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
556    const MachineOperand &MO = getOperand(NumOperands);
557    if (!MO.isRegister() || !MO.isImplicit())
558      NumOperands++;
559  }
560  return NumOperands;
561}
562
563
564/// isLabel - Returns true if the MachineInstr represents a label.
565///
566bool MachineInstr::isLabel() const {
567  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
568         getOpcode() == TargetInstrInfo::EH_LABEL ||
569         getOpcode() == TargetInstrInfo::GC_LABEL;
570}
571
572/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
573///
574bool MachineInstr::isDebugLabel() const {
575  return getOpcode() == TargetInstrInfo::DBG_LABEL;
576}
577
578/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
579/// the specific register or -1 if it is not found. It further tightening
580/// the search criteria to a use that kills the register if isKill is true.
581int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
582                                          const TargetRegisterInfo *TRI) const {
583  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
584    const MachineOperand &MO = getOperand(i);
585    if (!MO.isRegister() || !MO.isUse())
586      continue;
587    unsigned MOReg = MO.getReg();
588    if (!MOReg)
589      continue;
590    if (MOReg == Reg ||
591        (TRI &&
592         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
593         TargetRegisterInfo::isPhysicalRegister(Reg) &&
594         TRI->isSubRegister(MOReg, Reg)))
595      if (!isKill || MO.isKill())
596        return i;
597  }
598  return -1;
599}
600
601/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
602/// the specified register or -1 if it is not found. If isDead is true, defs
603/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
604/// also checks if there is a def of a super-register.
605int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
606                                          const TargetRegisterInfo *TRI) const {
607  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
608    const MachineOperand &MO = getOperand(i);
609    if (!MO.isRegister() || !MO.isDef())
610      continue;
611    unsigned MOReg = MO.getReg();
612    if (MOReg == Reg ||
613        (TRI &&
614         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
615         TargetRegisterInfo::isPhysicalRegister(Reg) &&
616         TRI->isSubRegister(MOReg, Reg)))
617      if (!isDead || MO.isDead())
618        return i;
619  }
620  return -1;
621}
622
623/// findFirstPredOperandIdx() - Find the index of the first operand in the
624/// operand list that is used to represent the predicate. It returns -1 if
625/// none is found.
626int MachineInstr::findFirstPredOperandIdx() const {
627  const TargetInstrDesc &TID = getDesc();
628  if (TID.isPredicable()) {
629    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
630      if (TID.OpInfo[i].isPredicate())
631        return i;
632  }
633
634  return -1;
635}
636
637/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
638/// check if the register def is a re-definition due to two addr elimination.
639bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
640  const TargetInstrDesc &TID = getDesc();
641  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
642    const MachineOperand &MO = getOperand(i);
643    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
644        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
645      return true;
646  }
647  return false;
648}
649
650/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
651///
652void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
653  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
654    const MachineOperand &MO = MI->getOperand(i);
655    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
656      continue;
657    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
658      MachineOperand &MOp = getOperand(j);
659      if (!MOp.isIdenticalTo(MO))
660        continue;
661      if (MO.isKill())
662        MOp.setIsKill();
663      else
664        MOp.setIsDead();
665      break;
666    }
667  }
668}
669
670/// copyPredicates - Copies predicate operand(s) from MI.
671void MachineInstr::copyPredicates(const MachineInstr *MI) {
672  const TargetInstrDesc &TID = MI->getDesc();
673  if (!TID.isPredicable())
674    return;
675  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
676    if (TID.OpInfo[i].isPredicate()) {
677      // Predicated operands must be last operands.
678      addOperand(MI->getOperand(i));
679    }
680  }
681}
682
683/// isSafeToMove - Return true if it is safe to move this instruction. If
684/// SawStore is set to true, it means that there is a store (or call) between
685/// the instruction's location and its intended destination.
686bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
687  // Ignore stuff that we obviously can't move.
688  if (TID->mayStore() || TID->isCall()) {
689    SawStore = true;
690    return false;
691  }
692  if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
693    return false;
694
695  // See if this instruction does a load.  If so, we have to guarantee that the
696  // loaded value doesn't change between the load and the its intended
697  // destination. The check for isInvariantLoad gives the targe the chance to
698  // classify the load as always returning a constant, e.g. a constant pool
699  // load.
700  if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
701    // Otherwise, this is a real load.  If there is a store between the load and
702    // end of block, we can't sink the load.
703    //
704    // FIXME: we can't do this transformation until we know that the load is
705    // not volatile, and machineinstrs don't keep this info. :(
706    //
707    //if (SawStore)
708    return false;
709  }
710  return true;
711}
712
713void MachineInstr::dump() const {
714  cerr << "  " << *this;
715}
716
717void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
718  // Specialize printing if op#0 is definition
719  unsigned StartOp = 0;
720  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
721    getOperand(0).print(OS, TM);
722    OS << " = ";
723    ++StartOp;   // Don't print this operand again!
724  }
725
726  OS << getDesc().getName();
727
728  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
729    if (i != StartOp)
730      OS << ",";
731    OS << " ";
732    getOperand(i).print(OS, TM);
733  }
734
735  if (!memoperands_empty()) {
736    OS << ", Mem:";
737    for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
738         e = memoperands_end(); i != e; ++i) {
739      const MachineMemOperand &MRO = *i;
740      const Value *V = MRO.getValue();
741
742      assert((MRO.isLoad() || MRO.isStore()) &&
743             "SV has to be a load, store or both.");
744
745      if (MRO.isVolatile())
746        OS << "Volatile ";
747
748      if (MRO.isLoad())
749        OS << "LD";
750      if (MRO.isStore())
751        OS << "ST";
752
753      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
754
755      if (!V)
756        OS << "<unknown>";
757      else if (!V->getName().empty())
758        OS << V->getName();
759      else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
760        OS << *PSV;
761      else
762        OS << V;
763
764      OS << " + " << MRO.getOffset() << "]";
765    }
766  }
767
768  OS << "\n";
769}
770
771bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
772                                     const TargetRegisterInfo *RegInfo,
773                                     bool AddIfNotFound) {
774  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
775  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
776  SmallVector<unsigned,4> DeadOps;
777  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
778    MachineOperand &MO = getOperand(i);
779    if (!MO.isRegister() || !MO.isUse())
780      continue;
781    unsigned Reg = MO.getReg();
782    if (!Reg)
783      continue;
784
785    if (Reg == IncomingReg) {
786      MO.setIsKill();
787      return true;
788    }
789    if (hasAliases && MO.isKill() &&
790        TargetRegisterInfo::isPhysicalRegister(Reg)) {
791      // A super-register kill already exists.
792      if (RegInfo->isSuperRegister(IncomingReg, Reg))
793        return true;
794      if (RegInfo->isSubRegister(IncomingReg, Reg))
795        DeadOps.push_back(i);
796    }
797  }
798
799  // Trim unneeded kill operands.
800  while (!DeadOps.empty()) {
801    unsigned OpIdx = DeadOps.back();
802    if (getOperand(OpIdx).isImplicit())
803      RemoveOperand(OpIdx);
804    else
805      getOperand(OpIdx).setIsKill(false);
806    DeadOps.pop_back();
807  }
808
809  // If not found, this means an alias of one of the operands is killed. Add a
810  // new implicit operand if required.
811  if (AddIfNotFound) {
812    addOperand(MachineOperand::CreateReg(IncomingReg,
813                                         false /*IsDef*/,
814                                         true  /*IsImp*/,
815                                         true  /*IsKill*/));
816    return true;
817  }
818  return false;
819}
820
821bool MachineInstr::addRegisterDead(unsigned IncomingReg,
822                                   const TargetRegisterInfo *RegInfo,
823                                   bool AddIfNotFound) {
824  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
825  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
826  SmallVector<unsigned,4> DeadOps;
827  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
828    MachineOperand &MO = getOperand(i);
829    if (!MO.isRegister() || !MO.isDef())
830      continue;
831    unsigned Reg = MO.getReg();
832    if (Reg == IncomingReg) {
833      MO.setIsDead();
834      return true;
835    }
836    if (hasAliases && MO.isDead() &&
837        TargetRegisterInfo::isPhysicalRegister(Reg)) {
838      // There exists a super-register that's marked dead.
839      if (RegInfo->isSuperRegister(IncomingReg, Reg))
840        return true;
841      if (RegInfo->getSubRegisters(IncomingReg) &&
842          RegInfo->getSuperRegisters(Reg) &&
843          RegInfo->isSubRegister(IncomingReg, Reg))
844        DeadOps.push_back(i);
845    }
846  }
847
848  // Trim unneeded dead operands.
849  while (!DeadOps.empty()) {
850    unsigned OpIdx = DeadOps.back();
851    if (getOperand(OpIdx).isImplicit())
852      RemoveOperand(OpIdx);
853    else
854      getOperand(OpIdx).setIsDead(false);
855    DeadOps.pop_back();
856  }
857
858  // If not found, this means an alias of one of the operand is dead. Add a
859  // new implicit operand.
860  if (AddIfNotFound) {
861    addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
862                                         true/*IsImp*/,false/*IsKill*/,
863                                         true/*IsDead*/));
864    return true;
865  }
866  return false;
867}
868