MachineInstr.cpp revision 48d7c069c76882475c23de153bda9483cd3c9bb4 
1//===-- MachineInstr.cpp --------------------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12// FIXME: Now that MachineInstrs have parent pointers, they should always
13// print themselves using their MachineFunction's TargetMachine.
14//
15//===----------------------------------------------------------------------===//
16
17#include "llvm/CodeGen/MachineInstr.h"
18#include "llvm/CodeGen/MachineFunction.h"
19#include "llvm/Value.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/MRegisterInfo.h"
23#include "llvm/Support/LeakDetector.h"
24#include <iostream>
25
26using namespace llvm;
27
28// Global variable holding an array of descriptors for machine instructions.
29// The actual object needs to be created separately for each target machine.
30// This variable is initialized and reset by class TargetInstrInfo.
31//
32// FIXME: This should be a property of the target so that more than one target
33// at a time can be active...
34//
35namespace llvm {
36  extern const TargetInstrDescriptor *TargetInstrDescriptors;
37}
38
39// Constructor for instructions with variable #operands
40MachineInstr::MachineInstr(short opcode, unsigned numOperands)
41  : Opcode(opcode),
42    numImplicitRefs(0),
43    operands(numOperands, MachineOperand()),
44    parent(0) {
45  // Make sure that we get added to a machine basicblock
46  LeakDetector::addGarbageObject(this);
47}
48
49/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
50/// not a resize for them.  It is expected that if you use this that you call
51/// add* methods below to fill up the operands, instead of the Set methods.
52/// Eventually, the "resizing" ctors will be phased out.
53///
54MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
55  : Opcode(opcode), numImplicitRefs(0), parent(0) {
56  operands.reserve(numOperands);
57  // Make sure that we get added to a machine basicblock
58  LeakDetector::addGarbageObject(this);
59}
60
61/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
62/// MachineInstr is created and added to the end of the specified basic block.
63///
64MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
65                           unsigned numOperands)
66  : Opcode(opcode), numImplicitRefs(0), parent(0) {
67  assert(MBB && "Cannot use inserting ctor with null basic block!");
68  operands.reserve(numOperands);
69  // Make sure that we get added to a machine basicblock
70  LeakDetector::addGarbageObject(this);
71  MBB->push_back(this);  // Add instruction to end of basic block!
72}
73
74/// MachineInstr ctor - Copies MachineInstr arg exactly
75///
76MachineInstr::MachineInstr(const MachineInstr &MI) {
77  Opcode = MI.getOpcode();
78  numImplicitRefs = MI.getNumImplicitRefs();
79  operands.reserve(MI.getNumOperands());
80
81  // Add operands
82  for (unsigned i = 0; i < MI.getNumOperands(); ++i)
83    operands.push_back(MachineOperand(MI.getOperand(i)));
84
85  // Set parent, next, and prev to null
86  parent = 0;
87  prev = 0;
88  next = 0;
89}
90
91
92MachineInstr::~MachineInstr() {
93  LeakDetector::removeGarbageObject(this);
94}
95
96/// clone - Create a copy of 'this' instruction that is identical in all ways
97/// except the following: the new instruction has no parent and it has no name
98///
99MachineInstr* MachineInstr::clone() const {
100  return new MachineInstr(*this);
101}
102
103/// removeFromParent - This method unlinks 'this' from the containing basic
104/// block, and returns it, but does not delete it.
105MachineInstr *MachineInstr::removeFromParent() {
106  assert(getParent() && "Not embedded in a basic block!");
107  getParent()->remove(this);
108  return this;
109}
110
111
112/// OperandComplete - Return true if it's illegal to add a new operand
113///
114bool MachineInstr::OperandsComplete() const {
115  int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
116  if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
117    return true;  // Broken: we have all the operands of this instruction!
118  return false;
119}
120
121/// replace - Support for replacing opcode and operands of a MachineInstr in
122/// place. This only resets the size of the operand vector and initializes it.
123/// The new operands must be set explicitly later.
124///
125void MachineInstr::replace(short opcode, unsigned numOperands) {
126  assert(getNumImplicitRefs() == 0 &&
127         "This is probably broken because implicit refs are going to be lost.");
128  Opcode = opcode;
129  operands.clear();
130  operands.resize(numOperands, MachineOperand());
131}
132
133void MachineInstr::SetMachineOperandVal(unsigned i,
134                                        MachineOperand::MachineOperandType opTy,
135                                        Value* V) {
136  assert(i < operands.size());          // may be explicit or implicit op
137  operands[i].opType = opTy;
138  operands[i].contents.value = V;
139  operands[i].extra.regNum = -1;
140}
141
142void
143MachineInstr::SetMachineOperandConst(unsigned i,
144                                     MachineOperand::MachineOperandType opTy,
145                                     int intValue) {
146  assert(i < getNumOperands());          // must be explicit op
147  assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
148         "immed. constant cannot be defined");
149
150  operands[i].opType = opTy;
151  operands[i].contents.value = NULL;
152  operands[i].contents.immedVal = intValue;
153  operands[i].extra.regNum = -1;
154  operands[i].flags = 0;
155}
156
157void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
158  assert(i < getNumOperands());          // must be explicit op
159
160  operands[i].opType = MachineOperand::MO_MachineRegister;
161  operands[i].contents.value = NULL;
162  operands[i].extra.regNum = regNum;
163}
164
165// Used only by the SPARC back-end.
166void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
167  assert(i < getNumOperands());          // must be explicit op
168  operands[i].setRegForValue(regNum);
169}
170
171// Used only by the SPARC back-end.
172void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
173  getImplicitOp(i).setRegForValue(regNum);
174}
175
176/// substituteValue - Substitute all occurrences of Value* oldVal with newVal
177/// in all operands and all implicit refs. If defsOnly == true, substitute defs
178/// only.
179///
180/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
181/// or make it a static function in that file.
182///
183unsigned
184MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
185                              bool defsOnly, bool notDefsAndUses,
186                              bool& someArgsWereIgnored)
187{
188  assert((!defsOnly || !notDefsAndUses) &&
189         "notDefsAndUses is irrelevant if defsOnly == true.");
190
191  unsigned numSubst = 0;
192
193  // Substitute operands
194  for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
195    if (*O == oldVal)
196      if (!defsOnly ||
197          notDefsAndUses && (O.isDef() && !O.isUse()) ||
198          !notDefsAndUses && O.isDef())
199      {
200        O.getMachineOperand().contents.value = newVal;
201        ++numSubst;
202      } else
203        someArgsWereIgnored = true;
204
205  // Substitute implicit refs
206  for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i)
207    if (getImplicitRef(i) == oldVal) {
208      MachineOperand Op = getImplicitOp(i);
209      if (!defsOnly ||
210          notDefsAndUses && (Op.isDef() && !Op.isUse()) ||
211          !notDefsAndUses && Op.isDef())
212      {
213        Op.contents.value = newVal;
214        ++numSubst;
215      } else
216        someArgsWereIgnored = true;
217    }
218  return numSubst;
219}
220
221void MachineInstr::dump() const {
222  std::cerr << "  " << *this;
223}
224
225static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
226  os << "(val ";
227  os << (void*) val;                // print address always
228  if (val && val->hasName())
229    os << " " << val->getName();    // print name also, if available
230  os << ")";
231  return os;
232}
233
234static inline void OutputReg(std::ostream &os, unsigned RegNo,
235                             const MRegisterInfo *MRI = 0) {
236  if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
237    if (MRI)
238      os << "%" << MRI->get(RegNo).Name;
239    else
240      os << "%mreg(" << RegNo << ")";
241  } else
242    os << "%reg" << RegNo;
243}
244
245static void print(const MachineOperand &MO, std::ostream &OS,
246                  const TargetMachine *TM) {
247  const MRegisterInfo *MRI = 0;
248
249  if (TM) MRI = TM->getRegisterInfo();
250
251  bool CloseParen = true;
252  if (MO.isHiBits32())
253    OS << "%lm(";
254  else if (MO.isLoBits32())
255    OS << "%lo(";
256  else if (MO.isHiBits64())
257    OS << "%hh(";
258  else if (MO.isLoBits64())
259    OS << "%hm(";
260  else
261    CloseParen = false;
262
263  switch (MO.getType()) {
264  case MachineOperand::MO_VirtualRegister:
265    if (MO.getVRegValue()) {
266      OS << "%reg";
267      OutputValue(OS, MO.getVRegValue());
268      if (MO.hasAllocatedReg())
269        OS << "==";
270    }
271    if (MO.hasAllocatedReg())
272      OutputReg(OS, MO.getReg(), MRI);
273    break;
274  case MachineOperand::MO_CCRegister:
275    OS << "%ccreg";
276    OutputValue(OS, MO.getVRegValue());
277    if (MO.hasAllocatedReg()) {
278      OS << "==";
279      OutputReg(OS, MO.getReg(), MRI);
280    }
281    break;
282  case MachineOperand::MO_MachineRegister:
283    OutputReg(OS, MO.getMachineRegNum(), MRI);
284    break;
285  case MachineOperand::MO_SignExtendedImmed:
286    OS << (long)MO.getImmedValue();
287    break;
288  case MachineOperand::MO_UnextendedImmed:
289    OS << (long)MO.getImmedValue();
290    break;
291  case MachineOperand::MO_PCRelativeDisp: {
292    const Value* opVal = MO.getVRegValue();
293    bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
294    OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
295    if (opVal->hasName())
296      OS << opVal->getName();
297    else
298      OS << (const void*) opVal;
299    OS << ")";
300    break;
301  }
302  case MachineOperand::MO_MachineBasicBlock:
303    OS << "mbb<"
304       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
305       << "," << (void*)MO.getMachineBasicBlock() << ">";
306    break;
307  case MachineOperand::MO_FrameIndex:
308    OS << "<fi#" << MO.getFrameIndex() << ">";
309    break;
310  case MachineOperand::MO_ConstantPoolIndex:
311    OS << "<cp#" << MO.getConstantPoolIndex() << ">";
312    break;
313  case MachineOperand::MO_GlobalAddress:
314    OS << "<ga:" << ((Value*)MO.getGlobal())->getName();
315    if (MO.getOffset()) OS << "+" << MO.getOffset();
316    OS << ">";
317    break;
318  case MachineOperand::MO_ExternalSymbol:
319    OS << "<es:" << MO.getSymbolName();
320    if (MO.getOffset()) OS << "+" << MO.getOffset();
321    OS << ">";
322    break;
323  default:
324    assert(0 && "Unrecognized operand type");
325  }
326
327  if (CloseParen)
328    OS << ")";
329}
330
331void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
332  unsigned StartOp = 0;
333
334   // Specialize printing if op#0 is definition
335  if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
336    ::print(getOperand(0), OS, TM);
337    OS << " = ";
338    ++StartOp;   // Don't print this operand again!
339  }
340
341  // Must check if Target machine is not null because machine BB could not
342  // be attached to a Machine function yet
343  if (TM)
344    OS << TM->getInstrInfo()->getName(getOpcode());
345
346  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
347    const MachineOperand& mop = getOperand(i);
348    if (i != StartOp)
349      OS << ",";
350    OS << " ";
351    ::print(mop, OS, TM);
352
353    if (mop.isDef())
354      if (mop.isUse())
355        OS << "<def&use>";
356      else
357        OS << "<def>";
358  }
359
360  // code for printing implicit references
361  if (getNumImplicitRefs()) {
362    OS << "\tImplicitRefs: ";
363    for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
364      OS << "\t";
365      OutputValue(OS, getImplicitRef(i));
366      if (getImplicitOp(i).isDef())
367        if (getImplicitOp(i).isUse())
368          OS << "<def&use>";
369        else
370          OS << "<def>";
371    }
372  }
373
374  OS << "\n";
375}
376
377namespace llvm {
378std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
379  // If the instruction is embedded into a basic block, we can find the target
380  // info for the instruction.
381  if (const MachineBasicBlock *MBB = MI.getParent()) {
382    const MachineFunction *MF = MBB->getParent();
383    if (MF)
384      MI.print(os, &MF->getTarget());
385    else
386      MI.print(os, 0);
387    return os;
388  }
389
390  // Otherwise, print it out in the "raw" format without symbolic register names
391  // and such.
392  os << TargetInstrDescriptors[MI.getOpcode()].Name;
393
394  for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
395    os << "\t" << MI.getOperand(i);
396    if (MI.getOperand(i).isDef())
397      if (MI.getOperand(i).isUse())
398        os << "<d&u>";
399      else
400        os << "<d>";
401  }
402
403  // code for printing implicit references
404  unsigned NumOfImpRefs = MI.getNumImplicitRefs();
405  if (NumOfImpRefs > 0) {
406    os << "\tImplicit: ";
407    for (unsigned z = 0; z < NumOfImpRefs; z++) {
408      OutputValue(os, MI.getImplicitRef(z));
409      if (MI.getImplicitOp(z).isDef())
410          if (MI.getImplicitOp(z).isUse())
411            os << "<d&u>";
412          else
413            os << "<d>";
414      os << "\t";
415    }
416  }
417
418  return os << "\n";
419}
420
421std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
422  if (MO.isHiBits32())
423    OS << "%lm(";
424  else if (MO.isLoBits32())
425    OS << "%lo(";
426  else if (MO.isHiBits64())
427    OS << "%hh(";
428  else if (MO.isLoBits64())
429    OS << "%hm(";
430
431  switch (MO.getType()) {
432  case MachineOperand::MO_VirtualRegister:
433    if (MO.hasAllocatedReg())
434      OutputReg(OS, MO.getReg());
435
436    if (MO.getVRegValue()) {
437      if (MO.hasAllocatedReg()) OS << "==";
438      OS << "%vreg";
439      OutputValue(OS, MO.getVRegValue());
440    }
441    break;
442  case MachineOperand::MO_CCRegister:
443    OS << "%ccreg";
444    OutputValue(OS, MO.getVRegValue());
445    if (MO.hasAllocatedReg()) {
446      OS << "==";
447      OutputReg(OS, MO.getReg());
448    }
449    break;
450  case MachineOperand::MO_MachineRegister:
451    OutputReg(OS, MO.getMachineRegNum());
452    break;
453  case MachineOperand::MO_SignExtendedImmed:
454    OS << (long)MO.getImmedValue();
455    break;
456  case MachineOperand::MO_UnextendedImmed:
457    OS << (long)MO.getImmedValue();
458    break;
459  case MachineOperand::MO_PCRelativeDisp: {
460    const Value* opVal = MO.getVRegValue();
461    bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
462    OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
463    if (opVal->hasName())
464      OS << opVal->getName();
465    else
466      OS << (const void*) opVal;
467    OS << ")";
468    break;
469  }
470  case MachineOperand::MO_MachineBasicBlock:
471    OS << "<mbb:"
472       << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
473       << "@" << (void*)MO.getMachineBasicBlock() << ">";
474    break;
475  case MachineOperand::MO_FrameIndex:
476    OS << "<fi#" << MO.getFrameIndex() << ">";
477    break;
478  case MachineOperand::MO_ConstantPoolIndex:
479    OS << "<cp#" << MO.getConstantPoolIndex() << ">";
480    break;
481  case MachineOperand::MO_GlobalAddress:
482    OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
483    break;
484  case MachineOperand::MO_ExternalSymbol:
485    OS << "<es:" << MO.getSymbolName() << ">";
486    break;
487  default:
488    assert(0 && "Unrecognized operand type");
489    break;
490  }
491
492  if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
493    OS << ")";
494
495  return OS;
496}
497
498}
499