MachineInstr.cpp revision 4ce1a527c1586c262bbc981101f3bfea2ed8dfd1 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetInstrDesc.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Support/LeakDetector.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/Streams.h"
27#include <ostream>
28using namespace llvm;
29
30//===----------------------------------------------------------------------===//
31// MachineOperand Implementation
32//===----------------------------------------------------------------------===//
33
34/// AddRegOperandToRegInfo - Add this register operand to the specified
35/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
36/// explicitly nulled out.
37void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
38  assert(isReg() && "Can only add reg operand to use lists");
39
40  // If the reginfo pointer is null, just explicitly null out or next/prev
41  // pointers, to ensure they are not garbage.
42  if (RegInfo == 0) {
43    Contents.Reg.Prev = 0;
44    Contents.Reg.Next = 0;
45    return;
46  }
47
48  // Otherwise, add this operand to the head of the registers use/def list.
49  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
50
51  // For SSA values, we prefer to keep the definition at the start of the list.
52  // we do this by skipping over the definition if it is at the head of the
53  // list.
54  if (*Head && (*Head)->isDef())
55    Head = &(*Head)->Contents.Reg.Next;
56
57  Contents.Reg.Next = *Head;
58  if (Contents.Reg.Next) {
59    assert(getReg() == Contents.Reg.Next->getReg() &&
60           "Different regs on the same list!");
61    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
62  }
63
64  Contents.Reg.Prev = Head;
65  *Head = this;
66}
67
68void MachineOperand::setReg(unsigned Reg) {
69  if (getReg() == Reg) return; // No change.
70
71  // Otherwise, we have to change the register.  If this operand is embedded
72  // into a machine function, we need to update the old and new register's
73  // use/def lists.
74  if (MachineInstr *MI = getParent())
75    if (MachineBasicBlock *MBB = MI->getParent())
76      if (MachineFunction *MF = MBB->getParent()) {
77        RemoveRegOperandFromRegInfo();
78        Contents.Reg.RegNo = Reg;
79        AddRegOperandToRegInfo(&MF->getRegInfo());
80        return;
81      }
82
83  // Otherwise, just change the register, no problem.  :)
84  Contents.Reg.RegNo = Reg;
85}
86
87/// ChangeToImmediate - Replace this operand with a new immediate operand of
88/// the specified value.  If an operand is known to be an immediate already,
89/// the setImm method should be used.
90void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
91  // If this operand is currently a register operand, and if this is in a
92  // function, deregister the operand from the register's use/def list.
93  if (isReg() && getParent() && getParent()->getParent() &&
94      getParent()->getParent()->getParent())
95    RemoveRegOperandFromRegInfo();
96
97  OpKind = MO_Immediate;
98  Contents.ImmVal = ImmVal;
99}
100
101/// ChangeToRegister - Replace this operand with a new register operand of
102/// the specified value.  If an operand is known to be an register already,
103/// the setReg method should be used.
104void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
105                                      bool isKill, bool isDead) {
106  // If this operand is already a register operand, use setReg to update the
107  // register's use/def lists.
108  if (isReg()) {
109    setReg(Reg);
110  } else {
111    // Otherwise, change this to a register and set the reg#.
112    OpKind = MO_Register;
113    Contents.Reg.RegNo = Reg;
114
115    // If this operand is embedded in a function, add the operand to the
116    // register's use/def list.
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          AddRegOperandToRegInfo(&MF->getRegInfo());
121  }
122
123  IsDef = isDef;
124  IsImp = isImp;
125  IsKill = isKill;
126  IsDead = isDead;
127  SubReg = 0;
128}
129
130/// isIdenticalTo - Return true if this operand is identical to the specified
131/// operand.
132bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
133  if (getType() != Other.getType()) return false;
134
135  switch (getType()) {
136  default: assert(0 && "Unrecognized operand type");
137  case MachineOperand::MO_Register:
138    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
139           getSubReg() == Other.getSubReg();
140  case MachineOperand::MO_Immediate:
141    return getImm() == Other.getImm();
142  case MachineOperand::MO_FPImmediate:
143    return getFPImm() == Other.getFPImm();
144  case MachineOperand::MO_MachineBasicBlock:
145    return getMBB() == Other.getMBB();
146  case MachineOperand::MO_FrameIndex:
147    return getIndex() == Other.getIndex();
148  case MachineOperand::MO_ConstantPoolIndex:
149    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
150  case MachineOperand::MO_JumpTableIndex:
151    return getIndex() == Other.getIndex();
152  case MachineOperand::MO_GlobalAddress:
153    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
154  case MachineOperand::MO_ExternalSymbol:
155    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
156           getOffset() == Other.getOffset();
157  }
158}
159
160/// print - Print the specified machine operand.
161///
162void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
163  switch (getType()) {
164  case MachineOperand::MO_Register:
165    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
166      OS << "%reg" << getReg();
167    } else {
168      // If the instruction is embedded into a basic block, we can find the
169      // target info for the instruction.
170      if (TM == 0)
171        if (const MachineInstr *MI = getParent())
172          if (const MachineBasicBlock *MBB = MI->getParent())
173            if (const MachineFunction *MF = MBB->getParent())
174              TM = &MF->getTarget();
175
176      if (TM)
177        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
178      else
179        OS << "%mreg" << getReg();
180    }
181
182    if (isDef() || isKill() || isDead() || isImplicit()) {
183      OS << "<";
184      bool NeedComma = false;
185      if (isImplicit()) {
186        OS << (isDef() ? "imp-def" : "imp-use");
187        NeedComma = true;
188      } else if (isDef()) {
189        OS << "def";
190        NeedComma = true;
191      }
192      if (isKill() || isDead()) {
193        if (NeedComma) OS << ",";
194        if (isKill())  OS << "kill";
195        if (isDead())  OS << "dead";
196      }
197      OS << ">";
198    }
199    break;
200  case MachineOperand::MO_Immediate:
201    OS << getImm();
202    break;
203  case MachineOperand::MO_FPImmediate:
204    if (getFPImm()->getType() == Type::FloatTy) {
205      OS << getFPImm()->getValueAPF().convertToFloat();
206    } else {
207      OS << getFPImm()->getValueAPF().convertToDouble();
208    }
209    break;
210  case MachineOperand::MO_MachineBasicBlock:
211    OS << "mbb<"
212       << ((Value*)getMBB()->getBasicBlock())->getName()
213       << "," << (void*)getMBB() << ">";
214    break;
215  case MachineOperand::MO_FrameIndex:
216    OS << "<fi#" << getIndex() << ">";
217    break;
218  case MachineOperand::MO_ConstantPoolIndex:
219    OS << "<cp#" << getIndex();
220    if (getOffset()) OS << "+" << getOffset();
221    OS << ">";
222    break;
223  case MachineOperand::MO_JumpTableIndex:
224    OS << "<jt#" << getIndex() << ">";
225    break;
226  case MachineOperand::MO_GlobalAddress:
227    OS << "<ga:" << ((Value*)getGlobal())->getName();
228    if (getOffset()) OS << "+" << getOffset();
229    OS << ">";
230    break;
231  case MachineOperand::MO_ExternalSymbol:
232    OS << "<es:" << getSymbolName();
233    if (getOffset()) OS << "+" << getOffset();
234    OS << ">";
235    break;
236  default:
237    assert(0 && "Unrecognized operand type");
238  }
239}
240
241//===----------------------------------------------------------------------===//
242// MachineMemOperand Implementation
243//===----------------------------------------------------------------------===//
244
245MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
246                                     int64_t o, uint64_t s, unsigned int a)
247  : Offset(o), Size(s), V(v),
248    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
249  assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
250  assert((isLoad() || isStore()) && "Not a load/store!");
251}
252
253//===----------------------------------------------------------------------===//
254// MachineInstr Implementation
255//===----------------------------------------------------------------------===//
256
257/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
258/// TID NULL and no operands.
259MachineInstr::MachineInstr()
260  : TID(0), NumImplicitOps(0), Parent(0) {
261  // Make sure that we get added to a machine basicblock
262  LeakDetector::addGarbageObject(this);
263}
264
265void MachineInstr::addImplicitDefUseOperands() {
266  if (TID->ImplicitDefs)
267    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
268      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
269  if (TID->ImplicitUses)
270    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
271      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
272}
273
274/// MachineInstr ctor - This constructor create a MachineInstr and add the
275/// implicit operands. It reserves space for number of operands specified by
276/// TargetInstrDesc or the numOperands if it is not zero. (for
277/// instructions with variable number of operands).
278MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
279  : TID(&tid), NumImplicitOps(0), Parent(0) {
280  if (!NoImp && TID->getImplicitDefs())
281    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
282      NumImplicitOps++;
283  if (!NoImp && TID->getImplicitUses())
284    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
285      NumImplicitOps++;
286  Operands.reserve(NumImplicitOps + TID->getNumOperands());
287  if (!NoImp)
288    addImplicitDefUseOperands();
289  // Make sure that we get added to a machine basicblock
290  LeakDetector::addGarbageObject(this);
291}
292
293/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
294/// MachineInstr is created and added to the end of the specified basic block.
295///
296MachineInstr::MachineInstr(MachineBasicBlock *MBB,
297                           const TargetInstrDesc &tid)
298  : TID(&tid), NumImplicitOps(0), Parent(0) {
299  assert(MBB && "Cannot use inserting ctor with null basic block!");
300  if (TID->ImplicitDefs)
301    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
302      NumImplicitOps++;
303  if (TID->ImplicitUses)
304    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
305      NumImplicitOps++;
306  Operands.reserve(NumImplicitOps + TID->getNumOperands());
307  addImplicitDefUseOperands();
308  // Make sure that we get added to a machine basicblock
309  LeakDetector::addGarbageObject(this);
310  MBB->push_back(this);  // Add instruction to end of basic block!
311}
312
313/// MachineInstr ctor - Copies MachineInstr arg exactly
314///
315MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
316  : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
317  Operands.reserve(MI.getNumOperands());
318
319  // Add operands
320  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
321    addOperand(MI.getOperand(i));
322  NumImplicitOps = MI.NumImplicitOps;
323
324  // Add memory operands.
325  for (alist<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
326       j = MI.memoperands_end(); i != j; ++i)
327    addMemOperand(MF, *i);
328
329  // Set parent to null.
330  Parent = 0;
331}
332
333MachineInstr::~MachineInstr() {
334  LeakDetector::removeGarbageObject(this);
335  assert(MemOperands.empty() &&
336         "MachineInstr being deleted with live memoperands!");
337#ifndef NDEBUG
338  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
339    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
340    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
341           "Reg operand def/use list corrupted");
342  }
343#endif
344}
345
346/// getOpcode - Returns the opcode of this MachineInstr.
347///
348int MachineInstr::getOpcode() const {
349  return TID->Opcode;
350}
351
352/// getRegInfo - If this instruction is embedded into a MachineFunction,
353/// return the MachineRegisterInfo object for the current function, otherwise
354/// return null.
355MachineRegisterInfo *MachineInstr::getRegInfo() {
356  if (MachineBasicBlock *MBB = getParent())
357    return &MBB->getParent()->getRegInfo();
358  return 0;
359}
360
361/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
362/// this instruction from their respective use lists.  This requires that the
363/// operands already be on their use lists.
364void MachineInstr::RemoveRegOperandsFromUseLists() {
365  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
366    if (Operands[i].isReg())
367      Operands[i].RemoveRegOperandFromRegInfo();
368  }
369}
370
371/// AddRegOperandsToUseLists - Add all of the register operands in
372/// this instruction from their respective use lists.  This requires that the
373/// operands not be on their use lists yet.
374void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
375  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
376    if (Operands[i].isReg())
377      Operands[i].AddRegOperandToRegInfo(&RegInfo);
378  }
379}
380
381
382/// addOperand - Add the specified operand to the instruction.  If it is an
383/// implicit operand, it is added to the end of the operand list.  If it is
384/// an explicit operand it is added at the end of the explicit operand list
385/// (before the first implicit operand).
386void MachineInstr::addOperand(const MachineOperand &Op) {
387  bool isImpReg = Op.isReg() && Op.isImplicit();
388  assert((isImpReg || !OperandsComplete()) &&
389         "Trying to add an operand to a machine instr that is already done!");
390
391  // If we are adding the operand to the end of the list, our job is simpler.
392  // This is true most of the time, so this is a reasonable optimization.
393  if (isImpReg || NumImplicitOps == 0) {
394    // We can only do this optimization if we know that the operand list won't
395    // reallocate.
396    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
397      Operands.push_back(Op);
398
399      // Set the parent of the operand.
400      Operands.back().ParentMI = this;
401
402      // If the operand is a register, update the operand's use list.
403      if (Op.isReg())
404        Operands.back().AddRegOperandToRegInfo(getRegInfo());
405      return;
406    }
407  }
408
409  // Otherwise, we have to insert a real operand before any implicit ones.
410  unsigned OpNo = Operands.size()-NumImplicitOps;
411
412  MachineRegisterInfo *RegInfo = getRegInfo();
413
414  // If this instruction isn't embedded into a function, then we don't need to
415  // update any operand lists.
416  if (RegInfo == 0) {
417    // Simple insertion, no reginfo update needed for other register operands.
418    Operands.insert(Operands.begin()+OpNo, Op);
419    Operands[OpNo].ParentMI = this;
420
421    // Do explicitly set the reginfo for this operand though, to ensure the
422    // next/prev fields are properly nulled out.
423    if (Operands[OpNo].isReg())
424      Operands[OpNo].AddRegOperandToRegInfo(0);
425
426  } else if (Operands.size()+1 <= Operands.capacity()) {
427    // Otherwise, we have to remove register operands from their register use
428    // list, add the operand, then add the register operands back to their use
429    // list.  This also must handle the case when the operand list reallocates
430    // to somewhere else.
431
432    // If insertion of this operand won't cause reallocation of the operand
433    // list, just remove the implicit operands, add the operand, then re-add all
434    // the rest of the operands.
435    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
436      assert(Operands[i].isReg() && "Should only be an implicit reg!");
437      Operands[i].RemoveRegOperandFromRegInfo();
438    }
439
440    // Add the operand.  If it is a register, add it to the reg list.
441    Operands.insert(Operands.begin()+OpNo, Op);
442    Operands[OpNo].ParentMI = this;
443
444    if (Operands[OpNo].isReg())
445      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
446
447    // Re-add all the implicit ops.
448    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
449      assert(Operands[i].isReg() && "Should only be an implicit reg!");
450      Operands[i].AddRegOperandToRegInfo(RegInfo);
451    }
452  } else {
453    // Otherwise, we will be reallocating the operand list.  Remove all reg
454    // operands from their list, then readd them after the operand list is
455    // reallocated.
456    RemoveRegOperandsFromUseLists();
457
458    Operands.insert(Operands.begin()+OpNo, Op);
459    Operands[OpNo].ParentMI = this;
460
461    // Re-add all the operands.
462    AddRegOperandsToUseLists(*RegInfo);
463  }
464}
465
466/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
467/// fewer operand than it started with.
468///
469void MachineInstr::RemoveOperand(unsigned OpNo) {
470  assert(OpNo < Operands.size() && "Invalid operand number");
471
472  // Special case removing the last one.
473  if (OpNo == Operands.size()-1) {
474    // If needed, remove from the reg def/use list.
475    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
476      Operands.back().RemoveRegOperandFromRegInfo();
477
478    Operands.pop_back();
479    return;
480  }
481
482  // Otherwise, we are removing an interior operand.  If we have reginfo to
483  // update, remove all operands that will be shifted down from their reg lists,
484  // move everything down, then re-add them.
485  MachineRegisterInfo *RegInfo = getRegInfo();
486  if (RegInfo) {
487    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
488      if (Operands[i].isReg())
489        Operands[i].RemoveRegOperandFromRegInfo();
490    }
491  }
492
493  Operands.erase(Operands.begin()+OpNo);
494
495  if (RegInfo) {
496    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
497      if (Operands[i].isReg())
498        Operands[i].AddRegOperandToRegInfo(RegInfo);
499    }
500  }
501}
502
503/// addMemOperand - Add a MachineMemOperand to the machine instruction,
504/// referencing arbitrary storage.
505void MachineInstr::addMemOperand(MachineFunction &MF,
506                                 const MachineMemOperand &MO) {
507  MemOperands.push_back(MF.CreateMachineMemOperand(MO));
508}
509
510/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
511void MachineInstr::clearMemOperands(MachineFunction &MF) {
512  while (!MemOperands.empty())
513    MF.DeleteMachineMemOperand(MemOperands.remove(MemOperands.begin()));
514}
515
516
517/// removeFromParent - This method unlinks 'this' from the containing basic
518/// block, and returns it, but does not delete it.
519MachineInstr *MachineInstr::removeFromParent() {
520  assert(getParent() && "Not embedded in a basic block!");
521  getParent()->remove(this);
522  return this;
523}
524
525
526/// eraseFromParent - This method unlinks 'this' from the containing basic
527/// block, and deletes it.
528void MachineInstr::eraseFromParent() {
529  assert(getParent() && "Not embedded in a basic block!");
530  getParent()->erase(this);
531}
532
533
534/// OperandComplete - Return true if it's illegal to add a new operand
535///
536bool MachineInstr::OperandsComplete() const {
537  unsigned short NumOperands = TID->getNumOperands();
538  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
539    return true;  // Broken: we have all the operands of this instruction!
540  return false;
541}
542
543/// getNumExplicitOperands - Returns the number of non-implicit operands.
544///
545unsigned MachineInstr::getNumExplicitOperands() const {
546  unsigned NumOperands = TID->getNumOperands();
547  if (!TID->isVariadic())
548    return NumOperands;
549
550  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
551    const MachineOperand &MO = getOperand(NumOperands);
552    if (!MO.isRegister() || !MO.isImplicit())
553      NumOperands++;
554  }
555  return NumOperands;
556}
557
558
559/// isLabel - Returns true if the MachineInstr represents a label.
560///
561bool MachineInstr::isLabel() const {
562  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
563         getOpcode() == TargetInstrInfo::EH_LABEL ||
564         getOpcode() == TargetInstrInfo::GC_LABEL;
565}
566
567/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
568///
569bool MachineInstr::isDebugLabel() const {
570  return getOpcode() == TargetInstrInfo::DBG_LABEL;
571}
572
573/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
574/// the specific register or -1 if it is not found. It further tightening
575/// the search criteria to a use that kills the register if isKill is true.
576int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
577                                          const TargetRegisterInfo *TRI) const {
578  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
579    const MachineOperand &MO = getOperand(i);
580    if (!MO.isRegister() || !MO.isUse())
581      continue;
582    unsigned MOReg = MO.getReg();
583    if (!MOReg)
584      continue;
585    if (MOReg == Reg ||
586        (TRI &&
587         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
588         TargetRegisterInfo::isPhysicalRegister(Reg) &&
589         TRI->isSubRegister(MOReg, Reg)))
590      if (!isKill || MO.isKill())
591        return i;
592  }
593  return -1;
594}
595
596/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
597/// the specified register or -1 if it is not found. If isDead is true, defs
598/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
599/// also checks if there is a def of a super-register.
600int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
601                                          const TargetRegisterInfo *TRI) const {
602  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
603    const MachineOperand &MO = getOperand(i);
604    if (!MO.isRegister() || !MO.isDef())
605      continue;
606    unsigned MOReg = MO.getReg();
607    if (MOReg == Reg ||
608        (TRI &&
609         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
610         TargetRegisterInfo::isPhysicalRegister(Reg) &&
611         TRI->isSubRegister(MOReg, Reg)))
612      if (!isDead || MO.isDead())
613        return i;
614  }
615  return -1;
616}
617
618/// findFirstPredOperandIdx() - Find the index of the first operand in the
619/// operand list that is used to represent the predicate. It returns -1 if
620/// none is found.
621int MachineInstr::findFirstPredOperandIdx() const {
622  const TargetInstrDesc &TID = getDesc();
623  if (TID.isPredicable()) {
624    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
625      if (TID.OpInfo[i].isPredicate())
626        return i;
627  }
628
629  return -1;
630}
631
632/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
633/// check if the register def is a re-definition due to two addr elimination.
634bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
635  const TargetInstrDesc &TID = getDesc();
636  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
637    const MachineOperand &MO = getOperand(i);
638    if (MO.isRegister() && MO.isUse() && MO.getReg() == Reg &&
639        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
640      return true;
641  }
642  return false;
643}
644
645/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
646///
647void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
648  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
649    const MachineOperand &MO = MI->getOperand(i);
650    if (!MO.isRegister() || (!MO.isKill() && !MO.isDead()))
651      continue;
652    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
653      MachineOperand &MOp = getOperand(j);
654      if (!MOp.isIdenticalTo(MO))
655        continue;
656      if (MO.isKill())
657        MOp.setIsKill();
658      else
659        MOp.setIsDead();
660      break;
661    }
662  }
663}
664
665/// copyPredicates - Copies predicate operand(s) from MI.
666void MachineInstr::copyPredicates(const MachineInstr *MI) {
667  const TargetInstrDesc &TID = MI->getDesc();
668  if (!TID.isPredicable())
669    return;
670  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
671    if (TID.OpInfo[i].isPredicate()) {
672      // Predicated operands must be last operands.
673      addOperand(MI->getOperand(i));
674    }
675  }
676}
677
678/// isSafeToMove - Return true if it is safe to move this instruction. If
679/// SawStore is set to true, it means that there is a store (or call) between
680/// the instruction's location and its intended destination.
681bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, bool &SawStore) {
682  // Ignore stuff that we obviously can't move.
683  if (TID->mayStore() || TID->isCall()) {
684    SawStore = true;
685    return false;
686  }
687  if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
688    return false;
689
690  // See if this instruction does a load.  If so, we have to guarantee that the
691  // loaded value doesn't change between the load and the its intended
692  // destination. The check for isInvariantLoad gives the targe the chance to
693  // classify the load as always returning a constant, e.g. a constant pool
694  // load.
695  if (TID->mayLoad() && !TII->isInvariantLoad(this)) {
696    // Otherwise, this is a real load.  If there is a store between the load and
697    // end of block, we can't sink the load.
698    //
699    // FIXME: we can't do this transformation until we know that the load is
700    // not volatile, and machineinstrs don't keep this info. :(
701    //
702    //if (SawStore)
703    return false;
704  }
705  return true;
706}
707
708void MachineInstr::dump() const {
709  cerr << "  " << *this;
710}
711
712void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
713  // Specialize printing if op#0 is definition
714  unsigned StartOp = 0;
715  if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
716    getOperand(0).print(OS, TM);
717    OS << " = ";
718    ++StartOp;   // Don't print this operand again!
719  }
720
721  OS << getDesc().getName();
722
723  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
724    if (i != StartOp)
725      OS << ",";
726    OS << " ";
727    getOperand(i).print(OS, TM);
728  }
729
730  if (!memoperands_empty()) {
731    OS << ", Mem:";
732    for (alist<MachineMemOperand>::const_iterator i = memoperands_begin(),
733         e = memoperands_end(); i != e; ++i) {
734      const MachineMemOperand &MRO = *i;
735      const Value *V = MRO.getValue();
736
737      assert((MRO.isLoad() || MRO.isStore()) &&
738             "SV has to be a load, store or both.");
739
740      if (MRO.isVolatile())
741        OS << "Volatile ";
742
743      if (MRO.isLoad())
744        OS << "LD";
745      if (MRO.isStore())
746        OS << "ST";
747
748      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
749
750      if (!V)
751        OS << "<unknown>";
752      else if (!V->getName().empty())
753        OS << V->getName();
754      else if (isa<PseudoSourceValue>(V))
755        OS << *V;
756      else
757        OS << V;
758
759      OS << " + " << MRO.getOffset() << "]";
760    }
761  }
762
763  OS << "\n";
764}
765
766bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
767                                     const TargetRegisterInfo *RegInfo,
768                                     bool AddIfNotFound) {
769  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
770  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
771  SmallVector<unsigned,4> DeadOps;
772  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
773    MachineOperand &MO = getOperand(i);
774    if (!MO.isRegister() || !MO.isUse())
775      continue;
776    unsigned Reg = MO.getReg();
777    if (!Reg)
778      continue;
779
780    if (Reg == IncomingReg) {
781      MO.setIsKill();
782      return true;
783    }
784    if (hasAliases && MO.isKill() &&
785        TargetRegisterInfo::isPhysicalRegister(Reg)) {
786      // A super-register kill already exists.
787      if (RegInfo->isSuperRegister(IncomingReg, Reg))
788        return true;
789      if (RegInfo->isSubRegister(IncomingReg, Reg))
790        DeadOps.push_back(i);
791    }
792  }
793
794  // Trim unneeded kill operands.
795  while (!DeadOps.empty()) {
796    unsigned OpIdx = DeadOps.back();
797    if (getOperand(OpIdx).isImplicit())
798      RemoveOperand(OpIdx);
799    else
800      getOperand(OpIdx).setIsKill(false);
801    DeadOps.pop_back();
802  }
803
804  // If not found, this means an alias of one of the operands is killed. Add a
805  // new implicit operand if required.
806  if (AddIfNotFound) {
807    addOperand(MachineOperand::CreateReg(IncomingReg,
808                                         false /*IsDef*/,
809                                         true  /*IsImp*/,
810                                         true  /*IsKill*/));
811    return true;
812  }
813  return false;
814}
815
816bool MachineInstr::addRegisterDead(unsigned IncomingReg,
817                                   const TargetRegisterInfo *RegInfo,
818                                   bool AddIfNotFound) {
819  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
820  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
821  SmallVector<unsigned,4> DeadOps;
822  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
823    MachineOperand &MO = getOperand(i);
824    if (!MO.isRegister() || !MO.isDef())
825      continue;
826    unsigned Reg = MO.getReg();
827    if (Reg == IncomingReg) {
828      MO.setIsDead();
829      return true;
830    }
831    if (hasAliases && MO.isDead() &&
832        TargetRegisterInfo::isPhysicalRegister(Reg)) {
833      // There exists a super-register that's marked dead.
834      if (RegInfo->isSuperRegister(IncomingReg, Reg))
835        return true;
836      if (RegInfo->isSubRegister(IncomingReg, Reg))
837        DeadOps.push_back(i);
838    }
839  }
840
841  // Trim unneeded dead operands.
842  while (!DeadOps.empty()) {
843    unsigned OpIdx = DeadOps.back();
844    if (getOperand(OpIdx).isImplicit())
845      RemoveOperand(OpIdx);
846    else
847      getOperand(OpIdx).setIsDead(false);
848    DeadOps.pop_back();
849  }
850
851  // If not found, this means an alias of one of the operand is dead. Add a
852  // new implicit operand.
853  if (AddIfNotFound) {
854    addOperand(MachineOperand::CreateReg(IncomingReg, true/*IsDef*/,
855                                         true/*IsImp*/,false/*IsKill*/,
856                                         true/*IsDead*/));
857    return true;
858  }
859  return false;
860}
861