MachineInstr.cpp revision 56706db45bbc7be0c087451ca9f1d258324df4b2 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/FoldingSet.h"
16#include "llvm/ADT/Hashing.h"
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/Assembly/Writer.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/Constants.h"
26#include "llvm/DebugInfo.h"
27#include "llvm/Function.h"
28#include "llvm/InlineAsm.h"
29#include "llvm/LLVMContext.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Metadata.h"
33#include "llvm/Module.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetMachine.h"
41#include "llvm/Target/TargetRegisterInfo.h"
42#include "llvm/Type.h"
43#include "llvm/Value.h"
44using namespace llvm;
45
46//===----------------------------------------------------------------------===//
47// MachineOperand Implementation
48//===----------------------------------------------------------------------===//
49
50void MachineOperand::setReg(unsigned Reg) {
51  if (getReg() == Reg) return; // No change.
52
53  // Otherwise, we have to change the register.  If this operand is embedded
54  // into a machine function, we need to update the old and new register's
55  // use/def lists.
56  if (MachineInstr *MI = getParent())
57    if (MachineBasicBlock *MBB = MI->getParent())
58      if (MachineFunction *MF = MBB->getParent()) {
59        MachineRegisterInfo &MRI = MF->getRegInfo();
60        MRI.removeRegOperandFromUseList(this);
61        SmallContents.RegNo = Reg;
62        MRI.addRegOperandToUseList(this);
63        return;
64      }
65
66  // Otherwise, just change the register, no problem.  :)
67  SmallContents.RegNo = Reg;
68}
69
70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71                                  const TargetRegisterInfo &TRI) {
72  assert(TargetRegisterInfo::isVirtualRegister(Reg));
73  if (SubIdx && getSubReg())
74    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75  setReg(Reg);
76  if (SubIdx)
77    setSubReg(SubIdx);
78}
79
80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82  if (getSubReg()) {
83    Reg = TRI.getSubReg(Reg, getSubReg());
84    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85    // That won't happen in legal code.
86    setSubReg(0);
87  }
88  setReg(Reg);
89}
90
91/// Change a def to a use, or a use to a def.
92void MachineOperand::setIsDef(bool Val) {
93  assert(isReg() && "Wrong MachineOperand accessor");
94  assert((!Val || !isDebug()) && "Marking a debug operation as def");
95  if (IsDef == Val)
96    return;
97  // MRI may keep uses and defs in different list positions.
98  if (MachineInstr *MI = getParent())
99    if (MachineBasicBlock *MBB = MI->getParent())
100      if (MachineFunction *MF = MBB->getParent()) {
101        MachineRegisterInfo &MRI = MF->getRegInfo();
102        MRI.removeRegOperandFromUseList(this);
103        IsDef = Val;
104        MRI.addRegOperandToUseList(this);
105        return;
106      }
107  IsDef = Val;
108}
109
110/// ChangeToImmediate - Replace this operand with a new immediate operand of
111/// the specified value.  If an operand is known to be an immediate already,
112/// the setImm method should be used.
113void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115  // If this operand is currently a register operand, and if this is in a
116  // function, deregister the operand from the register's use/def list.
117  if (isReg() && isOnRegUseList())
118    if (MachineInstr *MI = getParent())
119      if (MachineBasicBlock *MBB = MI->getParent())
120        if (MachineFunction *MF = MBB->getParent())
121          MF->getRegInfo().removeRegOperandFromUseList(this);
122
123  OpKind = MO_Immediate;
124  Contents.ImmVal = ImmVal;
125}
126
127/// ChangeToRegister - Replace this operand with a new register operand of
128/// the specified value.  If an operand is known to be an register already,
129/// the setReg method should be used.
130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131                                      bool isKill, bool isDead, bool isUndef,
132                                      bool isDebug) {
133  MachineRegisterInfo *RegInfo = 0;
134  if (MachineInstr *MI = getParent())
135    if (MachineBasicBlock *MBB = MI->getParent())
136      if (MachineFunction *MF = MBB->getParent())
137        RegInfo = &MF->getRegInfo();
138  // If this operand is already a register operand, remove it from the
139  // register's use/def lists.
140  bool WasReg = isReg();
141  if (RegInfo && WasReg)
142    RegInfo->removeRegOperandFromUseList(this);
143
144  // Change this to a register and set the reg#.
145  OpKind = MO_Register;
146  SmallContents.RegNo = Reg;
147  SubReg = 0;
148  IsDef = isDef;
149  IsImp = isImp;
150  IsKill = isKill;
151  IsDead = isDead;
152  IsUndef = isUndef;
153  IsInternalRead = false;
154  IsEarlyClobber = false;
155  IsDebug = isDebug;
156  // Ensure isOnRegUseList() returns false.
157  Contents.Reg.Prev = 0;
158  // Preserve the tie when the operand was already a register.
159  if (!WasReg)
160    TiedTo = 0;
161
162  // If this operand is embedded in a function, add the operand to the
163  // register's use/def list.
164  if (RegInfo)
165    RegInfo->addRegOperandToUseList(this);
166}
167
168/// isIdenticalTo - Return true if this operand is identical to the specified
169/// operand. Note that this should stay in sync with the hash_value overload
170/// below.
171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172  if (getType() != Other.getType() ||
173      getTargetFlags() != Other.getTargetFlags())
174    return false;
175
176  switch (getType()) {
177  case MachineOperand::MO_Register:
178    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179           getSubReg() == Other.getSubReg();
180  case MachineOperand::MO_Immediate:
181    return getImm() == Other.getImm();
182  case MachineOperand::MO_CImmediate:
183    return getCImm() == Other.getCImm();
184  case MachineOperand::MO_FPImmediate:
185    return getFPImm() == Other.getFPImm();
186  case MachineOperand::MO_MachineBasicBlock:
187    return getMBB() == Other.getMBB();
188  case MachineOperand::MO_FrameIndex:
189    return getIndex() == Other.getIndex();
190  case MachineOperand::MO_ConstantPoolIndex:
191  case MachineOperand::MO_TargetIndex:
192    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193  case MachineOperand::MO_JumpTableIndex:
194    return getIndex() == Other.getIndex();
195  case MachineOperand::MO_GlobalAddress:
196    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197  case MachineOperand::MO_ExternalSymbol:
198    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199           getOffset() == Other.getOffset();
200  case MachineOperand::MO_BlockAddress:
201    return getBlockAddress() == Other.getBlockAddress() &&
202           getOffset() == Other.getOffset();
203  case MO_RegisterMask:
204    return getRegMask() == Other.getRegMask();
205  case MachineOperand::MO_MCSymbol:
206    return getMCSymbol() == Other.getMCSymbol();
207  case MachineOperand::MO_Metadata:
208    return getMetadata() == Other.getMetadata();
209  }
210  llvm_unreachable("Invalid machine operand type");
211}
212
213// Note: this must stay exactly in sync with isIdenticalTo above.
214hash_code llvm::hash_value(const MachineOperand &MO) {
215  switch (MO.getType()) {
216  case MachineOperand::MO_Register:
217    // Register operands don't have target flags.
218    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
219  case MachineOperand::MO_Immediate:
220    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
221  case MachineOperand::MO_CImmediate:
222    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
223  case MachineOperand::MO_FPImmediate:
224    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
225  case MachineOperand::MO_MachineBasicBlock:
226    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
227  case MachineOperand::MO_FrameIndex:
228    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
229  case MachineOperand::MO_ConstantPoolIndex:
230  case MachineOperand::MO_TargetIndex:
231    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
232                        MO.getOffset());
233  case MachineOperand::MO_JumpTableIndex:
234    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
235  case MachineOperand::MO_ExternalSymbol:
236    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
237                        MO.getSymbolName());
238  case MachineOperand::MO_GlobalAddress:
239    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
240                        MO.getOffset());
241  case MachineOperand::MO_BlockAddress:
242    return hash_combine(MO.getType(), MO.getTargetFlags(),
243                        MO.getBlockAddress(), MO.getOffset());
244  case MachineOperand::MO_RegisterMask:
245    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
246  case MachineOperand::MO_Metadata:
247    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
248  case MachineOperand::MO_MCSymbol:
249    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
250  }
251  llvm_unreachable("Invalid machine operand type");
252}
253
254/// print - Print the specified machine operand.
255///
256void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
257  // If the instruction is embedded into a basic block, we can find the
258  // target info for the instruction.
259  if (!TM)
260    if (const MachineInstr *MI = getParent())
261      if (const MachineBasicBlock *MBB = MI->getParent())
262        if (const MachineFunction *MF = MBB->getParent())
263          TM = &MF->getTarget();
264  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
265
266  switch (getType()) {
267  case MachineOperand::MO_Register:
268    OS << PrintReg(getReg(), TRI, getSubReg());
269
270    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
271        isInternalRead() || isEarlyClobber() || isTied()) {
272      OS << '<';
273      bool NeedComma = false;
274      if (isDef()) {
275        if (NeedComma) OS << ',';
276        if (isEarlyClobber())
277          OS << "earlyclobber,";
278        if (isImplicit())
279          OS << "imp-";
280        OS << "def";
281        NeedComma = true;
282        // <def,read-undef> only makes sense when getSubReg() is set.
283        // Don't clutter the output otherwise.
284        if (isUndef() && getSubReg())
285          OS << ",read-undef";
286      } else if (isImplicit()) {
287          OS << "imp-use";
288          NeedComma = true;
289      }
290
291      if (isKill()) {
292        if (NeedComma) OS << ',';
293        OS << "kill";
294        NeedComma = true;
295      }
296      if (isDead()) {
297        if (NeedComma) OS << ',';
298        OS << "dead";
299        NeedComma = true;
300      }
301      if (isUndef() && isUse()) {
302        if (NeedComma) OS << ',';
303        OS << "undef";
304        NeedComma = true;
305      }
306      if (isInternalRead()) {
307        if (NeedComma) OS << ',';
308        OS << "internal";
309        NeedComma = true;
310      }
311      if (isTied()) {
312        if (NeedComma) OS << ',';
313        OS << "tied";
314        if (TiedTo != 15)
315          OS << unsigned(TiedTo - 1);
316        NeedComma = true;
317      }
318      OS << '>';
319    }
320    break;
321  case MachineOperand::MO_Immediate:
322    OS << getImm();
323    break;
324  case MachineOperand::MO_CImmediate:
325    getCImm()->getValue().print(OS, false);
326    break;
327  case MachineOperand::MO_FPImmediate:
328    if (getFPImm()->getType()->isFloatTy())
329      OS << getFPImm()->getValueAPF().convertToFloat();
330    else
331      OS << getFPImm()->getValueAPF().convertToDouble();
332    break;
333  case MachineOperand::MO_MachineBasicBlock:
334    OS << "<BB#" << getMBB()->getNumber() << ">";
335    break;
336  case MachineOperand::MO_FrameIndex:
337    OS << "<fi#" << getIndex() << '>';
338    break;
339  case MachineOperand::MO_ConstantPoolIndex:
340    OS << "<cp#" << getIndex();
341    if (getOffset()) OS << "+" << getOffset();
342    OS << '>';
343    break;
344  case MachineOperand::MO_TargetIndex:
345    OS << "<ti#" << getIndex();
346    if (getOffset()) OS << "+" << getOffset();
347    OS << '>';
348    break;
349  case MachineOperand::MO_JumpTableIndex:
350    OS << "<jt#" << getIndex() << '>';
351    break;
352  case MachineOperand::MO_GlobalAddress:
353    OS << "<ga:";
354    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
355    if (getOffset()) OS << "+" << getOffset();
356    OS << '>';
357    break;
358  case MachineOperand::MO_ExternalSymbol:
359    OS << "<es:" << getSymbolName();
360    if (getOffset()) OS << "+" << getOffset();
361    OS << '>';
362    break;
363  case MachineOperand::MO_BlockAddress:
364    OS << '<';
365    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
366    if (getOffset()) OS << "+" << getOffset();
367    OS << '>';
368    break;
369  case MachineOperand::MO_RegisterMask:
370    OS << "<regmask>";
371    break;
372  case MachineOperand::MO_Metadata:
373    OS << '<';
374    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
375    OS << '>';
376    break;
377  case MachineOperand::MO_MCSymbol:
378    OS << "<MCSym=" << *getMCSymbol() << '>';
379    break;
380  }
381
382  if (unsigned TF = getTargetFlags())
383    OS << "[TF=" << TF << ']';
384}
385
386//===----------------------------------------------------------------------===//
387// MachineMemOperand Implementation
388//===----------------------------------------------------------------------===//
389
390/// getAddrSpace - Return the LLVM IR address space number that this pointer
391/// points into.
392unsigned MachinePointerInfo::getAddrSpace() const {
393  if (V == 0) return 0;
394  return cast<PointerType>(V->getType())->getAddressSpace();
395}
396
397/// getConstantPool - Return a MachinePointerInfo record that refers to the
398/// constant pool.
399MachinePointerInfo MachinePointerInfo::getConstantPool() {
400  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
401}
402
403/// getFixedStack - Return a MachinePointerInfo record that refers to the
404/// the specified FrameIndex.
405MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
406  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
407}
408
409MachinePointerInfo MachinePointerInfo::getJumpTable() {
410  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
411}
412
413MachinePointerInfo MachinePointerInfo::getGOT() {
414  return MachinePointerInfo(PseudoSourceValue::getGOT());
415}
416
417MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
418  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
419}
420
421MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
422                                     uint64_t s, unsigned int a,
423                                     const MDNode *TBAAInfo,
424                                     const MDNode *Ranges)
425  : PtrInfo(ptrinfo), Size(s),
426    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
427    TBAAInfo(TBAAInfo), Ranges(Ranges) {
428  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
429         "invalid pointer value");
430  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
431  assert((isLoad() || isStore()) && "Not a load/store!");
432}
433
434/// Profile - Gather unique data for the object.
435///
436void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
437  ID.AddInteger(getOffset());
438  ID.AddInteger(Size);
439  ID.AddPointer(getValue());
440  ID.AddInteger(Flags);
441}
442
443void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
444  // The Value and Offset may differ due to CSE. But the flags and size
445  // should be the same.
446  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
447  assert(MMO->getSize() == getSize() && "Size mismatch!");
448
449  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
450    // Update the alignment value.
451    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
452      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
453    // Also update the base and offset, because the new alignment may
454    // not be applicable with the old ones.
455    PtrInfo = MMO->PtrInfo;
456  }
457}
458
459/// getAlignment - Return the minimum known alignment in bytes of the
460/// actual memory reference.
461uint64_t MachineMemOperand::getAlignment() const {
462  return MinAlign(getBaseAlignment(), getOffset());
463}
464
465raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
466  assert((MMO.isLoad() || MMO.isStore()) &&
467         "SV has to be a load, store or both.");
468
469  if (MMO.isVolatile())
470    OS << "Volatile ";
471
472  if (MMO.isLoad())
473    OS << "LD";
474  if (MMO.isStore())
475    OS << "ST";
476  OS << MMO.getSize();
477
478  // Print the address information.
479  OS << "[";
480  if (!MMO.getValue())
481    OS << "<unknown>";
482  else
483    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
484
485  // If the alignment of the memory reference itself differs from the alignment
486  // of the base pointer, print the base alignment explicitly, next to the base
487  // pointer.
488  if (MMO.getBaseAlignment() != MMO.getAlignment())
489    OS << "(align=" << MMO.getBaseAlignment() << ")";
490
491  if (MMO.getOffset() != 0)
492    OS << "+" << MMO.getOffset();
493  OS << "]";
494
495  // Print the alignment of the reference.
496  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
497      MMO.getBaseAlignment() != MMO.getSize())
498    OS << "(align=" << MMO.getAlignment() << ")";
499
500  // Print TBAA info.
501  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
502    OS << "(tbaa=";
503    if (TBAAInfo->getNumOperands() > 0)
504      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
505    else
506      OS << "<unknown>";
507    OS << ")";
508  }
509
510  // Print nontemporal info.
511  if (MMO.isNonTemporal())
512    OS << "(nontemporal)";
513
514  return OS;
515}
516
517//===----------------------------------------------------------------------===//
518// MachineInstr Implementation
519//===----------------------------------------------------------------------===//
520
521void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
522  if (MCID->ImplicitDefs)
523    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
524      addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
525  if (MCID->ImplicitUses)
526    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
527      addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
528}
529
530/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
531/// implicit operands. It reserves space for the number of operands specified by
532/// the MCInstrDesc.
533MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
534                           const DebugLoc dl, bool NoImp)
535  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
536    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
537  unsigned NumImplicitOps = 0;
538  if (!NoImp)
539    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
540  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
541  if (!NoImp)
542    addImplicitDefUseOperands(MF);
543  // Make sure that we get added to a machine basicblock
544  LeakDetector::addGarbageObject(this);
545}
546
547/// MachineInstr ctor - Copies MachineInstr arg exactly
548///
549MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
550  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
551    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
552    Parent(0), debugLoc(MI.getDebugLoc()) {
553  Operands.reserve(MI.getNumOperands());
554
555  // Add operands
556  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
557    addOperand(MF, MI.getOperand(i));
558
559  // Copy all the sensible flags.
560  setFlags(MI.Flags);
561
562  // Set parent to null.
563  Parent = 0;
564
565  LeakDetector::addGarbageObject(this);
566}
567
568MachineInstr::~MachineInstr() {
569  LeakDetector::removeGarbageObject(this);
570#ifndef NDEBUG
571  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
572    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
573    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
574           "Reg operand def/use list corrupted");
575  }
576#endif
577}
578
579/// getRegInfo - If this instruction is embedded into a MachineFunction,
580/// return the MachineRegisterInfo object for the current function, otherwise
581/// return null.
582MachineRegisterInfo *MachineInstr::getRegInfo() {
583  if (MachineBasicBlock *MBB = getParent())
584    return &MBB->getParent()->getRegInfo();
585  return 0;
586}
587
588/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
589/// this instruction from their respective use lists.  This requires that the
590/// operands already be on their use lists.
591void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
592  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
593    if (Operands[i].isReg())
594      MRI.removeRegOperandFromUseList(&Operands[i]);
595}
596
597/// AddRegOperandsToUseLists - Add all of the register operands in
598/// this instruction from their respective use lists.  This requires that the
599/// operands not be on their use lists yet.
600void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
601  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
602    if (Operands[i].isReg())
603      MRI.addRegOperandToUseList(&Operands[i]);
604}
605
606void MachineInstr::addOperand(const MachineOperand &Op) {
607  MachineBasicBlock *MBB = getParent();
608  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
609  MachineFunction *MF = MBB->getParent();
610  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
611  addOperand(*MF, Op);
612}
613
614/// addOperand - Add the specified operand to the instruction.  If it is an
615/// implicit operand, it is added to the end of the operand list.  If it is
616/// an explicit operand it is added at the end of the explicit operand list
617/// (before the first implicit operand).
618void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
619  assert(MCID && "Cannot add operands before providing an instr descriptor");
620  bool isImpReg = Op.isReg() && Op.isImplicit();
621  MachineRegisterInfo *RegInfo = getRegInfo();
622
623  // If the Operands backing store is reallocated, all register operands must
624  // be removed and re-added to RegInfo.  It is storing pointers to operands.
625  bool Reallocate = RegInfo &&
626    !Operands.empty() && Operands.size() == Operands.capacity();
627
628  // Find the insert location for the new operand.  Implicit registers go at
629  // the end, everything goes before the implicit regs.
630  unsigned OpNo = Operands.size();
631
632  // Remove all the implicit operands from RegInfo if they need to be shifted.
633  // FIXME: Allow mixed explicit and implicit operands on inline asm.
634  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
635  // implicit-defs, but they must not be moved around.  See the FIXME in
636  // InstrEmitter.cpp.
637  if (!isImpReg && !isInlineAsm()) {
638    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
639      --OpNo;
640      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
641      if (RegInfo)
642        RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
643    }
644  }
645
646  // OpNo now points as the desired insertion point.  Unless this is a variadic
647  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
648  // RegMask operands go between the explicit and implicit operands.
649  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
650          OpNo < MCID->getNumOperands()) &&
651         "Trying to add an operand to a machine instr that is already done!");
652
653  // All operands from OpNo have been removed from RegInfo.  If the Operands
654  // backing store needs to be reallocated, we also need to remove any other
655  // register operands.
656  if (Reallocate)
657    for (unsigned i = 0; i != OpNo; ++i)
658      if (Operands[i].isReg())
659        RegInfo->removeRegOperandFromUseList(&Operands[i]);
660
661  // Insert the new operand at OpNo.
662  Operands.insert(Operands.begin() + OpNo, Op);
663  Operands[OpNo].ParentMI = this;
664
665  // The Operands backing store has now been reallocated, so we can re-add the
666  // operands before OpNo.
667  if (Reallocate)
668    for (unsigned i = 0; i != OpNo; ++i)
669      if (Operands[i].isReg())
670        RegInfo->addRegOperandToUseList(&Operands[i]);
671
672  // When adding a register operand, tell RegInfo about it.
673  if (Operands[OpNo].isReg()) {
674    // Ensure isOnRegUseList() returns false, regardless of Op's status.
675    Operands[OpNo].Contents.Reg.Prev = 0;
676    // Ignore existing ties. This is not a property that can be copied.
677    Operands[OpNo].TiedTo = 0;
678    // Add the new operand to RegInfo.
679    if (RegInfo)
680      RegInfo->addRegOperandToUseList(&Operands[OpNo]);
681    // The MCID operand information isn't accurate until we start adding
682    // explicit operands. The implicit operands are added first, then the
683    // explicits are inserted before them.
684    if (!isImpReg) {
685      // Tie uses to defs as indicated in MCInstrDesc.
686      if (Operands[OpNo].isUse()) {
687        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
688        if (DefIdx != -1)
689          tieOperands(DefIdx, OpNo);
690      }
691      // If the register operand is flagged as early, mark the operand as such.
692      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
693        Operands[OpNo].setIsEarlyClobber(true);
694    }
695  }
696
697  // Re-add all the implicit ops.
698  if (RegInfo) {
699    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
700      assert(Operands[i].isReg() && "Should only be an implicit reg!");
701      RegInfo->addRegOperandToUseList(&Operands[i]);
702    }
703  }
704}
705
706/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
707/// fewer operand than it started with.
708///
709void MachineInstr::RemoveOperand(unsigned OpNo) {
710  assert(OpNo < Operands.size() && "Invalid operand number");
711  untieRegOperand(OpNo);
712  MachineRegisterInfo *RegInfo = getRegInfo();
713
714  // Special case removing the last one.
715  if (OpNo == Operands.size()-1) {
716    // If needed, remove from the reg def/use list.
717    if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
718      RegInfo->removeRegOperandFromUseList(&Operands.back());
719
720    Operands.pop_back();
721    return;
722  }
723
724  // Otherwise, we are removing an interior operand.  If we have reginfo to
725  // update, remove all operands that will be shifted down from their reg lists,
726  // move everything down, then re-add them.
727  if (RegInfo) {
728    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
729      if (Operands[i].isReg())
730        RegInfo->removeRegOperandFromUseList(&Operands[i]);
731    }
732  }
733
734#ifndef NDEBUG
735  // Moving tied operands would break the ties.
736  for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i)
737    if (Operands[i].isReg())
738      assert(!Operands[i].isTied() && "Cannot move tied operands");
739#endif
740
741  Operands.erase(Operands.begin()+OpNo);
742
743  if (RegInfo) {
744    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
745      if (Operands[i].isReg())
746        RegInfo->addRegOperandToUseList(&Operands[i]);
747    }
748  }
749}
750
751/// addMemOperand - Add a MachineMemOperand to the machine instruction.
752/// This function should be used only occasionally. The setMemRefs function
753/// is the primary method for setting up a MachineInstr's MemRefs list.
754void MachineInstr::addMemOperand(MachineFunction &MF,
755                                 MachineMemOperand *MO) {
756  mmo_iterator OldMemRefs = MemRefs;
757  uint16_t OldNumMemRefs = NumMemRefs;
758
759  uint16_t NewNum = NumMemRefs + 1;
760  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
761
762  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
763  NewMemRefs[NewNum - 1] = MO;
764
765  MemRefs = NewMemRefs;
766  NumMemRefs = NewNum;
767}
768
769bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
770  const MachineBasicBlock *MBB = getParent();
771  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
772  while (MII != MBB->end() && MII->isInsideBundle()) {
773    if (MII->getDesc().getFlags() & Mask) {
774      if (Type == AnyInBundle)
775        return true;
776    } else {
777      if (Type == AllInBundle)
778        return false;
779    }
780    ++MII;
781  }
782
783  return Type == AllInBundle;
784}
785
786bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
787                                 MICheckType Check) const {
788  // If opcodes or number of operands are not the same then the two
789  // instructions are obviously not identical.
790  if (Other->getOpcode() != getOpcode() ||
791      Other->getNumOperands() != getNumOperands())
792    return false;
793
794  if (isBundle()) {
795    // Both instructions are bundles, compare MIs inside the bundle.
796    MachineBasicBlock::const_instr_iterator I1 = *this;
797    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
798    MachineBasicBlock::const_instr_iterator I2 = *Other;
799    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
800    while (++I1 != E1 && I1->isInsideBundle()) {
801      ++I2;
802      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
803        return false;
804    }
805  }
806
807  // Check operands to make sure they match.
808  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
809    const MachineOperand &MO = getOperand(i);
810    const MachineOperand &OMO = Other->getOperand(i);
811    if (!MO.isReg()) {
812      if (!MO.isIdenticalTo(OMO))
813        return false;
814      continue;
815    }
816
817    // Clients may or may not want to ignore defs when testing for equality.
818    // For example, machine CSE pass only cares about finding common
819    // subexpressions, so it's safe to ignore virtual register defs.
820    if (MO.isDef()) {
821      if (Check == IgnoreDefs)
822        continue;
823      else if (Check == IgnoreVRegDefs) {
824        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
825            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
826          if (MO.getReg() != OMO.getReg())
827            return false;
828      } else {
829        if (!MO.isIdenticalTo(OMO))
830          return false;
831        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
832          return false;
833      }
834    } else {
835      if (!MO.isIdenticalTo(OMO))
836        return false;
837      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
838        return false;
839    }
840  }
841  // If DebugLoc does not match then two dbg.values are not identical.
842  if (isDebugValue())
843    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
844        && getDebugLoc() != Other->getDebugLoc())
845      return false;
846  return true;
847}
848
849MachineInstr *MachineInstr::removeFromParent() {
850  assert(getParent() && "Not embedded in a basic block!");
851  return getParent()->remove(this);
852}
853
854MachineInstr *MachineInstr::removeFromBundle() {
855  assert(getParent() && "Not embedded in a basic block!");
856  return getParent()->remove_instr(this);
857}
858
859void MachineInstr::eraseFromParent() {
860  assert(getParent() && "Not embedded in a basic block!");
861  getParent()->erase(this);
862}
863
864void MachineInstr::eraseFromBundle() {
865  assert(getParent() && "Not embedded in a basic block!");
866  getParent()->erase_instr(this);
867}
868
869/// getNumExplicitOperands - Returns the number of non-implicit operands.
870///
871unsigned MachineInstr::getNumExplicitOperands() const {
872  unsigned NumOperands = MCID->getNumOperands();
873  if (!MCID->isVariadic())
874    return NumOperands;
875
876  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
877    const MachineOperand &MO = getOperand(i);
878    if (!MO.isReg() || !MO.isImplicit())
879      NumOperands++;
880  }
881  return NumOperands;
882}
883
884void MachineInstr::bundleWithPred() {
885  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
886  setFlag(BundledPred);
887  MachineBasicBlock::instr_iterator Pred = this;
888  --Pred;
889  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
890  Pred->setFlag(BundledSucc);
891}
892
893void MachineInstr::bundleWithSucc() {
894  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
895  setFlag(BundledSucc);
896  MachineBasicBlock::instr_iterator Succ = this;
897  ++Succ;
898  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
899  Succ->setFlag(BundledPred);
900}
901
902void MachineInstr::unbundleFromPred() {
903  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
904  clearFlag(BundledPred);
905  MachineBasicBlock::instr_iterator Pred = this;
906  --Pred;
907  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
908  Pred->clearFlag(BundledSucc);
909}
910
911void MachineInstr::unbundleFromSucc() {
912  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
913  clearFlag(BundledSucc);
914  MachineBasicBlock::instr_iterator Succ = this;
915  --Succ;
916  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
917  Succ->clearFlag(BundledPred);
918}
919
920bool MachineInstr::isStackAligningInlineAsm() const {
921  if (isInlineAsm()) {
922    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
923    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
924      return true;
925  }
926  return false;
927}
928
929InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
930  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
931  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
932  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
933}
934
935int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
936                                       unsigned *GroupNo) const {
937  assert(isInlineAsm() && "Expected an inline asm instruction");
938  assert(OpIdx < getNumOperands() && "OpIdx out of range");
939
940  // Ignore queries about the initial operands.
941  if (OpIdx < InlineAsm::MIOp_FirstOperand)
942    return -1;
943
944  unsigned Group = 0;
945  unsigned NumOps;
946  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
947       i += NumOps) {
948    const MachineOperand &FlagMO = getOperand(i);
949    // If we reach the implicit register operands, stop looking.
950    if (!FlagMO.isImm())
951      return -1;
952    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
953    if (i + NumOps > OpIdx) {
954      if (GroupNo)
955        *GroupNo = Group;
956      return i;
957    }
958    ++Group;
959  }
960  return -1;
961}
962
963const TargetRegisterClass*
964MachineInstr::getRegClassConstraint(unsigned OpIdx,
965                                    const TargetInstrInfo *TII,
966                                    const TargetRegisterInfo *TRI) const {
967  assert(getParent() && "Can't have an MBB reference here!");
968  assert(getParent()->getParent() && "Can't have an MF reference here!");
969  const MachineFunction &MF = *getParent()->getParent();
970
971  // Most opcodes have fixed constraints in their MCInstrDesc.
972  if (!isInlineAsm())
973    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
974
975  if (!getOperand(OpIdx).isReg())
976    return NULL;
977
978  // For tied uses on inline asm, get the constraint from the def.
979  unsigned DefIdx;
980  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
981    OpIdx = DefIdx;
982
983  // Inline asm stores register class constraints in the flag word.
984  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
985  if (FlagIdx < 0)
986    return NULL;
987
988  unsigned Flag = getOperand(FlagIdx).getImm();
989  unsigned RCID;
990  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
991    return TRI->getRegClass(RCID);
992
993  // Assume that all registers in a memory operand are pointers.
994  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
995    return TRI->getPointerRegClass(MF);
996
997  return NULL;
998}
999
1000/// getBundleSize - Return the number of instructions inside the MI bundle.
1001unsigned MachineInstr::getBundleSize() const {
1002  assert(isBundle() && "Expecting a bundle");
1003
1004  const MachineBasicBlock *MBB = getParent();
1005  MachineBasicBlock::const_instr_iterator I = *this, E = MBB->instr_end();
1006  unsigned Size = 0;
1007  while ((++I != E) && I->isInsideBundle()) {
1008    ++Size;
1009  }
1010  assert(Size > 1 && "Malformed bundle");
1011
1012  return Size;
1013}
1014
1015/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1016/// the specific register or -1 if it is not found. It further tightens
1017/// the search criteria to a use that kills the register if isKill is true.
1018int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1019                                          const TargetRegisterInfo *TRI) const {
1020  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1021    const MachineOperand &MO = getOperand(i);
1022    if (!MO.isReg() || !MO.isUse())
1023      continue;
1024    unsigned MOReg = MO.getReg();
1025    if (!MOReg)
1026      continue;
1027    if (MOReg == Reg ||
1028        (TRI &&
1029         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1030         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1031         TRI->isSubRegister(MOReg, Reg)))
1032      if (!isKill || MO.isKill())
1033        return i;
1034  }
1035  return -1;
1036}
1037
1038/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1039/// indicating if this instruction reads or writes Reg. This also considers
1040/// partial defines.
1041std::pair<bool,bool>
1042MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1043                                         SmallVectorImpl<unsigned> *Ops) const {
1044  bool PartDef = false; // Partial redefine.
1045  bool FullDef = false; // Full define.
1046  bool Use = false;
1047
1048  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1049    const MachineOperand &MO = getOperand(i);
1050    if (!MO.isReg() || MO.getReg() != Reg)
1051      continue;
1052    if (Ops)
1053      Ops->push_back(i);
1054    if (MO.isUse())
1055      Use |= !MO.isUndef();
1056    else if (MO.getSubReg() && !MO.isUndef())
1057      // A partial <def,undef> doesn't count as reading the register.
1058      PartDef = true;
1059    else
1060      FullDef = true;
1061  }
1062  // A partial redefine uses Reg unless there is also a full define.
1063  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1064}
1065
1066/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1067/// the specified register or -1 if it is not found. If isDead is true, defs
1068/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1069/// also checks if there is a def of a super-register.
1070int
1071MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1072                                        const TargetRegisterInfo *TRI) const {
1073  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1074  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1075    const MachineOperand &MO = getOperand(i);
1076    // Accept regmask operands when Overlap is set.
1077    // Ignore them when looking for a specific def operand (Overlap == false).
1078    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1079      return i;
1080    if (!MO.isReg() || !MO.isDef())
1081      continue;
1082    unsigned MOReg = MO.getReg();
1083    bool Found = (MOReg == Reg);
1084    if (!Found && TRI && isPhys &&
1085        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1086      if (Overlap)
1087        Found = TRI->regsOverlap(MOReg, Reg);
1088      else
1089        Found = TRI->isSubRegister(MOReg, Reg);
1090    }
1091    if (Found && (!isDead || MO.isDead()))
1092      return i;
1093  }
1094  return -1;
1095}
1096
1097/// findFirstPredOperandIdx() - Find the index of the first operand in the
1098/// operand list that is used to represent the predicate. It returns -1 if
1099/// none is found.
1100int MachineInstr::findFirstPredOperandIdx() const {
1101  // Don't call MCID.findFirstPredOperandIdx() because this variant
1102  // is sometimes called on an instruction that's not yet complete, and
1103  // so the number of operands is less than the MCID indicates. In
1104  // particular, the PTX target does this.
1105  const MCInstrDesc &MCID = getDesc();
1106  if (MCID.isPredicable()) {
1107    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1108      if (MCID.OpInfo[i].isPredicate())
1109        return i;
1110  }
1111
1112  return -1;
1113}
1114
1115// MachineOperand::TiedTo is 4 bits wide.
1116const unsigned TiedMax = 15;
1117
1118/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1119///
1120/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1121/// field. TiedTo can have these values:
1122///
1123/// 0:              Operand is not tied to anything.
1124/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1125/// TiedMax:        Tied to an operand >= TiedMax-1.
1126///
1127/// The tied def must be one of the first TiedMax operands on a normal
1128/// instruction. INLINEASM instructions allow more tied defs.
1129///
1130void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1131  MachineOperand &DefMO = getOperand(DefIdx);
1132  MachineOperand &UseMO = getOperand(UseIdx);
1133  assert(DefMO.isDef() && "DefIdx must be a def operand");
1134  assert(UseMO.isUse() && "UseIdx must be a use operand");
1135  assert(!DefMO.isTied() && "Def is already tied to another use");
1136  assert(!UseMO.isTied() && "Use is already tied to another def");
1137
1138  if (DefIdx < TiedMax)
1139    UseMO.TiedTo = DefIdx + 1;
1140  else {
1141    // Inline asm can use the group descriptors to find tied operands, but on
1142    // normal instruction, the tied def must be within the first TiedMax
1143    // operands.
1144    assert(isInlineAsm() && "DefIdx out of range");
1145    UseMO.TiedTo = TiedMax;
1146  }
1147
1148  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1149  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1150}
1151
1152/// Given the index of a tied register operand, find the operand it is tied to.
1153/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1154/// which must exist.
1155unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1156  const MachineOperand &MO = getOperand(OpIdx);
1157  assert(MO.isTied() && "Operand isn't tied");
1158
1159  // Normally TiedTo is in range.
1160  if (MO.TiedTo < TiedMax)
1161    return MO.TiedTo - 1;
1162
1163  // Uses on normal instructions can be out of range.
1164  if (!isInlineAsm()) {
1165    // Normal tied defs must be in the 0..TiedMax-1 range.
1166    if (MO.isUse())
1167      return TiedMax - 1;
1168    // MO is a def. Search for the tied use.
1169    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1170      const MachineOperand &UseMO = getOperand(i);
1171      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1172        return i;
1173    }
1174    llvm_unreachable("Can't find tied use");
1175  }
1176
1177  // Now deal with inline asm by parsing the operand group descriptor flags.
1178  // Find the beginning of each operand group.
1179  SmallVector<unsigned, 8> GroupIdx;
1180  unsigned OpIdxGroup = ~0u;
1181  unsigned NumOps;
1182  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1183       i += NumOps) {
1184    const MachineOperand &FlagMO = getOperand(i);
1185    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1186    unsigned CurGroup = GroupIdx.size();
1187    GroupIdx.push_back(i);
1188    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1189    // OpIdx belongs to this operand group.
1190    if (OpIdx > i && OpIdx < i + NumOps)
1191      OpIdxGroup = CurGroup;
1192    unsigned TiedGroup;
1193    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1194      continue;
1195    // Operands in this group are tied to operands in TiedGroup which must be
1196    // earlier. Find the number of operands between the two groups.
1197    unsigned Delta = i - GroupIdx[TiedGroup];
1198
1199    // OpIdx is a use tied to TiedGroup.
1200    if (OpIdxGroup == CurGroup)
1201      return OpIdx - Delta;
1202
1203    // OpIdx is a def tied to this use group.
1204    if (OpIdxGroup == TiedGroup)
1205      return OpIdx + Delta;
1206  }
1207  llvm_unreachable("Invalid tied operand on inline asm");
1208}
1209
1210/// clearKillInfo - Clears kill flags on all operands.
1211///
1212void MachineInstr::clearKillInfo() {
1213  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1214    MachineOperand &MO = getOperand(i);
1215    if (MO.isReg() && MO.isUse())
1216      MO.setIsKill(false);
1217  }
1218}
1219
1220void MachineInstr::substituteRegister(unsigned FromReg,
1221                                      unsigned ToReg,
1222                                      unsigned SubIdx,
1223                                      const TargetRegisterInfo &RegInfo) {
1224  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1225    if (SubIdx)
1226      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1227    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1228      MachineOperand &MO = getOperand(i);
1229      if (!MO.isReg() || MO.getReg() != FromReg)
1230        continue;
1231      MO.substPhysReg(ToReg, RegInfo);
1232    }
1233  } else {
1234    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1235      MachineOperand &MO = getOperand(i);
1236      if (!MO.isReg() || MO.getReg() != FromReg)
1237        continue;
1238      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1239    }
1240  }
1241}
1242
1243/// isSafeToMove - Return true if it is safe to move this instruction. If
1244/// SawStore is set to true, it means that there is a store (or call) between
1245/// the instruction's location and its intended destination.
1246bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1247                                AliasAnalysis *AA,
1248                                bool &SawStore) const {
1249  // Ignore stuff that we obviously can't move.
1250  //
1251  // Treat volatile loads as stores. This is not strictly necessary for
1252  // volatiles, but it is required for atomic loads. It is not allowed to move
1253  // a load across an atomic load with Ordering > Monotonic.
1254  if (mayStore() || isCall() ||
1255      (mayLoad() && hasOrderedMemoryRef())) {
1256    SawStore = true;
1257    return false;
1258  }
1259
1260  if (isLabel() || isDebugValue() ||
1261      isTerminator() || hasUnmodeledSideEffects())
1262    return false;
1263
1264  // See if this instruction does a load.  If so, we have to guarantee that the
1265  // loaded value doesn't change between the load and the its intended
1266  // destination. The check for isInvariantLoad gives the targe the chance to
1267  // classify the load as always returning a constant, e.g. a constant pool
1268  // load.
1269  if (mayLoad() && !isInvariantLoad(AA))
1270    // Otherwise, this is a real load.  If there is a store between the load and
1271    // end of block, we can't move it.
1272    return !SawStore;
1273
1274  return true;
1275}
1276
1277/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1278/// instruction which defined the specified register instead of copying it.
1279bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1280                                 AliasAnalysis *AA,
1281                                 unsigned DstReg) const {
1282  bool SawStore = false;
1283  if (!TII->isTriviallyReMaterializable(this, AA) ||
1284      !isSafeToMove(TII, AA, SawStore))
1285    return false;
1286  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1287    const MachineOperand &MO = getOperand(i);
1288    if (!MO.isReg())
1289      continue;
1290    // FIXME: For now, do not remat any instruction with register operands.
1291    // Later on, we can loosen the restriction is the register operands have
1292    // not been modified between the def and use. Note, this is different from
1293    // MachineSink because the code is no longer in two-address form (at least
1294    // partially).
1295    if (MO.isUse())
1296      return false;
1297    else if (!MO.isDead() && MO.getReg() != DstReg)
1298      return false;
1299  }
1300  return true;
1301}
1302
1303/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1304/// or volatile memory reference, or if the information describing the memory
1305/// reference is not available. Return false if it is known to have no ordered
1306/// memory references.
1307bool MachineInstr::hasOrderedMemoryRef() const {
1308  // An instruction known never to access memory won't have a volatile access.
1309  if (!mayStore() &&
1310      !mayLoad() &&
1311      !isCall() &&
1312      !hasUnmodeledSideEffects())
1313    return false;
1314
1315  // Otherwise, if the instruction has no memory reference information,
1316  // conservatively assume it wasn't preserved.
1317  if (memoperands_empty())
1318    return true;
1319
1320  // Check the memory reference information for ordered references.
1321  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1322    if (!(*I)->isUnordered())
1323      return true;
1324
1325  return false;
1326}
1327
1328/// isInvariantLoad - Return true if this instruction is loading from a
1329/// location whose value is invariant across the function.  For example,
1330/// loading a value from the constant pool or from the argument area
1331/// of a function if it does not change.  This should only return true of
1332/// *all* loads the instruction does are invariant (if it does multiple loads).
1333bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1334  // If the instruction doesn't load at all, it isn't an invariant load.
1335  if (!mayLoad())
1336    return false;
1337
1338  // If the instruction has lost its memoperands, conservatively assume that
1339  // it may not be an invariant load.
1340  if (memoperands_empty())
1341    return false;
1342
1343  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1344
1345  for (mmo_iterator I = memoperands_begin(),
1346       E = memoperands_end(); I != E; ++I) {
1347    if ((*I)->isVolatile()) return false;
1348    if ((*I)->isStore()) return false;
1349    if ((*I)->isInvariant()) return true;
1350
1351    if (const Value *V = (*I)->getValue()) {
1352      // A load from a constant PseudoSourceValue is invariant.
1353      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1354        if (PSV->isConstant(MFI))
1355          continue;
1356      // If we have an AliasAnalysis, ask it whether the memory is constant.
1357      if (AA && AA->pointsToConstantMemory(
1358                      AliasAnalysis::Location(V, (*I)->getSize(),
1359                                              (*I)->getTBAAInfo())))
1360        continue;
1361    }
1362
1363    // Otherwise assume conservatively.
1364    return false;
1365  }
1366
1367  // Everything checks out.
1368  return true;
1369}
1370
1371/// isConstantValuePHI - If the specified instruction is a PHI that always
1372/// merges together the same virtual register, return the register, otherwise
1373/// return 0.
1374unsigned MachineInstr::isConstantValuePHI() const {
1375  if (!isPHI())
1376    return 0;
1377  assert(getNumOperands() >= 3 &&
1378         "It's illegal to have a PHI without source operands");
1379
1380  unsigned Reg = getOperand(1).getReg();
1381  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1382    if (getOperand(i).getReg() != Reg)
1383      return 0;
1384  return Reg;
1385}
1386
1387bool MachineInstr::hasUnmodeledSideEffects() const {
1388  if (hasProperty(MCID::UnmodeledSideEffects))
1389    return true;
1390  if (isInlineAsm()) {
1391    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1392    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1393      return true;
1394  }
1395
1396  return false;
1397}
1398
1399/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1400///
1401bool MachineInstr::allDefsAreDead() const {
1402  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1403    const MachineOperand &MO = getOperand(i);
1404    if (!MO.isReg() || MO.isUse())
1405      continue;
1406    if (!MO.isDead())
1407      return false;
1408  }
1409  return true;
1410}
1411
1412/// copyImplicitOps - Copy implicit register operands from specified
1413/// instruction to this instruction.
1414void MachineInstr::copyImplicitOps(MachineFunction &MF,
1415                                   const MachineInstr *MI) {
1416  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1417       i != e; ++i) {
1418    const MachineOperand &MO = MI->getOperand(i);
1419    if (MO.isReg() && MO.isImplicit())
1420      addOperand(MF, MO);
1421  }
1422}
1423
1424void MachineInstr::dump() const {
1425#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1426  dbgs() << "  " << *this;
1427#endif
1428}
1429
1430static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1431                         raw_ostream &CommentOS) {
1432  const LLVMContext &Ctx = MF->getFunction()->getContext();
1433  if (!DL.isUnknown()) {          // Print source line info.
1434    DIScope Scope(DL.getScope(Ctx));
1435    // Omit the directory, because it's likely to be long and uninteresting.
1436    if (Scope.Verify())
1437      CommentOS << Scope.getFilename();
1438    else
1439      CommentOS << "<unknown>";
1440    CommentOS << ':' << DL.getLine();
1441    if (DL.getCol() != 0)
1442      CommentOS << ':' << DL.getCol();
1443    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1444    if (!InlinedAtDL.isUnknown()) {
1445      CommentOS << " @[ ";
1446      printDebugLoc(InlinedAtDL, MF, CommentOS);
1447      CommentOS << " ]";
1448    }
1449  }
1450}
1451
1452void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1453  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1454  const MachineFunction *MF = 0;
1455  const MachineRegisterInfo *MRI = 0;
1456  if (const MachineBasicBlock *MBB = getParent()) {
1457    MF = MBB->getParent();
1458    if (!TM && MF)
1459      TM = &MF->getTarget();
1460    if (MF)
1461      MRI = &MF->getRegInfo();
1462  }
1463
1464  // Save a list of virtual registers.
1465  SmallVector<unsigned, 8> VirtRegs;
1466
1467  // Print explicitly defined operands on the left of an assignment syntax.
1468  unsigned StartOp = 0, e = getNumOperands();
1469  for (; StartOp < e && getOperand(StartOp).isReg() &&
1470         getOperand(StartOp).isDef() &&
1471         !getOperand(StartOp).isImplicit();
1472       ++StartOp) {
1473    if (StartOp != 0) OS << ", ";
1474    getOperand(StartOp).print(OS, TM);
1475    unsigned Reg = getOperand(StartOp).getReg();
1476    if (TargetRegisterInfo::isVirtualRegister(Reg))
1477      VirtRegs.push_back(Reg);
1478  }
1479
1480  if (StartOp != 0)
1481    OS << " = ";
1482
1483  // Print the opcode name.
1484  if (TM && TM->getInstrInfo())
1485    OS << TM->getInstrInfo()->getName(getOpcode());
1486  else
1487    OS << "UNKNOWN";
1488
1489  // Print the rest of the operands.
1490  bool OmittedAnyCallClobbers = false;
1491  bool FirstOp = true;
1492  unsigned AsmDescOp = ~0u;
1493  unsigned AsmOpCount = 0;
1494
1495  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1496    // Print asm string.
1497    OS << " ";
1498    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1499
1500    // Print HasSideEffects, IsAlignStack
1501    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1502    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1503      OS << " [sideeffect]";
1504    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1505      OS << " [alignstack]";
1506    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1507      OS << " [attdialect]";
1508    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1509      OS << " [inteldialect]";
1510
1511    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1512    FirstOp = false;
1513  }
1514
1515
1516  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1517    const MachineOperand &MO = getOperand(i);
1518
1519    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1520      VirtRegs.push_back(MO.getReg());
1521
1522    // Omit call-clobbered registers which aren't used anywhere. This makes
1523    // call instructions much less noisy on targets where calls clobber lots
1524    // of registers. Don't rely on MO.isDead() because we may be called before
1525    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1526    if (MF && isCall() &&
1527        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1528      unsigned Reg = MO.getReg();
1529      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1530        const MachineRegisterInfo &MRI = MF->getRegInfo();
1531        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1532          bool HasAliasLive = false;
1533          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1534               AI.isValid(); ++AI) {
1535            unsigned AliasReg = *AI;
1536            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1537              HasAliasLive = true;
1538              break;
1539            }
1540          }
1541          if (!HasAliasLive) {
1542            OmittedAnyCallClobbers = true;
1543            continue;
1544          }
1545        }
1546      }
1547    }
1548
1549    if (FirstOp) FirstOp = false; else OS << ",";
1550    OS << " ";
1551    if (i < getDesc().NumOperands) {
1552      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1553      if (MCOI.isPredicate())
1554        OS << "pred:";
1555      if (MCOI.isOptionalDef())
1556        OS << "opt:";
1557    }
1558    if (isDebugValue() && MO.isMetadata()) {
1559      // Pretty print DBG_VALUE instructions.
1560      const MDNode *MD = MO.getMetadata();
1561      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1562        OS << "!\"" << MDS->getString() << '\"';
1563      else
1564        MO.print(OS, TM);
1565    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1566      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1567    } else if (i == AsmDescOp && MO.isImm()) {
1568      // Pretty print the inline asm operand descriptor.
1569      OS << '$' << AsmOpCount++;
1570      unsigned Flag = MO.getImm();
1571      switch (InlineAsm::getKind(Flag)) {
1572      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1573      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1574      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1575      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1576      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1577      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1578      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1579      }
1580
1581      unsigned RCID = 0;
1582      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1583        if (TM)
1584          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1585        else
1586          OS << ":RC" << RCID;
1587      }
1588
1589      unsigned TiedTo = 0;
1590      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1591        OS << " tiedto:$" << TiedTo;
1592
1593      OS << ']';
1594
1595      // Compute the index of the next operand descriptor.
1596      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1597    } else
1598      MO.print(OS, TM);
1599  }
1600
1601  // Briefly indicate whether any call clobbers were omitted.
1602  if (OmittedAnyCallClobbers) {
1603    if (!FirstOp) OS << ",";
1604    OS << " ...";
1605  }
1606
1607  bool HaveSemi = false;
1608  if (Flags) {
1609    if (!HaveSemi) OS << ";"; HaveSemi = true;
1610    OS << " flags: ";
1611
1612    if (Flags & FrameSetup)
1613      OS << "FrameSetup";
1614  }
1615
1616  if (!memoperands_empty()) {
1617    if (!HaveSemi) OS << ";"; HaveSemi = true;
1618
1619    OS << " mem:";
1620    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1621         i != e; ++i) {
1622      OS << **i;
1623      if (llvm::next(i) != e)
1624        OS << " ";
1625    }
1626  }
1627
1628  // Print the regclass of any virtual registers encountered.
1629  if (MRI && !VirtRegs.empty()) {
1630    if (!HaveSemi) OS << ";"; HaveSemi = true;
1631    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1632      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1633      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1634      for (unsigned j = i+1; j != VirtRegs.size();) {
1635        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1636          ++j;
1637          continue;
1638        }
1639        if (VirtRegs[i] != VirtRegs[j])
1640          OS << "," << PrintReg(VirtRegs[j]);
1641        VirtRegs.erase(VirtRegs.begin()+j);
1642      }
1643    }
1644  }
1645
1646  // Print debug location information.
1647  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1648    if (!HaveSemi) OS << ";"; HaveSemi = true;
1649    DIVariable DV(getOperand(e - 1).getMetadata());
1650    OS << " line no:" <<  DV.getLineNumber();
1651    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1652      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1653      if (!InlinedAtDL.isUnknown()) {
1654        OS << " inlined @[ ";
1655        printDebugLoc(InlinedAtDL, MF, OS);
1656        OS << " ]";
1657      }
1658    }
1659  } else if (!debugLoc.isUnknown() && MF) {
1660    if (!HaveSemi) OS << ";"; HaveSemi = true;
1661    OS << " dbg:";
1662    printDebugLoc(debugLoc, MF, OS);
1663  }
1664
1665  OS << '\n';
1666}
1667
1668bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1669                                     const TargetRegisterInfo *RegInfo,
1670                                     bool AddIfNotFound) {
1671  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1672  bool hasAliases = isPhysReg &&
1673    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1674  bool Found = false;
1675  SmallVector<unsigned,4> DeadOps;
1676  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1677    MachineOperand &MO = getOperand(i);
1678    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1679      continue;
1680    unsigned Reg = MO.getReg();
1681    if (!Reg)
1682      continue;
1683
1684    if (Reg == IncomingReg) {
1685      if (!Found) {
1686        if (MO.isKill())
1687          // The register is already marked kill.
1688          return true;
1689        if (isPhysReg && isRegTiedToDefOperand(i))
1690          // Two-address uses of physregs must not be marked kill.
1691          return true;
1692        MO.setIsKill();
1693        Found = true;
1694      }
1695    } else if (hasAliases && MO.isKill() &&
1696               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1697      // A super-register kill already exists.
1698      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1699        return true;
1700      if (RegInfo->isSubRegister(IncomingReg, Reg))
1701        DeadOps.push_back(i);
1702    }
1703  }
1704
1705  // Trim unneeded kill operands.
1706  while (!DeadOps.empty()) {
1707    unsigned OpIdx = DeadOps.back();
1708    if (getOperand(OpIdx).isImplicit())
1709      RemoveOperand(OpIdx);
1710    else
1711      getOperand(OpIdx).setIsKill(false);
1712    DeadOps.pop_back();
1713  }
1714
1715  // If not found, this means an alias of one of the operands is killed. Add a
1716  // new implicit operand if required.
1717  if (!Found && AddIfNotFound) {
1718    addOperand(MachineOperand::CreateReg(IncomingReg,
1719                                         false /*IsDef*/,
1720                                         true  /*IsImp*/,
1721                                         true  /*IsKill*/));
1722    return true;
1723  }
1724  return Found;
1725}
1726
1727void MachineInstr::clearRegisterKills(unsigned Reg,
1728                                      const TargetRegisterInfo *RegInfo) {
1729  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1730    RegInfo = 0;
1731  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1732    MachineOperand &MO = getOperand(i);
1733    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1734      continue;
1735    unsigned OpReg = MO.getReg();
1736    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1737      MO.setIsKill(false);
1738  }
1739}
1740
1741bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1742                                   const TargetRegisterInfo *RegInfo,
1743                                   bool AddIfNotFound) {
1744  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1745  bool hasAliases = isPhysReg &&
1746    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1747  bool Found = false;
1748  SmallVector<unsigned,4> DeadOps;
1749  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1750    MachineOperand &MO = getOperand(i);
1751    if (!MO.isReg() || !MO.isDef())
1752      continue;
1753    unsigned Reg = MO.getReg();
1754    if (!Reg)
1755      continue;
1756
1757    if (Reg == IncomingReg) {
1758      MO.setIsDead();
1759      Found = true;
1760    } else if (hasAliases && MO.isDead() &&
1761               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1762      // There exists a super-register that's marked dead.
1763      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1764        return true;
1765      if (RegInfo->isSubRegister(IncomingReg, Reg))
1766        DeadOps.push_back(i);
1767    }
1768  }
1769
1770  // Trim unneeded dead operands.
1771  while (!DeadOps.empty()) {
1772    unsigned OpIdx = DeadOps.back();
1773    if (getOperand(OpIdx).isImplicit())
1774      RemoveOperand(OpIdx);
1775    else
1776      getOperand(OpIdx).setIsDead(false);
1777    DeadOps.pop_back();
1778  }
1779
1780  // If not found, this means an alias of one of the operands is dead. Add a
1781  // new implicit operand if required.
1782  if (Found || !AddIfNotFound)
1783    return Found;
1784
1785  addOperand(MachineOperand::CreateReg(IncomingReg,
1786                                       true  /*IsDef*/,
1787                                       true  /*IsImp*/,
1788                                       false /*IsKill*/,
1789                                       true  /*IsDead*/));
1790  return true;
1791}
1792
1793void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1794                                      const TargetRegisterInfo *RegInfo) {
1795  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1796    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1797    if (MO)
1798      return;
1799  } else {
1800    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1801      const MachineOperand &MO = getOperand(i);
1802      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1803          MO.getSubReg() == 0)
1804        return;
1805    }
1806  }
1807  addOperand(MachineOperand::CreateReg(IncomingReg,
1808                                       true  /*IsDef*/,
1809                                       true  /*IsImp*/));
1810}
1811
1812void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1813                                         const TargetRegisterInfo &TRI) {
1814  bool HasRegMask = false;
1815  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1816    MachineOperand &MO = getOperand(i);
1817    if (MO.isRegMask()) {
1818      HasRegMask = true;
1819      continue;
1820    }
1821    if (!MO.isReg() || !MO.isDef()) continue;
1822    unsigned Reg = MO.getReg();
1823    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1824    bool Dead = true;
1825    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1826         I != E; ++I)
1827      if (TRI.regsOverlap(*I, Reg)) {
1828        Dead = false;
1829        break;
1830      }
1831    // If there are no uses, including partial uses, the def is dead.
1832    if (Dead) MO.setIsDead();
1833  }
1834
1835  // This is a call with a register mask operand.
1836  // Mask clobbers are always dead, so add defs for the non-dead defines.
1837  if (HasRegMask)
1838    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1839         I != E; ++I)
1840      addRegisterDefined(*I, &TRI);
1841}
1842
1843unsigned
1844MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1845  // Build up a buffer of hash code components.
1846  SmallVector<size_t, 8> HashComponents;
1847  HashComponents.reserve(MI->getNumOperands() + 1);
1848  HashComponents.push_back(MI->getOpcode());
1849  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1850    const MachineOperand &MO = MI->getOperand(i);
1851    if (MO.isReg() && MO.isDef() &&
1852        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1853      continue;  // Skip virtual register defs.
1854
1855    HashComponents.push_back(hash_value(MO));
1856  }
1857  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1858}
1859
1860void MachineInstr::emitError(StringRef Msg) const {
1861  // Find the source location cookie.
1862  unsigned LocCookie = 0;
1863  const MDNode *LocMD = 0;
1864  for (unsigned i = getNumOperands(); i != 0; --i) {
1865    if (getOperand(i-1).isMetadata() &&
1866        (LocMD = getOperand(i-1).getMetadata()) &&
1867        LocMD->getNumOperands() != 0) {
1868      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1869        LocCookie = CI->getZExtValue();
1870        break;
1871      }
1872    }
1873  }
1874
1875  if (const MachineBasicBlock *MBB = getParent())
1876    if (const MachineFunction *MF = MBB->getParent())
1877      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1878  report_fatal_error(Msg);
1879}
1880