MachineInstr.cpp revision 87802d52e1e873592c6fe39827081b492bd318cc 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/DebugInfo.h"
17#include "llvm/Function.h"
18#include "llvm/InlineAsm.h"
19#include "llvm/LLVMContext.h"
20#include "llvm/Metadata.h"
21#include "llvm/Module.h"
22#include "llvm/Type.h"
23#include "llvm/Value.h"
24#include "llvm/Assembly/Writer.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/PseudoSourceValue.h"
31#include "llvm/MC/MCInstrDesc.h"
32#include "llvm/MC/MCSymbol.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetRegisterInfo.h"
36#include "llvm/Analysis/AliasAnalysis.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/LeakDetector.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/FoldingSet.h"
43#include "llvm/ADT/Hashing.h"
44using namespace llvm;
45
46//===----------------------------------------------------------------------===//
47// MachineOperand Implementation
48//===----------------------------------------------------------------------===//
49
50void MachineOperand::setReg(unsigned Reg) {
51  if (getReg() == Reg) return; // No change.
52
53  // Otherwise, we have to change the register.  If this operand is embedded
54  // into a machine function, we need to update the old and new register's
55  // use/def lists.
56  if (MachineInstr *MI = getParent())
57    if (MachineBasicBlock *MBB = MI->getParent())
58      if (MachineFunction *MF = MBB->getParent()) {
59        MachineRegisterInfo &MRI = MF->getRegInfo();
60        MRI.removeRegOperandFromUseList(this);
61        SmallContents.RegNo = Reg;
62        MRI.addRegOperandToUseList(this);
63        return;
64      }
65
66  // Otherwise, just change the register, no problem.  :)
67  SmallContents.RegNo = Reg;
68}
69
70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71                                  const TargetRegisterInfo &TRI) {
72  assert(TargetRegisterInfo::isVirtualRegister(Reg));
73  if (SubIdx && getSubReg())
74    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75  setReg(Reg);
76  if (SubIdx)
77    setSubReg(SubIdx);
78}
79
80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82  if (getSubReg()) {
83    Reg = TRI.getSubReg(Reg, getSubReg());
84    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85    // That won't happen in legal code.
86    setSubReg(0);
87  }
88  setReg(Reg);
89}
90
91/// Change a def to a use, or a use to a def.
92void MachineOperand::setIsDef(bool Val) {
93  assert(isReg() && "Wrong MachineOperand accessor");
94  assert((!Val || !isDebug()) && "Marking a debug operation as def");
95  if (IsDef == Val)
96    return;
97  // MRI may keep uses and defs in different list positions.
98  if (MachineInstr *MI = getParent())
99    if (MachineBasicBlock *MBB = MI->getParent())
100      if (MachineFunction *MF = MBB->getParent()) {
101        MachineRegisterInfo &MRI = MF->getRegInfo();
102        MRI.removeRegOperandFromUseList(this);
103        IsDef = Val;
104        MRI.addRegOperandToUseList(this);
105        return;
106      }
107  IsDef = Val;
108}
109
110/// ChangeToImmediate - Replace this operand with a new immediate operand of
111/// the specified value.  If an operand is known to be an immediate already,
112/// the setImm method should be used.
113void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115  // If this operand is currently a register operand, and if this is in a
116  // function, deregister the operand from the register's use/def list.
117  if (isReg() && isOnRegUseList())
118    if (MachineInstr *MI = getParent())
119      if (MachineBasicBlock *MBB = MI->getParent())
120        if (MachineFunction *MF = MBB->getParent())
121          MF->getRegInfo().removeRegOperandFromUseList(this);
122
123  OpKind = MO_Immediate;
124  Contents.ImmVal = ImmVal;
125}
126
127/// ChangeToRegister - Replace this operand with a new register operand of
128/// the specified value.  If an operand is known to be an register already,
129/// the setReg method should be used.
130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131                                      bool isKill, bool isDead, bool isUndef,
132                                      bool isDebug) {
133  MachineRegisterInfo *RegInfo = 0;
134  if (MachineInstr *MI = getParent())
135    if (MachineBasicBlock *MBB = MI->getParent())
136      if (MachineFunction *MF = MBB->getParent())
137        RegInfo = &MF->getRegInfo();
138  // If this operand is already a register operand, remove it from the
139  // register's use/def lists.
140  bool WasReg = isReg();
141  if (RegInfo && WasReg)
142    RegInfo->removeRegOperandFromUseList(this);
143
144  // Change this to a register and set the reg#.
145  OpKind = MO_Register;
146  SmallContents.RegNo = Reg;
147  SubReg = 0;
148  IsDef = isDef;
149  IsImp = isImp;
150  IsKill = isKill;
151  IsDead = isDead;
152  IsUndef = isUndef;
153  IsInternalRead = false;
154  IsEarlyClobber = false;
155  IsDebug = isDebug;
156  // Ensure isOnRegUseList() returns false.
157  Contents.Reg.Prev = 0;
158  // Preserve the tie when the operand was already a register.
159  if (!WasReg)
160    TiedTo = 0;
161
162  // If this operand is embedded in a function, add the operand to the
163  // register's use/def list.
164  if (RegInfo)
165    RegInfo->addRegOperandToUseList(this);
166}
167
168/// isIdenticalTo - Return true if this operand is identical to the specified
169/// operand. Note that this should stay in sync with the hash_value overload
170/// below.
171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172  if (getType() != Other.getType() ||
173      getTargetFlags() != Other.getTargetFlags())
174    return false;
175
176  switch (getType()) {
177  case MachineOperand::MO_Register:
178    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179           getSubReg() == Other.getSubReg();
180  case MachineOperand::MO_Immediate:
181    return getImm() == Other.getImm();
182  case MachineOperand::MO_CImmediate:
183    return getCImm() == Other.getCImm();
184  case MachineOperand::MO_FPImmediate:
185    return getFPImm() == Other.getFPImm();
186  case MachineOperand::MO_MachineBasicBlock:
187    return getMBB() == Other.getMBB();
188  case MachineOperand::MO_FrameIndex:
189    return getIndex() == Other.getIndex();
190  case MachineOperand::MO_ConstantPoolIndex:
191  case MachineOperand::MO_TargetIndex:
192    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193  case MachineOperand::MO_JumpTableIndex:
194    return getIndex() == Other.getIndex();
195  case MachineOperand::MO_GlobalAddress:
196    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197  case MachineOperand::MO_ExternalSymbol:
198    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199           getOffset() == Other.getOffset();
200  case MachineOperand::MO_BlockAddress:
201    return getBlockAddress() == Other.getBlockAddress() &&
202           getOffset() == Other.getOffset();
203  case MO_RegisterMask:
204    return getRegMask() == Other.getRegMask();
205  case MachineOperand::MO_MCSymbol:
206    return getMCSymbol() == Other.getMCSymbol();
207  case MachineOperand::MO_Metadata:
208    return getMetadata() == Other.getMetadata();
209  }
210  llvm_unreachable("Invalid machine operand type");
211}
212
213// Note: this must stay exactly in sync with isIdenticalTo above.
214hash_code llvm::hash_value(const MachineOperand &MO) {
215  switch (MO.getType()) {
216  case MachineOperand::MO_Register:
217    // Register operands don't have target flags.
218    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
219  case MachineOperand::MO_Immediate:
220    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
221  case MachineOperand::MO_CImmediate:
222    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
223  case MachineOperand::MO_FPImmediate:
224    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
225  case MachineOperand::MO_MachineBasicBlock:
226    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
227  case MachineOperand::MO_FrameIndex:
228    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
229  case MachineOperand::MO_ConstantPoolIndex:
230  case MachineOperand::MO_TargetIndex:
231    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
232                        MO.getOffset());
233  case MachineOperand::MO_JumpTableIndex:
234    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
235  case MachineOperand::MO_ExternalSymbol:
236    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
237                        MO.getSymbolName());
238  case MachineOperand::MO_GlobalAddress:
239    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
240                        MO.getOffset());
241  case MachineOperand::MO_BlockAddress:
242    return hash_combine(MO.getType(), MO.getTargetFlags(),
243                        MO.getBlockAddress(), MO.getOffset());
244  case MachineOperand::MO_RegisterMask:
245    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
246  case MachineOperand::MO_Metadata:
247    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
248  case MachineOperand::MO_MCSymbol:
249    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
250  }
251  llvm_unreachable("Invalid machine operand type");
252}
253
254/// print - Print the specified machine operand.
255///
256void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
257  // If the instruction is embedded into a basic block, we can find the
258  // target info for the instruction.
259  if (!TM)
260    if (const MachineInstr *MI = getParent())
261      if (const MachineBasicBlock *MBB = MI->getParent())
262        if (const MachineFunction *MF = MBB->getParent())
263          TM = &MF->getTarget();
264  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
265
266  switch (getType()) {
267  case MachineOperand::MO_Register:
268    OS << PrintReg(getReg(), TRI, getSubReg());
269
270    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
271        isInternalRead() || isEarlyClobber() || isTied()) {
272      OS << '<';
273      bool NeedComma = false;
274      if (isDef()) {
275        if (NeedComma) OS << ',';
276        if (isEarlyClobber())
277          OS << "earlyclobber,";
278        if (isImplicit())
279          OS << "imp-";
280        OS << "def";
281        NeedComma = true;
282        // <def,read-undef> only makes sense when getSubReg() is set.
283        // Don't clutter the output otherwise.
284        if (isUndef() && getSubReg())
285          OS << ",read-undef";
286      } else if (isImplicit()) {
287          OS << "imp-use";
288          NeedComma = true;
289      }
290
291      if (isKill()) {
292        if (NeedComma) OS << ',';
293        OS << "kill";
294        NeedComma = true;
295      }
296      if (isDead()) {
297        if (NeedComma) OS << ',';
298        OS << "dead";
299        NeedComma = true;
300      }
301      if (isUndef() && isUse()) {
302        if (NeedComma) OS << ',';
303        OS << "undef";
304        NeedComma = true;
305      }
306      if (isInternalRead()) {
307        if (NeedComma) OS << ',';
308        OS << "internal";
309        NeedComma = true;
310      }
311      if (isTied()) {
312        if (NeedComma) OS << ',';
313        OS << "tied";
314        if (TiedTo != 15)
315          OS << unsigned(TiedTo - 1);
316        NeedComma = true;
317      }
318      OS << '>';
319    }
320    break;
321  case MachineOperand::MO_Immediate:
322    OS << getImm();
323    break;
324  case MachineOperand::MO_CImmediate:
325    getCImm()->getValue().print(OS, false);
326    break;
327  case MachineOperand::MO_FPImmediate:
328    if (getFPImm()->getType()->isFloatTy())
329      OS << getFPImm()->getValueAPF().convertToFloat();
330    else
331      OS << getFPImm()->getValueAPF().convertToDouble();
332    break;
333  case MachineOperand::MO_MachineBasicBlock:
334    OS << "<BB#" << getMBB()->getNumber() << ">";
335    break;
336  case MachineOperand::MO_FrameIndex:
337    OS << "<fi#" << getIndex() << '>';
338    break;
339  case MachineOperand::MO_ConstantPoolIndex:
340    OS << "<cp#" << getIndex();
341    if (getOffset()) OS << "+" << getOffset();
342    OS << '>';
343    break;
344  case MachineOperand::MO_TargetIndex:
345    OS << "<ti#" << getIndex();
346    if (getOffset()) OS << "+" << getOffset();
347    OS << '>';
348    break;
349  case MachineOperand::MO_JumpTableIndex:
350    OS << "<jt#" << getIndex() << '>';
351    break;
352  case MachineOperand::MO_GlobalAddress:
353    OS << "<ga:";
354    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
355    if (getOffset()) OS << "+" << getOffset();
356    OS << '>';
357    break;
358  case MachineOperand::MO_ExternalSymbol:
359    OS << "<es:" << getSymbolName();
360    if (getOffset()) OS << "+" << getOffset();
361    OS << '>';
362    break;
363  case MachineOperand::MO_BlockAddress:
364    OS << '<';
365    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
366    if (getOffset()) OS << "+" << getOffset();
367    OS << '>';
368    break;
369  case MachineOperand::MO_RegisterMask:
370    OS << "<regmask>";
371    break;
372  case MachineOperand::MO_Metadata:
373    OS << '<';
374    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
375    OS << '>';
376    break;
377  case MachineOperand::MO_MCSymbol:
378    OS << "<MCSym=" << *getMCSymbol() << '>';
379    break;
380  }
381
382  if (unsigned TF = getTargetFlags())
383    OS << "[TF=" << TF << ']';
384}
385
386//===----------------------------------------------------------------------===//
387// MachineMemOperand Implementation
388//===----------------------------------------------------------------------===//
389
390/// getAddrSpace - Return the LLVM IR address space number that this pointer
391/// points into.
392unsigned MachinePointerInfo::getAddrSpace() const {
393  if (V == 0) return 0;
394  return cast<PointerType>(V->getType())->getAddressSpace();
395}
396
397/// getConstantPool - Return a MachinePointerInfo record that refers to the
398/// constant pool.
399MachinePointerInfo MachinePointerInfo::getConstantPool() {
400  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
401}
402
403/// getFixedStack - Return a MachinePointerInfo record that refers to the
404/// the specified FrameIndex.
405MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
406  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
407}
408
409MachinePointerInfo MachinePointerInfo::getJumpTable() {
410  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
411}
412
413MachinePointerInfo MachinePointerInfo::getGOT() {
414  return MachinePointerInfo(PseudoSourceValue::getGOT());
415}
416
417MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
418  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
419}
420
421MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
422                                     uint64_t s, unsigned int a,
423                                     const MDNode *TBAAInfo,
424                                     const MDNode *Ranges)
425  : PtrInfo(ptrinfo), Size(s),
426    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
427    TBAAInfo(TBAAInfo), Ranges(Ranges) {
428  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
429         "invalid pointer value");
430  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
431  assert((isLoad() || isStore()) && "Not a load/store!");
432}
433
434/// Profile - Gather unique data for the object.
435///
436void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
437  ID.AddInteger(getOffset());
438  ID.AddInteger(Size);
439  ID.AddPointer(getValue());
440  ID.AddInteger(Flags);
441}
442
443void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
444  // The Value and Offset may differ due to CSE. But the flags and size
445  // should be the same.
446  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
447  assert(MMO->getSize() == getSize() && "Size mismatch!");
448
449  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
450    // Update the alignment value.
451    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
452      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
453    // Also update the base and offset, because the new alignment may
454    // not be applicable with the old ones.
455    PtrInfo = MMO->PtrInfo;
456  }
457}
458
459/// getAlignment - Return the minimum known alignment in bytes of the
460/// actual memory reference.
461uint64_t MachineMemOperand::getAlignment() const {
462  return MinAlign(getBaseAlignment(), getOffset());
463}
464
465raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
466  assert((MMO.isLoad() || MMO.isStore()) &&
467         "SV has to be a load, store or both.");
468
469  if (MMO.isVolatile())
470    OS << "Volatile ";
471
472  if (MMO.isLoad())
473    OS << "LD";
474  if (MMO.isStore())
475    OS << "ST";
476  OS << MMO.getSize();
477
478  // Print the address information.
479  OS << "[";
480  if (!MMO.getValue())
481    OS << "<unknown>";
482  else
483    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
484
485  // If the alignment of the memory reference itself differs from the alignment
486  // of the base pointer, print the base alignment explicitly, next to the base
487  // pointer.
488  if (MMO.getBaseAlignment() != MMO.getAlignment())
489    OS << "(align=" << MMO.getBaseAlignment() << ")";
490
491  if (MMO.getOffset() != 0)
492    OS << "+" << MMO.getOffset();
493  OS << "]";
494
495  // Print the alignment of the reference.
496  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
497      MMO.getBaseAlignment() != MMO.getSize())
498    OS << "(align=" << MMO.getAlignment() << ")";
499
500  // Print TBAA info.
501  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
502    OS << "(tbaa=";
503    if (TBAAInfo->getNumOperands() > 0)
504      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
505    else
506      OS << "<unknown>";
507    OS << ")";
508  }
509
510  // Print nontemporal info.
511  if (MMO.isNonTemporal())
512    OS << "(nontemporal)";
513
514  return OS;
515}
516
517//===----------------------------------------------------------------------===//
518// MachineInstr Implementation
519//===----------------------------------------------------------------------===//
520
521/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
522/// MCID NULL and no operands.
523MachineInstr::MachineInstr()
524  : MCID(0), Flags(0), AsmPrinterFlags(0),
525    NumMemRefs(0), MemRefs(0),
526    Parent(0) {
527  // Make sure that we get added to a machine basicblock
528  LeakDetector::addGarbageObject(this);
529}
530
531void MachineInstr::addImplicitDefUseOperands() {
532  if (MCID->ImplicitDefs)
533    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
534      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
535  if (MCID->ImplicitUses)
536    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
537      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
538}
539
540/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
541/// implicit operands. It reserves space for the number of operands specified by
542/// the MCInstrDesc.
543MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
544                           bool NoImp)
545  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
546    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
547  unsigned NumImplicitOps = 0;
548  if (!NoImp)
549    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
550  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
551  if (!NoImp)
552    addImplicitDefUseOperands();
553  // Make sure that we get added to a machine basicblock
554  LeakDetector::addGarbageObject(this);
555}
556
557/// MachineInstr ctor - Work exactly the same as the ctor two above, except
558/// that the MachineInstr is created and added to the end of the specified
559/// basic block.
560MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
561                           const MCInstrDesc &tid)
562  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
563    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
564  assert(MBB && "Cannot use inserting ctor with null basic block!");
565  unsigned NumImplicitOps =
566    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
567  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
568  addImplicitDefUseOperands();
569  // Make sure that we get added to a machine basicblock
570  LeakDetector::addGarbageObject(this);
571  MBB->push_back(this);  // Add instruction to end of basic block!
572}
573
574/// MachineInstr ctor - Copies MachineInstr arg exactly
575///
576MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
577  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
578    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
579    Parent(0), debugLoc(MI.getDebugLoc()) {
580  Operands.reserve(MI.getNumOperands());
581
582  // Add operands
583  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
584    addOperand(MI.getOperand(i));
585
586  // Copy all the flags.
587  Flags = MI.Flags;
588
589  // Set parent to null.
590  Parent = 0;
591
592  LeakDetector::addGarbageObject(this);
593}
594
595MachineInstr::~MachineInstr() {
596  LeakDetector::removeGarbageObject(this);
597#ifndef NDEBUG
598  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
599    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
600    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
601           "Reg operand def/use list corrupted");
602  }
603#endif
604}
605
606/// getRegInfo - If this instruction is embedded into a MachineFunction,
607/// return the MachineRegisterInfo object for the current function, otherwise
608/// return null.
609MachineRegisterInfo *MachineInstr::getRegInfo() {
610  if (MachineBasicBlock *MBB = getParent())
611    return &MBB->getParent()->getRegInfo();
612  return 0;
613}
614
615/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
616/// this instruction from their respective use lists.  This requires that the
617/// operands already be on their use lists.
618void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
619  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
620    if (Operands[i].isReg())
621      MRI.removeRegOperandFromUseList(&Operands[i]);
622}
623
624/// AddRegOperandsToUseLists - Add all of the register operands in
625/// this instruction from their respective use lists.  This requires that the
626/// operands not be on their use lists yet.
627void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
628  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
629    if (Operands[i].isReg())
630      MRI.addRegOperandToUseList(&Operands[i]);
631}
632
633/// addOperand - Add the specified operand to the instruction.  If it is an
634/// implicit operand, it is added to the end of the operand list.  If it is
635/// an explicit operand it is added at the end of the explicit operand list
636/// (before the first implicit operand).
637void MachineInstr::addOperand(const MachineOperand &Op) {
638  assert(MCID && "Cannot add operands before providing an instr descriptor");
639  bool isImpReg = Op.isReg() && Op.isImplicit();
640  MachineRegisterInfo *RegInfo = getRegInfo();
641
642  // If the Operands backing store is reallocated, all register operands must
643  // be removed and re-added to RegInfo.  It is storing pointers to operands.
644  bool Reallocate = RegInfo &&
645    !Operands.empty() && Operands.size() == Operands.capacity();
646
647  // Find the insert location for the new operand.  Implicit registers go at
648  // the end, everything goes before the implicit regs.
649  unsigned OpNo = Operands.size();
650
651  // Remove all the implicit operands from RegInfo if they need to be shifted.
652  // FIXME: Allow mixed explicit and implicit operands on inline asm.
653  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
654  // implicit-defs, but they must not be moved around.  See the FIXME in
655  // InstrEmitter.cpp.
656  if (!isImpReg && !isInlineAsm()) {
657    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
658      --OpNo;
659      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
660      if (RegInfo)
661        RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
662    }
663  }
664
665  // OpNo now points as the desired insertion point.  Unless this is a variadic
666  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
667  // RegMask operands go between the explicit and implicit operands.
668  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
669          OpNo < MCID->getNumOperands()) &&
670         "Trying to add an operand to a machine instr that is already done!");
671
672  // All operands from OpNo have been removed from RegInfo.  If the Operands
673  // backing store needs to be reallocated, we also need to remove any other
674  // register operands.
675  if (Reallocate)
676    for (unsigned i = 0; i != OpNo; ++i)
677      if (Operands[i].isReg())
678        RegInfo->removeRegOperandFromUseList(&Operands[i]);
679
680  // Insert the new operand at OpNo.
681  Operands.insert(Operands.begin() + OpNo, Op);
682  Operands[OpNo].ParentMI = this;
683
684  // The Operands backing store has now been reallocated, so we can re-add the
685  // operands before OpNo.
686  if (Reallocate)
687    for (unsigned i = 0; i != OpNo; ++i)
688      if (Operands[i].isReg())
689        RegInfo->addRegOperandToUseList(&Operands[i]);
690
691  // When adding a register operand, tell RegInfo about it.
692  if (Operands[OpNo].isReg()) {
693    // Ensure isOnRegUseList() returns false, regardless of Op's status.
694    Operands[OpNo].Contents.Reg.Prev = 0;
695    // Ignore existing ties. This is not a property that can be copied.
696    Operands[OpNo].TiedTo = 0;
697    // Add the new operand to RegInfo.
698    if (RegInfo)
699      RegInfo->addRegOperandToUseList(&Operands[OpNo]);
700    // The MCID operand information isn't accurate until we start adding
701    // explicit operands. The implicit operands are added first, then the
702    // explicits are inserted before them.
703    if (!isImpReg) {
704      // Tie uses to defs as indicated in MCInstrDesc.
705      if (Operands[OpNo].isUse()) {
706        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
707        if (DefIdx != -1)
708          tieOperands(DefIdx, OpNo);
709      }
710      // If the register operand is flagged as early, mark the operand as such.
711      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
712        Operands[OpNo].setIsEarlyClobber(true);
713    }
714  }
715
716  // Re-add all the implicit ops.
717  if (RegInfo) {
718    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
719      assert(Operands[i].isReg() && "Should only be an implicit reg!");
720      RegInfo->addRegOperandToUseList(&Operands[i]);
721    }
722  }
723}
724
725/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
726/// fewer operand than it started with.
727///
728void MachineInstr::RemoveOperand(unsigned OpNo) {
729  assert(OpNo < Operands.size() && "Invalid operand number");
730  untieRegOperand(OpNo);
731  MachineRegisterInfo *RegInfo = getRegInfo();
732
733  // Special case removing the last one.
734  if (OpNo == Operands.size()-1) {
735    // If needed, remove from the reg def/use list.
736    if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
737      RegInfo->removeRegOperandFromUseList(&Operands.back());
738
739    Operands.pop_back();
740    return;
741  }
742
743  // Otherwise, we are removing an interior operand.  If we have reginfo to
744  // update, remove all operands that will be shifted down from their reg lists,
745  // move everything down, then re-add them.
746  if (RegInfo) {
747    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
748      if (Operands[i].isReg())
749        RegInfo->removeRegOperandFromUseList(&Operands[i]);
750    }
751  }
752
753#ifndef NDEBUG
754  // Moving tied operands would break the ties.
755  for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i)
756    if (Operands[i].isReg())
757      assert(!Operands[i].isTied() && "Cannot move tied operands");
758#endif
759
760  Operands.erase(Operands.begin()+OpNo);
761
762  if (RegInfo) {
763    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
764      if (Operands[i].isReg())
765        RegInfo->addRegOperandToUseList(&Operands[i]);
766    }
767  }
768}
769
770/// addMemOperand - Add a MachineMemOperand to the machine instruction.
771/// This function should be used only occasionally. The setMemRefs function
772/// is the primary method for setting up a MachineInstr's MemRefs list.
773void MachineInstr::addMemOperand(MachineFunction &MF,
774                                 MachineMemOperand *MO) {
775  mmo_iterator OldMemRefs = MemRefs;
776  uint16_t OldNumMemRefs = NumMemRefs;
777
778  uint16_t NewNum = NumMemRefs + 1;
779  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
780
781  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
782  NewMemRefs[NewNum - 1] = MO;
783
784  MemRefs = NewMemRefs;
785  NumMemRefs = NewNum;
786}
787
788bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
789  const MachineBasicBlock *MBB = getParent();
790  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
791  while (MII != MBB->end() && MII->isInsideBundle()) {
792    if (MII->getDesc().getFlags() & Mask) {
793      if (Type == AnyInBundle)
794        return true;
795    } else {
796      if (Type == AllInBundle)
797        return false;
798    }
799    ++MII;
800  }
801
802  return Type == AllInBundle;
803}
804
805bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
806                                 MICheckType Check) const {
807  // If opcodes or number of operands are not the same then the two
808  // instructions are obviously not identical.
809  if (Other->getOpcode() != getOpcode() ||
810      Other->getNumOperands() != getNumOperands())
811    return false;
812
813  if (isBundle()) {
814    // Both instructions are bundles, compare MIs inside the bundle.
815    MachineBasicBlock::const_instr_iterator I1 = *this;
816    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
817    MachineBasicBlock::const_instr_iterator I2 = *Other;
818    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
819    while (++I1 != E1 && I1->isInsideBundle()) {
820      ++I2;
821      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
822        return false;
823    }
824  }
825
826  // Check operands to make sure they match.
827  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
828    const MachineOperand &MO = getOperand(i);
829    const MachineOperand &OMO = Other->getOperand(i);
830    if (!MO.isReg()) {
831      if (!MO.isIdenticalTo(OMO))
832        return false;
833      continue;
834    }
835
836    // Clients may or may not want to ignore defs when testing for equality.
837    // For example, machine CSE pass only cares about finding common
838    // subexpressions, so it's safe to ignore virtual register defs.
839    if (MO.isDef()) {
840      if (Check == IgnoreDefs)
841        continue;
842      else if (Check == IgnoreVRegDefs) {
843        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
844            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
845          if (MO.getReg() != OMO.getReg())
846            return false;
847      } else {
848        if (!MO.isIdenticalTo(OMO))
849          return false;
850        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
851          return false;
852      }
853    } else {
854      if (!MO.isIdenticalTo(OMO))
855        return false;
856      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
857        return false;
858    }
859  }
860  // If DebugLoc does not match then two dbg.values are not identical.
861  if (isDebugValue())
862    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
863        && getDebugLoc() != Other->getDebugLoc())
864      return false;
865  return true;
866}
867
868/// removeFromParent - This method unlinks 'this' from the containing basic
869/// block, and returns it, but does not delete it.
870MachineInstr *MachineInstr::removeFromParent() {
871  assert(getParent() && "Not embedded in a basic block!");
872
873  // If it's a bundle then remove the MIs inside the bundle as well.
874  if (isBundle()) {
875    MachineBasicBlock *MBB = getParent();
876    MachineBasicBlock::instr_iterator MII = *this; ++MII;
877    MachineBasicBlock::instr_iterator E = MBB->instr_end();
878    while (MII != E && MII->isInsideBundle()) {
879      MachineInstr *MI = &*MII;
880      ++MII;
881      MBB->remove(MI);
882    }
883  }
884  getParent()->remove(this);
885  return this;
886}
887
888
889/// eraseFromParent - This method unlinks 'this' from the containing basic
890/// block, and deletes it.
891void MachineInstr::eraseFromParent() {
892  assert(getParent() && "Not embedded in a basic block!");
893  // If it's a bundle then remove the MIs inside the bundle as well.
894  if (isBundle()) {
895    MachineBasicBlock *MBB = getParent();
896    MachineBasicBlock::instr_iterator MII = *this; ++MII;
897    MachineBasicBlock::instr_iterator E = MBB->instr_end();
898    while (MII != E && MII->isInsideBundle()) {
899      MachineInstr *MI = &*MII;
900      ++MII;
901      MBB->erase(MI);
902    }
903  }
904  // Erase the individual instruction, which may itself be inside a bundle.
905  getParent()->erase_instr(this);
906}
907
908
909/// getNumExplicitOperands - Returns the number of non-implicit operands.
910///
911unsigned MachineInstr::getNumExplicitOperands() const {
912  unsigned NumOperands = MCID->getNumOperands();
913  if (!MCID->isVariadic())
914    return NumOperands;
915
916  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
917    const MachineOperand &MO = getOperand(i);
918    if (!MO.isReg() || !MO.isImplicit())
919      NumOperands++;
920  }
921  return NumOperands;
922}
923
924/// isBundled - Return true if this instruction part of a bundle. This is true
925/// if either itself or its following instruction is marked "InsideBundle".
926bool MachineInstr::isBundled() const {
927  if (isInsideBundle())
928    return true;
929  MachineBasicBlock::const_instr_iterator nextMI = this;
930  ++nextMI;
931  return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
932}
933
934bool MachineInstr::isStackAligningInlineAsm() const {
935  if (isInlineAsm()) {
936    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
937    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
938      return true;
939  }
940  return false;
941}
942
943InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
944  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
945  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
946  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
947}
948
949int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
950                                       unsigned *GroupNo) const {
951  assert(isInlineAsm() && "Expected an inline asm instruction");
952  assert(OpIdx < getNumOperands() && "OpIdx out of range");
953
954  // Ignore queries about the initial operands.
955  if (OpIdx < InlineAsm::MIOp_FirstOperand)
956    return -1;
957
958  unsigned Group = 0;
959  unsigned NumOps;
960  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
961       i += NumOps) {
962    const MachineOperand &FlagMO = getOperand(i);
963    // If we reach the implicit register operands, stop looking.
964    if (!FlagMO.isImm())
965      return -1;
966    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
967    if (i + NumOps > OpIdx) {
968      if (GroupNo)
969        *GroupNo = Group;
970      return i;
971    }
972    ++Group;
973  }
974  return -1;
975}
976
977const TargetRegisterClass*
978MachineInstr::getRegClassConstraint(unsigned OpIdx,
979                                    const TargetInstrInfo *TII,
980                                    const TargetRegisterInfo *TRI) const {
981  assert(getParent() && "Can't have an MBB reference here!");
982  assert(getParent()->getParent() && "Can't have an MF reference here!");
983  const MachineFunction &MF = *getParent()->getParent();
984
985  // Most opcodes have fixed constraints in their MCInstrDesc.
986  if (!isInlineAsm())
987    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
988
989  if (!getOperand(OpIdx).isReg())
990    return NULL;
991
992  // For tied uses on inline asm, get the constraint from the def.
993  unsigned DefIdx;
994  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
995    OpIdx = DefIdx;
996
997  // Inline asm stores register class constraints in the flag word.
998  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
999  if (FlagIdx < 0)
1000    return NULL;
1001
1002  unsigned Flag = getOperand(FlagIdx).getImm();
1003  unsigned RCID;
1004  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1005    return TRI->getRegClass(RCID);
1006
1007  // Assume that all registers in a memory operand are pointers.
1008  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1009    return TRI->getPointerRegClass(MF);
1010
1011  return NULL;
1012}
1013
1014/// getBundleSize - Return the number of instructions inside the MI bundle.
1015unsigned MachineInstr::getBundleSize() const {
1016  assert(isBundle() && "Expecting a bundle");
1017
1018  MachineBasicBlock::const_instr_iterator I = *this;
1019  unsigned Size = 0;
1020  while ((++I)->isInsideBundle()) {
1021    ++Size;
1022  }
1023  assert(Size > 1 && "Malformed bundle");
1024
1025  return Size;
1026}
1027
1028/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1029/// the specific register or -1 if it is not found. It further tightens
1030/// the search criteria to a use that kills the register if isKill is true.
1031int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1032                                          const TargetRegisterInfo *TRI) const {
1033  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1034    const MachineOperand &MO = getOperand(i);
1035    if (!MO.isReg() || !MO.isUse())
1036      continue;
1037    unsigned MOReg = MO.getReg();
1038    if (!MOReg)
1039      continue;
1040    if (MOReg == Reg ||
1041        (TRI &&
1042         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1043         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1044         TRI->isSubRegister(MOReg, Reg)))
1045      if (!isKill || MO.isKill())
1046        return i;
1047  }
1048  return -1;
1049}
1050
1051/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1052/// indicating if this instruction reads or writes Reg. This also considers
1053/// partial defines.
1054std::pair<bool,bool>
1055MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1056                                         SmallVectorImpl<unsigned> *Ops) const {
1057  bool PartDef = false; // Partial redefine.
1058  bool FullDef = false; // Full define.
1059  bool Use = false;
1060
1061  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1062    const MachineOperand &MO = getOperand(i);
1063    if (!MO.isReg() || MO.getReg() != Reg)
1064      continue;
1065    if (Ops)
1066      Ops->push_back(i);
1067    if (MO.isUse())
1068      Use |= !MO.isUndef();
1069    else if (MO.getSubReg() && !MO.isUndef())
1070      // A partial <def,undef> doesn't count as reading the register.
1071      PartDef = true;
1072    else
1073      FullDef = true;
1074  }
1075  // A partial redefine uses Reg unless there is also a full define.
1076  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1077}
1078
1079/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1080/// the specified register or -1 if it is not found. If isDead is true, defs
1081/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1082/// also checks if there is a def of a super-register.
1083int
1084MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1085                                        const TargetRegisterInfo *TRI) const {
1086  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1087  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1088    const MachineOperand &MO = getOperand(i);
1089    // Accept regmask operands when Overlap is set.
1090    // Ignore them when looking for a specific def operand (Overlap == false).
1091    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1092      return i;
1093    if (!MO.isReg() || !MO.isDef())
1094      continue;
1095    unsigned MOReg = MO.getReg();
1096    bool Found = (MOReg == Reg);
1097    if (!Found && TRI && isPhys &&
1098        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1099      if (Overlap)
1100        Found = TRI->regsOverlap(MOReg, Reg);
1101      else
1102        Found = TRI->isSubRegister(MOReg, Reg);
1103    }
1104    if (Found && (!isDead || MO.isDead()))
1105      return i;
1106  }
1107  return -1;
1108}
1109
1110/// findFirstPredOperandIdx() - Find the index of the first operand in the
1111/// operand list that is used to represent the predicate. It returns -1 if
1112/// none is found.
1113int MachineInstr::findFirstPredOperandIdx() const {
1114  // Don't call MCID.findFirstPredOperandIdx() because this variant
1115  // is sometimes called on an instruction that's not yet complete, and
1116  // so the number of operands is less than the MCID indicates. In
1117  // particular, the PTX target does this.
1118  const MCInstrDesc &MCID = getDesc();
1119  if (MCID.isPredicable()) {
1120    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1121      if (MCID.OpInfo[i].isPredicate())
1122        return i;
1123  }
1124
1125  return -1;
1126}
1127
1128// MachineOperand::TiedTo is 4 bits wide.
1129const unsigned TiedMax = 15;
1130
1131/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1132///
1133/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1134/// field. TiedTo can have these values:
1135///
1136/// 0:              Operand is not tied to anything.
1137/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1138/// TiedMax:        Tied to an operand >= TiedMax-1.
1139///
1140/// The tied def must be one of the first TiedMax operands on a normal
1141/// instruction. INLINEASM instructions allow more tied defs.
1142///
1143void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1144  MachineOperand &DefMO = getOperand(DefIdx);
1145  MachineOperand &UseMO = getOperand(UseIdx);
1146  assert(DefMO.isDef() && "DefIdx must be a def operand");
1147  assert(UseMO.isUse() && "UseIdx must be a use operand");
1148  assert(!DefMO.isTied() && "Def is already tied to another use");
1149  assert(!UseMO.isTied() && "Use is already tied to another def");
1150
1151  if (DefIdx < TiedMax)
1152    UseMO.TiedTo = DefIdx + 1;
1153  else {
1154    // Inline asm can use the group descriptors to find tied operands, but on
1155    // normal instruction, the tied def must be within the first TiedMax
1156    // operands.
1157    assert(isInlineAsm() && "DefIdx out of range");
1158    UseMO.TiedTo = TiedMax;
1159  }
1160
1161  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1162  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1163}
1164
1165/// Given the index of a tied register operand, find the operand it is tied to.
1166/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1167/// which must exist.
1168unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1169  const MachineOperand &MO = getOperand(OpIdx);
1170  assert(MO.isTied() && "Operand isn't tied");
1171
1172  // Normally TiedTo is in range.
1173  if (MO.TiedTo < TiedMax)
1174    return MO.TiedTo - 1;
1175
1176  // Uses on normal instructions can be out of range.
1177  if (!isInlineAsm()) {
1178    // Normal tied defs must be in the 0..TiedMax-1 range.
1179    if (MO.isUse())
1180      return TiedMax - 1;
1181    // MO is a def. Search for the tied use.
1182    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1183      const MachineOperand &UseMO = getOperand(i);
1184      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1185        return i;
1186    }
1187    llvm_unreachable("Can't find tied use");
1188  }
1189
1190  // Now deal with inline asm by parsing the operand group descriptor flags.
1191  // Find the beginning of each operand group.
1192  SmallVector<unsigned, 8> GroupIdx;
1193  unsigned OpIdxGroup = ~0u;
1194  unsigned NumOps;
1195  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1196       i += NumOps) {
1197    const MachineOperand &FlagMO = getOperand(i);
1198    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1199    unsigned CurGroup = GroupIdx.size();
1200    GroupIdx.push_back(i);
1201    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1202    // OpIdx belongs to this operand group.
1203    if (OpIdx > i && OpIdx < i + NumOps)
1204      OpIdxGroup = CurGroup;
1205    unsigned TiedGroup;
1206    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1207      continue;
1208    // Operands in this group are tied to operands in TiedGroup which must be
1209    // earlier. Find the number of operands between the two groups.
1210    unsigned Delta = i - GroupIdx[TiedGroup];
1211
1212    // OpIdx is a use tied to TiedGroup.
1213    if (OpIdxGroup == CurGroup)
1214      return OpIdx - Delta;
1215
1216    // OpIdx is a def tied to this use group.
1217    if (OpIdxGroup == TiedGroup)
1218      return OpIdx + Delta;
1219  }
1220  llvm_unreachable("Invalid tied operand on inline asm");
1221}
1222
1223/// clearKillInfo - Clears kill flags on all operands.
1224///
1225void MachineInstr::clearKillInfo() {
1226  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1227    MachineOperand &MO = getOperand(i);
1228    if (MO.isReg() && MO.isUse())
1229      MO.setIsKill(false);
1230  }
1231}
1232
1233/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1234///
1235void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1236  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1237    const MachineOperand &MO = MI->getOperand(i);
1238    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1239      continue;
1240    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1241      MachineOperand &MOp = getOperand(j);
1242      if (!MOp.isIdenticalTo(MO))
1243        continue;
1244      if (MO.isKill())
1245        MOp.setIsKill();
1246      else
1247        MOp.setIsDead();
1248      break;
1249    }
1250  }
1251}
1252
1253/// copyPredicates - Copies predicate operand(s) from MI.
1254void MachineInstr::copyPredicates(const MachineInstr *MI) {
1255  assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1256
1257  const MCInstrDesc &MCID = MI->getDesc();
1258  if (!MCID.isPredicable())
1259    return;
1260  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1261    if (MCID.OpInfo[i].isPredicate()) {
1262      // Predicated operands must be last operands.
1263      addOperand(MI->getOperand(i));
1264    }
1265  }
1266}
1267
1268void MachineInstr::substituteRegister(unsigned FromReg,
1269                                      unsigned ToReg,
1270                                      unsigned SubIdx,
1271                                      const TargetRegisterInfo &RegInfo) {
1272  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1273    if (SubIdx)
1274      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1275    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1276      MachineOperand &MO = getOperand(i);
1277      if (!MO.isReg() || MO.getReg() != FromReg)
1278        continue;
1279      MO.substPhysReg(ToReg, RegInfo);
1280    }
1281  } else {
1282    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1283      MachineOperand &MO = getOperand(i);
1284      if (!MO.isReg() || MO.getReg() != FromReg)
1285        continue;
1286      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1287    }
1288  }
1289}
1290
1291/// isSafeToMove - Return true if it is safe to move this instruction. If
1292/// SawStore is set to true, it means that there is a store (or call) between
1293/// the instruction's location and its intended destination.
1294bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1295                                AliasAnalysis *AA,
1296                                bool &SawStore) const {
1297  // Ignore stuff that we obviously can't move.
1298  //
1299  // Treat volatile loads as stores. This is not strictly necessary for
1300  // volatiles, but it is required for atomic loads. It is not allowed to move
1301  // a load across an atomic load with Ordering > Monotonic.
1302  if (mayStore() || isCall() ||
1303      (mayLoad() && hasOrderedMemoryRef())) {
1304    SawStore = true;
1305    return false;
1306  }
1307
1308  if (isLabel() || isDebugValue() ||
1309      isTerminator() || hasUnmodeledSideEffects())
1310    return false;
1311
1312  // See if this instruction does a load.  If so, we have to guarantee that the
1313  // loaded value doesn't change between the load and the its intended
1314  // destination. The check for isInvariantLoad gives the targe the chance to
1315  // classify the load as always returning a constant, e.g. a constant pool
1316  // load.
1317  if (mayLoad() && !isInvariantLoad(AA))
1318    // Otherwise, this is a real load.  If there is a store between the load and
1319    // end of block, we can't move it.
1320    return !SawStore;
1321
1322  return true;
1323}
1324
1325/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1326/// instruction which defined the specified register instead of copying it.
1327bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1328                                 AliasAnalysis *AA,
1329                                 unsigned DstReg) const {
1330  bool SawStore = false;
1331  if (!TII->isTriviallyReMaterializable(this, AA) ||
1332      !isSafeToMove(TII, AA, SawStore))
1333    return false;
1334  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1335    const MachineOperand &MO = getOperand(i);
1336    if (!MO.isReg())
1337      continue;
1338    // FIXME: For now, do not remat any instruction with register operands.
1339    // Later on, we can loosen the restriction is the register operands have
1340    // not been modified between the def and use. Note, this is different from
1341    // MachineSink because the code is no longer in two-address form (at least
1342    // partially).
1343    if (MO.isUse())
1344      return false;
1345    else if (!MO.isDead() && MO.getReg() != DstReg)
1346      return false;
1347  }
1348  return true;
1349}
1350
1351/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1352/// or volatile memory reference, or if the information describing the memory
1353/// reference is not available. Return false if it is known to have no ordered
1354/// memory references.
1355bool MachineInstr::hasOrderedMemoryRef() const {
1356  // An instruction known never to access memory won't have a volatile access.
1357  if (!mayStore() &&
1358      !mayLoad() &&
1359      !isCall() &&
1360      !hasUnmodeledSideEffects())
1361    return false;
1362
1363  // Otherwise, if the instruction has no memory reference information,
1364  // conservatively assume it wasn't preserved.
1365  if (memoperands_empty())
1366    return true;
1367
1368  // Check the memory reference information for ordered references.
1369  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1370    if (!(*I)->isUnordered())
1371      return true;
1372
1373  return false;
1374}
1375
1376/// isInvariantLoad - Return true if this instruction is loading from a
1377/// location whose value is invariant across the function.  For example,
1378/// loading a value from the constant pool or from the argument area
1379/// of a function if it does not change.  This should only return true of
1380/// *all* loads the instruction does are invariant (if it does multiple loads).
1381bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1382  // If the instruction doesn't load at all, it isn't an invariant load.
1383  if (!mayLoad())
1384    return false;
1385
1386  // If the instruction has lost its memoperands, conservatively assume that
1387  // it may not be an invariant load.
1388  if (memoperands_empty())
1389    return false;
1390
1391  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1392
1393  for (mmo_iterator I = memoperands_begin(),
1394       E = memoperands_end(); I != E; ++I) {
1395    if ((*I)->isVolatile()) return false;
1396    if ((*I)->isStore()) return false;
1397    if ((*I)->isInvariant()) return true;
1398
1399    if (const Value *V = (*I)->getValue()) {
1400      // A load from a constant PseudoSourceValue is invariant.
1401      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1402        if (PSV->isConstant(MFI))
1403          continue;
1404      // If we have an AliasAnalysis, ask it whether the memory is constant.
1405      if (AA && AA->pointsToConstantMemory(
1406                      AliasAnalysis::Location(V, (*I)->getSize(),
1407                                              (*I)->getTBAAInfo())))
1408        continue;
1409    }
1410
1411    // Otherwise assume conservatively.
1412    return false;
1413  }
1414
1415  // Everything checks out.
1416  return true;
1417}
1418
1419/// isConstantValuePHI - If the specified instruction is a PHI that always
1420/// merges together the same virtual register, return the register, otherwise
1421/// return 0.
1422unsigned MachineInstr::isConstantValuePHI() const {
1423  if (!isPHI())
1424    return 0;
1425  assert(getNumOperands() >= 3 &&
1426         "It's illegal to have a PHI without source operands");
1427
1428  unsigned Reg = getOperand(1).getReg();
1429  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1430    if (getOperand(i).getReg() != Reg)
1431      return 0;
1432  return Reg;
1433}
1434
1435bool MachineInstr::hasUnmodeledSideEffects() const {
1436  if (hasProperty(MCID::UnmodeledSideEffects))
1437    return true;
1438  if (isInlineAsm()) {
1439    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1440    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1441      return true;
1442  }
1443
1444  return false;
1445}
1446
1447/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1448///
1449bool MachineInstr::allDefsAreDead() const {
1450  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1451    const MachineOperand &MO = getOperand(i);
1452    if (!MO.isReg() || MO.isUse())
1453      continue;
1454    if (!MO.isDead())
1455      return false;
1456  }
1457  return true;
1458}
1459
1460/// copyImplicitOps - Copy implicit register operands from specified
1461/// instruction to this instruction.
1462void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1463  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1464       i != e; ++i) {
1465    const MachineOperand &MO = MI->getOperand(i);
1466    if (MO.isReg() && MO.isImplicit())
1467      addOperand(MO);
1468  }
1469}
1470
1471void MachineInstr::dump() const {
1472#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1473  dbgs() << "  " << *this;
1474#endif
1475}
1476
1477static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1478                         raw_ostream &CommentOS) {
1479  const LLVMContext &Ctx = MF->getFunction()->getContext();
1480  if (!DL.isUnknown()) {          // Print source line info.
1481    DIScope Scope(DL.getScope(Ctx));
1482    // Omit the directory, because it's likely to be long and uninteresting.
1483    if (Scope.Verify())
1484      CommentOS << Scope.getFilename();
1485    else
1486      CommentOS << "<unknown>";
1487    CommentOS << ':' << DL.getLine();
1488    if (DL.getCol() != 0)
1489      CommentOS << ':' << DL.getCol();
1490    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1491    if (!InlinedAtDL.isUnknown()) {
1492      CommentOS << " @[ ";
1493      printDebugLoc(InlinedAtDL, MF, CommentOS);
1494      CommentOS << " ]";
1495    }
1496  }
1497}
1498
1499void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1500  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1501  const MachineFunction *MF = 0;
1502  const MachineRegisterInfo *MRI = 0;
1503  if (const MachineBasicBlock *MBB = getParent()) {
1504    MF = MBB->getParent();
1505    if (!TM && MF)
1506      TM = &MF->getTarget();
1507    if (MF)
1508      MRI = &MF->getRegInfo();
1509  }
1510
1511  // Save a list of virtual registers.
1512  SmallVector<unsigned, 8> VirtRegs;
1513
1514  // Print explicitly defined operands on the left of an assignment syntax.
1515  unsigned StartOp = 0, e = getNumOperands();
1516  for (; StartOp < e && getOperand(StartOp).isReg() &&
1517         getOperand(StartOp).isDef() &&
1518         !getOperand(StartOp).isImplicit();
1519       ++StartOp) {
1520    if (StartOp != 0) OS << ", ";
1521    getOperand(StartOp).print(OS, TM);
1522    unsigned Reg = getOperand(StartOp).getReg();
1523    if (TargetRegisterInfo::isVirtualRegister(Reg))
1524      VirtRegs.push_back(Reg);
1525  }
1526
1527  if (StartOp != 0)
1528    OS << " = ";
1529
1530  // Print the opcode name.
1531  if (TM && TM->getInstrInfo())
1532    OS << TM->getInstrInfo()->getName(getOpcode());
1533  else
1534    OS << "UNKNOWN";
1535
1536  // Print the rest of the operands.
1537  bool OmittedAnyCallClobbers = false;
1538  bool FirstOp = true;
1539  unsigned AsmDescOp = ~0u;
1540  unsigned AsmOpCount = 0;
1541
1542  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1543    // Print asm string.
1544    OS << " ";
1545    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1546
1547    // Print HasSideEffects, IsAlignStack
1548    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1549    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1550      OS << " [sideeffect]";
1551    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1552      OS << " [alignstack]";
1553    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1554      OS << " [attdialect]";
1555    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1556      OS << " [inteldialect]";
1557
1558    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1559    FirstOp = false;
1560  }
1561
1562
1563  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1564    const MachineOperand &MO = getOperand(i);
1565
1566    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1567      VirtRegs.push_back(MO.getReg());
1568
1569    // Omit call-clobbered registers which aren't used anywhere. This makes
1570    // call instructions much less noisy on targets where calls clobber lots
1571    // of registers. Don't rely on MO.isDead() because we may be called before
1572    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1573    if (MF && isCall() &&
1574        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1575      unsigned Reg = MO.getReg();
1576      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1577        const MachineRegisterInfo &MRI = MF->getRegInfo();
1578        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1579          bool HasAliasLive = false;
1580          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1581               AI.isValid(); ++AI) {
1582            unsigned AliasReg = *AI;
1583            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1584              HasAliasLive = true;
1585              break;
1586            }
1587          }
1588          if (!HasAliasLive) {
1589            OmittedAnyCallClobbers = true;
1590            continue;
1591          }
1592        }
1593      }
1594    }
1595
1596    if (FirstOp) FirstOp = false; else OS << ",";
1597    OS << " ";
1598    if (i < getDesc().NumOperands) {
1599      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1600      if (MCOI.isPredicate())
1601        OS << "pred:";
1602      if (MCOI.isOptionalDef())
1603        OS << "opt:";
1604    }
1605    if (isDebugValue() && MO.isMetadata()) {
1606      // Pretty print DBG_VALUE instructions.
1607      const MDNode *MD = MO.getMetadata();
1608      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1609        OS << "!\"" << MDS->getString() << '\"';
1610      else
1611        MO.print(OS, TM);
1612    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1613      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1614    } else if (i == AsmDescOp && MO.isImm()) {
1615      // Pretty print the inline asm operand descriptor.
1616      OS << '$' << AsmOpCount++;
1617      unsigned Flag = MO.getImm();
1618      switch (InlineAsm::getKind(Flag)) {
1619      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1620      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1621      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1622      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1623      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1624      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1625      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1626      }
1627
1628      unsigned RCID = 0;
1629      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1630        if (TM)
1631          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1632        else
1633          OS << ":RC" << RCID;
1634      }
1635
1636      unsigned TiedTo = 0;
1637      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1638        OS << " tiedto:$" << TiedTo;
1639
1640      OS << ']';
1641
1642      // Compute the index of the next operand descriptor.
1643      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1644    } else
1645      MO.print(OS, TM);
1646  }
1647
1648  // Briefly indicate whether any call clobbers were omitted.
1649  if (OmittedAnyCallClobbers) {
1650    if (!FirstOp) OS << ",";
1651    OS << " ...";
1652  }
1653
1654  bool HaveSemi = false;
1655  if (Flags) {
1656    if (!HaveSemi) OS << ";"; HaveSemi = true;
1657    OS << " flags: ";
1658
1659    if (Flags & FrameSetup)
1660      OS << "FrameSetup";
1661  }
1662
1663  if (!memoperands_empty()) {
1664    if (!HaveSemi) OS << ";"; HaveSemi = true;
1665
1666    OS << " mem:";
1667    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1668         i != e; ++i) {
1669      OS << **i;
1670      if (llvm::next(i) != e)
1671        OS << " ";
1672    }
1673  }
1674
1675  // Print the regclass of any virtual registers encountered.
1676  if (MRI && !VirtRegs.empty()) {
1677    if (!HaveSemi) OS << ";"; HaveSemi = true;
1678    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1679      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1680      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1681      for (unsigned j = i+1; j != VirtRegs.size();) {
1682        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1683          ++j;
1684          continue;
1685        }
1686        if (VirtRegs[i] != VirtRegs[j])
1687          OS << "," << PrintReg(VirtRegs[j]);
1688        VirtRegs.erase(VirtRegs.begin()+j);
1689      }
1690    }
1691  }
1692
1693  // Print debug location information.
1694  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1695    if (!HaveSemi) OS << ";"; HaveSemi = true;
1696    DIVariable DV(getOperand(e - 1).getMetadata());
1697    OS << " line no:" <<  DV.getLineNumber();
1698    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1699      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1700      if (!InlinedAtDL.isUnknown()) {
1701        OS << " inlined @[ ";
1702        printDebugLoc(InlinedAtDL, MF, OS);
1703        OS << " ]";
1704      }
1705    }
1706  } else if (!debugLoc.isUnknown() && MF) {
1707    if (!HaveSemi) OS << ";"; HaveSemi = true;
1708    OS << " dbg:";
1709    printDebugLoc(debugLoc, MF, OS);
1710  }
1711
1712  OS << '\n';
1713}
1714
1715bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1716                                     const TargetRegisterInfo *RegInfo,
1717                                     bool AddIfNotFound) {
1718  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1719  bool hasAliases = isPhysReg &&
1720    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1721  bool Found = false;
1722  SmallVector<unsigned,4> DeadOps;
1723  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1724    MachineOperand &MO = getOperand(i);
1725    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1726      continue;
1727    unsigned Reg = MO.getReg();
1728    if (!Reg)
1729      continue;
1730
1731    if (Reg == IncomingReg) {
1732      if (!Found) {
1733        if (MO.isKill())
1734          // The register is already marked kill.
1735          return true;
1736        if (isPhysReg && isRegTiedToDefOperand(i))
1737          // Two-address uses of physregs must not be marked kill.
1738          return true;
1739        MO.setIsKill();
1740        Found = true;
1741      }
1742    } else if (hasAliases && MO.isKill() &&
1743               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1744      // A super-register kill already exists.
1745      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1746        return true;
1747      if (RegInfo->isSubRegister(IncomingReg, Reg))
1748        DeadOps.push_back(i);
1749    }
1750  }
1751
1752  // Trim unneeded kill operands.
1753  while (!DeadOps.empty()) {
1754    unsigned OpIdx = DeadOps.back();
1755    if (getOperand(OpIdx).isImplicit())
1756      RemoveOperand(OpIdx);
1757    else
1758      getOperand(OpIdx).setIsKill(false);
1759    DeadOps.pop_back();
1760  }
1761
1762  // If not found, this means an alias of one of the operands is killed. Add a
1763  // new implicit operand if required.
1764  if (!Found && AddIfNotFound) {
1765    addOperand(MachineOperand::CreateReg(IncomingReg,
1766                                         false /*IsDef*/,
1767                                         true  /*IsImp*/,
1768                                         true  /*IsKill*/));
1769    return true;
1770  }
1771  return Found;
1772}
1773
1774void MachineInstr::clearRegisterKills(unsigned Reg,
1775                                      const TargetRegisterInfo *RegInfo) {
1776  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1777    RegInfo = 0;
1778  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1779    MachineOperand &MO = getOperand(i);
1780    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1781      continue;
1782    unsigned OpReg = MO.getReg();
1783    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1784      MO.setIsKill(false);
1785  }
1786}
1787
1788bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1789                                   const TargetRegisterInfo *RegInfo,
1790                                   bool AddIfNotFound) {
1791  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1792  bool hasAliases = isPhysReg &&
1793    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1794  bool Found = false;
1795  SmallVector<unsigned,4> DeadOps;
1796  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1797    MachineOperand &MO = getOperand(i);
1798    if (!MO.isReg() || !MO.isDef())
1799      continue;
1800    unsigned Reg = MO.getReg();
1801    if (!Reg)
1802      continue;
1803
1804    if (Reg == IncomingReg) {
1805      MO.setIsDead();
1806      Found = true;
1807    } else if (hasAliases && MO.isDead() &&
1808               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1809      // There exists a super-register that's marked dead.
1810      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1811        return true;
1812      if (RegInfo->isSubRegister(IncomingReg, Reg))
1813        DeadOps.push_back(i);
1814    }
1815  }
1816
1817  // Trim unneeded dead operands.
1818  while (!DeadOps.empty()) {
1819    unsigned OpIdx = DeadOps.back();
1820    if (getOperand(OpIdx).isImplicit())
1821      RemoveOperand(OpIdx);
1822    else
1823      getOperand(OpIdx).setIsDead(false);
1824    DeadOps.pop_back();
1825  }
1826
1827  // If not found, this means an alias of one of the operands is dead. Add a
1828  // new implicit operand if required.
1829  if (Found || !AddIfNotFound)
1830    return Found;
1831
1832  addOperand(MachineOperand::CreateReg(IncomingReg,
1833                                       true  /*IsDef*/,
1834                                       true  /*IsImp*/,
1835                                       false /*IsKill*/,
1836                                       true  /*IsDead*/));
1837  return true;
1838}
1839
1840void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1841                                      const TargetRegisterInfo *RegInfo) {
1842  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1843    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1844    if (MO)
1845      return;
1846  } else {
1847    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1848      const MachineOperand &MO = getOperand(i);
1849      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1850          MO.getSubReg() == 0)
1851        return;
1852    }
1853  }
1854  addOperand(MachineOperand::CreateReg(IncomingReg,
1855                                       true  /*IsDef*/,
1856                                       true  /*IsImp*/));
1857}
1858
1859void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1860                                         const TargetRegisterInfo &TRI) {
1861  bool HasRegMask = false;
1862  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1863    MachineOperand &MO = getOperand(i);
1864    if (MO.isRegMask()) {
1865      HasRegMask = true;
1866      continue;
1867    }
1868    if (!MO.isReg() || !MO.isDef()) continue;
1869    unsigned Reg = MO.getReg();
1870    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1871    bool Dead = true;
1872    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1873         I != E; ++I)
1874      if (TRI.regsOverlap(*I, Reg)) {
1875        Dead = false;
1876        break;
1877      }
1878    // If there are no uses, including partial uses, the def is dead.
1879    if (Dead) MO.setIsDead();
1880  }
1881
1882  // This is a call with a register mask operand.
1883  // Mask clobbers are always dead, so add defs for the non-dead defines.
1884  if (HasRegMask)
1885    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1886         I != E; ++I)
1887      addRegisterDefined(*I, &TRI);
1888}
1889
1890unsigned
1891MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1892  // Build up a buffer of hash code components.
1893  SmallVector<size_t, 8> HashComponents;
1894  HashComponents.reserve(MI->getNumOperands() + 1);
1895  HashComponents.push_back(MI->getOpcode());
1896  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1897    const MachineOperand &MO = MI->getOperand(i);
1898    if (MO.isReg() && MO.isDef() &&
1899        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1900      continue;  // Skip virtual register defs.
1901
1902    HashComponents.push_back(hash_value(MO));
1903  }
1904  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1905}
1906
1907void MachineInstr::emitError(StringRef Msg) const {
1908  // Find the source location cookie.
1909  unsigned LocCookie = 0;
1910  const MDNode *LocMD = 0;
1911  for (unsigned i = getNumOperands(); i != 0; --i) {
1912    if (getOperand(i-1).isMetadata() &&
1913        (LocMD = getOperand(i-1).getMetadata()) &&
1914        LocMD->getNumOperands() != 0) {
1915      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1916        LocCookie = CI->getZExtValue();
1917        break;
1918      }
1919    }
1920  }
1921
1922  if (const MachineBasicBlock *MBB = getParent())
1923    if (const MachineFunction *MF = MBB->getParent())
1924      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1925  report_fatal_error(Msg);
1926}
1927