MachineInstr.cpp revision 9f4692d2953b47e9037ccfe5709a6e75de3911d4
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Methods common to all machine instructions. 11// 12//===----------------------------------------------------------------------===// 13 14#include "llvm/CodeGen/MachineInstr.h" 15#include "llvm/ADT/FoldingSet.h" 16#include "llvm/ADT/Hashing.h" 17#include "llvm/Analysis/AliasAnalysis.h" 18#include "llvm/Assembly/Writer.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineMemOperand.h" 22#include "llvm/CodeGen/MachineModuleInfo.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/PseudoSourceValue.h" 25#include "llvm/Constants.h" 26#include "llvm/DebugInfo.h" 27#include "llvm/Function.h" 28#include "llvm/InlineAsm.h" 29#include "llvm/LLVMContext.h" 30#include "llvm/MC/MCInstrDesc.h" 31#include "llvm/MC/MCSymbol.h" 32#include "llvm/Metadata.h" 33#include "llvm/Module.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/LeakDetector.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include "llvm/Target/TargetInstrInfo.h" 40#include "llvm/Target/TargetMachine.h" 41#include "llvm/Target/TargetRegisterInfo.h" 42#include "llvm/Type.h" 43#include "llvm/Value.h" 44using namespace llvm; 45 46//===----------------------------------------------------------------------===// 47// MachineOperand Implementation 48//===----------------------------------------------------------------------===// 49 50void MachineOperand::setReg(unsigned Reg) { 51 if (getReg() == Reg) return; // No change. 52 53 // Otherwise, we have to change the register. If this operand is embedded 54 // into a machine function, we need to update the old and new register's 55 // use/def lists. 56 if (MachineInstr *MI = getParent()) 57 if (MachineBasicBlock *MBB = MI->getParent()) 58 if (MachineFunction *MF = MBB->getParent()) { 59 MachineRegisterInfo &MRI = MF->getRegInfo(); 60 MRI.removeRegOperandFromUseList(this); 61 SmallContents.RegNo = Reg; 62 MRI.addRegOperandToUseList(this); 63 return; 64 } 65 66 // Otherwise, just change the register, no problem. :) 67 SmallContents.RegNo = Reg; 68} 69 70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 71 const TargetRegisterInfo &TRI) { 72 assert(TargetRegisterInfo::isVirtualRegister(Reg)); 73 if (SubIdx && getSubReg()) 74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 75 setReg(Reg); 76 if (SubIdx) 77 setSubReg(SubIdx); 78} 79 80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 81 assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 82 if (getSubReg()) { 83 Reg = TRI.getSubReg(Reg, getSubReg()); 84 // Note that getSubReg() may return 0 if the sub-register doesn't exist. 85 // That won't happen in legal code. 86 setSubReg(0); 87 } 88 setReg(Reg); 89} 90 91/// Change a def to a use, or a use to a def. 92void MachineOperand::setIsDef(bool Val) { 93 assert(isReg() && "Wrong MachineOperand accessor"); 94 assert((!Val || !isDebug()) && "Marking a debug operation as def"); 95 if (IsDef == Val) 96 return; 97 // MRI may keep uses and defs in different list positions. 98 if (MachineInstr *MI = getParent()) 99 if (MachineBasicBlock *MBB = MI->getParent()) 100 if (MachineFunction *MF = MBB->getParent()) { 101 MachineRegisterInfo &MRI = MF->getRegInfo(); 102 MRI.removeRegOperandFromUseList(this); 103 IsDef = Val; 104 MRI.addRegOperandToUseList(this); 105 return; 106 } 107 IsDef = Val; 108} 109 110/// ChangeToImmediate - Replace this operand with a new immediate operand of 111/// the specified value. If an operand is known to be an immediate already, 112/// the setImm method should be used. 113void MachineOperand::ChangeToImmediate(int64_t ImmVal) { 114 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 115 // If this operand is currently a register operand, and if this is in a 116 // function, deregister the operand from the register's use/def list. 117 if (isReg() && isOnRegUseList()) 118 if (MachineInstr *MI = getParent()) 119 if (MachineBasicBlock *MBB = MI->getParent()) 120 if (MachineFunction *MF = MBB->getParent()) 121 MF->getRegInfo().removeRegOperandFromUseList(this); 122 123 OpKind = MO_Immediate; 124 Contents.ImmVal = ImmVal; 125} 126 127/// ChangeToRegister - Replace this operand with a new register operand of 128/// the specified value. If an operand is known to be an register already, 129/// the setReg method should be used. 130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 131 bool isKill, bool isDead, bool isUndef, 132 bool isDebug) { 133 MachineRegisterInfo *RegInfo = 0; 134 if (MachineInstr *MI = getParent()) 135 if (MachineBasicBlock *MBB = MI->getParent()) 136 if (MachineFunction *MF = MBB->getParent()) 137 RegInfo = &MF->getRegInfo(); 138 // If this operand is already a register operand, remove it from the 139 // register's use/def lists. 140 bool WasReg = isReg(); 141 if (RegInfo && WasReg) 142 RegInfo->removeRegOperandFromUseList(this); 143 144 // Change this to a register and set the reg#. 145 OpKind = MO_Register; 146 SmallContents.RegNo = Reg; 147 SubReg = 0; 148 IsDef = isDef; 149 IsImp = isImp; 150 IsKill = isKill; 151 IsDead = isDead; 152 IsUndef = isUndef; 153 IsInternalRead = false; 154 IsEarlyClobber = false; 155 IsDebug = isDebug; 156 // Ensure isOnRegUseList() returns false. 157 Contents.Reg.Prev = 0; 158 // Preserve the tie when the operand was already a register. 159 if (!WasReg) 160 TiedTo = 0; 161 162 // If this operand is embedded in a function, add the operand to the 163 // register's use/def list. 164 if (RegInfo) 165 RegInfo->addRegOperandToUseList(this); 166} 167 168/// isIdenticalTo - Return true if this operand is identical to the specified 169/// operand. Note that this should stay in sync with the hash_value overload 170/// below. 171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 172 if (getType() != Other.getType() || 173 getTargetFlags() != Other.getTargetFlags()) 174 return false; 175 176 switch (getType()) { 177 case MachineOperand::MO_Register: 178 return getReg() == Other.getReg() && isDef() == Other.isDef() && 179 getSubReg() == Other.getSubReg(); 180 case MachineOperand::MO_Immediate: 181 return getImm() == Other.getImm(); 182 case MachineOperand::MO_CImmediate: 183 return getCImm() == Other.getCImm(); 184 case MachineOperand::MO_FPImmediate: 185 return getFPImm() == Other.getFPImm(); 186 case MachineOperand::MO_MachineBasicBlock: 187 return getMBB() == Other.getMBB(); 188 case MachineOperand::MO_FrameIndex: 189 return getIndex() == Other.getIndex(); 190 case MachineOperand::MO_ConstantPoolIndex: 191 case MachineOperand::MO_TargetIndex: 192 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 193 case MachineOperand::MO_JumpTableIndex: 194 return getIndex() == Other.getIndex(); 195 case MachineOperand::MO_GlobalAddress: 196 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 197 case MachineOperand::MO_ExternalSymbol: 198 return !strcmp(getSymbolName(), Other.getSymbolName()) && 199 getOffset() == Other.getOffset(); 200 case MachineOperand::MO_BlockAddress: 201 return getBlockAddress() == Other.getBlockAddress() && 202 getOffset() == Other.getOffset(); 203 case MO_RegisterMask: 204 return getRegMask() == Other.getRegMask(); 205 case MachineOperand::MO_MCSymbol: 206 return getMCSymbol() == Other.getMCSymbol(); 207 case MachineOperand::MO_Metadata: 208 return getMetadata() == Other.getMetadata(); 209 } 210 llvm_unreachable("Invalid machine operand type"); 211} 212 213// Note: this must stay exactly in sync with isIdenticalTo above. 214hash_code llvm::hash_value(const MachineOperand &MO) { 215 switch (MO.getType()) { 216 case MachineOperand::MO_Register: 217 // Register operands don't have target flags. 218 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 219 case MachineOperand::MO_Immediate: 220 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 221 case MachineOperand::MO_CImmediate: 222 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); 223 case MachineOperand::MO_FPImmediate: 224 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); 225 case MachineOperand::MO_MachineBasicBlock: 226 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); 227 case MachineOperand::MO_FrameIndex: 228 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 229 case MachineOperand::MO_ConstantPoolIndex: 230 case MachineOperand::MO_TargetIndex: 231 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), 232 MO.getOffset()); 233 case MachineOperand::MO_JumpTableIndex: 234 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 235 case MachineOperand::MO_ExternalSymbol: 236 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), 237 MO.getSymbolName()); 238 case MachineOperand::MO_GlobalAddress: 239 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), 240 MO.getOffset()); 241 case MachineOperand::MO_BlockAddress: 242 return hash_combine(MO.getType(), MO.getTargetFlags(), 243 MO.getBlockAddress(), MO.getOffset()); 244 case MachineOperand::MO_RegisterMask: 245 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); 246 case MachineOperand::MO_Metadata: 247 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); 248 case MachineOperand::MO_MCSymbol: 249 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); 250 } 251 llvm_unreachable("Invalid machine operand type"); 252} 253 254/// print - Print the specified machine operand. 255/// 256void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 257 // If the instruction is embedded into a basic block, we can find the 258 // target info for the instruction. 259 if (!TM) 260 if (const MachineInstr *MI = getParent()) 261 if (const MachineBasicBlock *MBB = MI->getParent()) 262 if (const MachineFunction *MF = MBB->getParent()) 263 TM = &MF->getTarget(); 264 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 265 266 switch (getType()) { 267 case MachineOperand::MO_Register: 268 OS << PrintReg(getReg(), TRI, getSubReg()); 269 270 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 271 isInternalRead() || isEarlyClobber() || isTied()) { 272 OS << '<'; 273 bool NeedComma = false; 274 if (isDef()) { 275 if (NeedComma) OS << ','; 276 if (isEarlyClobber()) 277 OS << "earlyclobber,"; 278 if (isImplicit()) 279 OS << "imp-"; 280 OS << "def"; 281 NeedComma = true; 282 // <def,read-undef> only makes sense when getSubReg() is set. 283 // Don't clutter the output otherwise. 284 if (isUndef() && getSubReg()) 285 OS << ",read-undef"; 286 } else if (isImplicit()) { 287 OS << "imp-use"; 288 NeedComma = true; 289 } 290 291 if (isKill()) { 292 if (NeedComma) OS << ','; 293 OS << "kill"; 294 NeedComma = true; 295 } 296 if (isDead()) { 297 if (NeedComma) OS << ','; 298 OS << "dead"; 299 NeedComma = true; 300 } 301 if (isUndef() && isUse()) { 302 if (NeedComma) OS << ','; 303 OS << "undef"; 304 NeedComma = true; 305 } 306 if (isInternalRead()) { 307 if (NeedComma) OS << ','; 308 OS << "internal"; 309 NeedComma = true; 310 } 311 if (isTied()) { 312 if (NeedComma) OS << ','; 313 OS << "tied"; 314 if (TiedTo != 15) 315 OS << unsigned(TiedTo - 1); 316 NeedComma = true; 317 } 318 OS << '>'; 319 } 320 break; 321 case MachineOperand::MO_Immediate: 322 OS << getImm(); 323 break; 324 case MachineOperand::MO_CImmediate: 325 getCImm()->getValue().print(OS, false); 326 break; 327 case MachineOperand::MO_FPImmediate: 328 if (getFPImm()->getType()->isFloatTy()) 329 OS << getFPImm()->getValueAPF().convertToFloat(); 330 else 331 OS << getFPImm()->getValueAPF().convertToDouble(); 332 break; 333 case MachineOperand::MO_MachineBasicBlock: 334 OS << "<BB#" << getMBB()->getNumber() << ">"; 335 break; 336 case MachineOperand::MO_FrameIndex: 337 OS << "<fi#" << getIndex() << '>'; 338 break; 339 case MachineOperand::MO_ConstantPoolIndex: 340 OS << "<cp#" << getIndex(); 341 if (getOffset()) OS << "+" << getOffset(); 342 OS << '>'; 343 break; 344 case MachineOperand::MO_TargetIndex: 345 OS << "<ti#" << getIndex(); 346 if (getOffset()) OS << "+" << getOffset(); 347 OS << '>'; 348 break; 349 case MachineOperand::MO_JumpTableIndex: 350 OS << "<jt#" << getIndex() << '>'; 351 break; 352 case MachineOperand::MO_GlobalAddress: 353 OS << "<ga:"; 354 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 355 if (getOffset()) OS << "+" << getOffset(); 356 OS << '>'; 357 break; 358 case MachineOperand::MO_ExternalSymbol: 359 OS << "<es:" << getSymbolName(); 360 if (getOffset()) OS << "+" << getOffset(); 361 OS << '>'; 362 break; 363 case MachineOperand::MO_BlockAddress: 364 OS << '<'; 365 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 366 if (getOffset()) OS << "+" << getOffset(); 367 OS << '>'; 368 break; 369 case MachineOperand::MO_RegisterMask: 370 OS << "<regmask>"; 371 break; 372 case MachineOperand::MO_Metadata: 373 OS << '<'; 374 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 375 OS << '>'; 376 break; 377 case MachineOperand::MO_MCSymbol: 378 OS << "<MCSym=" << *getMCSymbol() << '>'; 379 break; 380 } 381 382 if (unsigned TF = getTargetFlags()) 383 OS << "[TF=" << TF << ']'; 384} 385 386//===----------------------------------------------------------------------===// 387// MachineMemOperand Implementation 388//===----------------------------------------------------------------------===// 389 390/// getAddrSpace - Return the LLVM IR address space number that this pointer 391/// points into. 392unsigned MachinePointerInfo::getAddrSpace() const { 393 if (V == 0) return 0; 394 return cast<PointerType>(V->getType())->getAddressSpace(); 395} 396 397/// getConstantPool - Return a MachinePointerInfo record that refers to the 398/// constant pool. 399MachinePointerInfo MachinePointerInfo::getConstantPool() { 400 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 401} 402 403/// getFixedStack - Return a MachinePointerInfo record that refers to the 404/// the specified FrameIndex. 405MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 406 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 407} 408 409MachinePointerInfo MachinePointerInfo::getJumpTable() { 410 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 411} 412 413MachinePointerInfo MachinePointerInfo::getGOT() { 414 return MachinePointerInfo(PseudoSourceValue::getGOT()); 415} 416 417MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 418 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 419} 420 421MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 422 uint64_t s, unsigned int a, 423 const MDNode *TBAAInfo, 424 const MDNode *Ranges) 425 : PtrInfo(ptrinfo), Size(s), 426 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 427 TBAAInfo(TBAAInfo), Ranges(Ranges) { 428 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 429 "invalid pointer value"); 430 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 431 assert((isLoad() || isStore()) && "Not a load/store!"); 432} 433 434/// Profile - Gather unique data for the object. 435/// 436void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 437 ID.AddInteger(getOffset()); 438 ID.AddInteger(Size); 439 ID.AddPointer(getValue()); 440 ID.AddInteger(Flags); 441} 442 443void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 444 // The Value and Offset may differ due to CSE. But the flags and size 445 // should be the same. 446 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 447 assert(MMO->getSize() == getSize() && "Size mismatch!"); 448 449 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 450 // Update the alignment value. 451 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 452 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 453 // Also update the base and offset, because the new alignment may 454 // not be applicable with the old ones. 455 PtrInfo = MMO->PtrInfo; 456 } 457} 458 459/// getAlignment - Return the minimum known alignment in bytes of the 460/// actual memory reference. 461uint64_t MachineMemOperand::getAlignment() const { 462 return MinAlign(getBaseAlignment(), getOffset()); 463} 464 465raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 466 assert((MMO.isLoad() || MMO.isStore()) && 467 "SV has to be a load, store or both."); 468 469 if (MMO.isVolatile()) 470 OS << "Volatile "; 471 472 if (MMO.isLoad()) 473 OS << "LD"; 474 if (MMO.isStore()) 475 OS << "ST"; 476 OS << MMO.getSize(); 477 478 // Print the address information. 479 OS << "["; 480 if (!MMO.getValue()) 481 OS << "<unknown>"; 482 else 483 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 484 485 // If the alignment of the memory reference itself differs from the alignment 486 // of the base pointer, print the base alignment explicitly, next to the base 487 // pointer. 488 if (MMO.getBaseAlignment() != MMO.getAlignment()) 489 OS << "(align=" << MMO.getBaseAlignment() << ")"; 490 491 if (MMO.getOffset() != 0) 492 OS << "+" << MMO.getOffset(); 493 OS << "]"; 494 495 // Print the alignment of the reference. 496 if (MMO.getBaseAlignment() != MMO.getAlignment() || 497 MMO.getBaseAlignment() != MMO.getSize()) 498 OS << "(align=" << MMO.getAlignment() << ")"; 499 500 // Print TBAA info. 501 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 502 OS << "(tbaa="; 503 if (TBAAInfo->getNumOperands() > 0) 504 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 505 else 506 OS << "<unknown>"; 507 OS << ")"; 508 } 509 510 // Print nontemporal info. 511 if (MMO.isNonTemporal()) 512 OS << "(nontemporal)"; 513 514 return OS; 515} 516 517//===----------------------------------------------------------------------===// 518// MachineInstr Implementation 519//===----------------------------------------------------------------------===// 520 521void MachineInstr::addImplicitDefUseOperands() { 522 if (MCID->ImplicitDefs) 523 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 524 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); 525 if (MCID->ImplicitUses) 526 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 527 addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); 528} 529 530/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 531/// implicit operands. It reserves space for the number of operands specified by 532/// the MCInstrDesc. 533MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, 534 bool NoImp) 535 : MCID(&tid), Flags(0), AsmPrinterFlags(0), 536 NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) { 537 unsigned NumImplicitOps = 0; 538 if (!NoImp) 539 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); 540 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); 541 if (!NoImp) 542 addImplicitDefUseOperands(); 543 // Make sure that we get added to a machine basicblock 544 LeakDetector::addGarbageObject(this); 545} 546 547/// MachineInstr ctor - Copies MachineInstr arg exactly 548/// 549MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 550 : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0), 551 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), 552 Parent(0), debugLoc(MI.getDebugLoc()) { 553 Operands.reserve(MI.getNumOperands()); 554 555 // Add operands 556 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 557 addOperand(MI.getOperand(i)); 558 559 // Copy all the flags. 560 Flags = MI.Flags; 561 562 // Set parent to null. 563 Parent = 0; 564 565 LeakDetector::addGarbageObject(this); 566} 567 568MachineInstr::~MachineInstr() { 569 LeakDetector::removeGarbageObject(this); 570#ifndef NDEBUG 571 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { 572 assert(Operands[i].ParentMI == this && "ParentMI mismatch!"); 573 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && 574 "Reg operand def/use list corrupted"); 575 } 576#endif 577} 578 579/// getRegInfo - If this instruction is embedded into a MachineFunction, 580/// return the MachineRegisterInfo object for the current function, otherwise 581/// return null. 582MachineRegisterInfo *MachineInstr::getRegInfo() { 583 if (MachineBasicBlock *MBB = getParent()) 584 return &MBB->getParent()->getRegInfo(); 585 return 0; 586} 587 588/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 589/// this instruction from their respective use lists. This requires that the 590/// operands already be on their use lists. 591void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { 592 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 593 if (Operands[i].isReg()) 594 MRI.removeRegOperandFromUseList(&Operands[i]); 595} 596 597/// AddRegOperandsToUseLists - Add all of the register operands in 598/// this instruction from their respective use lists. This requires that the 599/// operands not be on their use lists yet. 600void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { 601 for (unsigned i = 0, e = Operands.size(); i != e; ++i) 602 if (Operands[i].isReg()) 603 MRI.addRegOperandToUseList(&Operands[i]); 604} 605 606/// addOperand - Add the specified operand to the instruction. If it is an 607/// implicit operand, it is added to the end of the operand list. If it is 608/// an explicit operand it is added at the end of the explicit operand list 609/// (before the first implicit operand). 610void MachineInstr::addOperand(const MachineOperand &Op) { 611 assert(MCID && "Cannot add operands before providing an instr descriptor"); 612 bool isImpReg = Op.isReg() && Op.isImplicit(); 613 MachineRegisterInfo *RegInfo = getRegInfo(); 614 615 // If the Operands backing store is reallocated, all register operands must 616 // be removed and re-added to RegInfo. It is storing pointers to operands. 617 bool Reallocate = RegInfo && 618 !Operands.empty() && Operands.size() == Operands.capacity(); 619 620 // Find the insert location for the new operand. Implicit registers go at 621 // the end, everything goes before the implicit regs. 622 unsigned OpNo = Operands.size(); 623 624 // Remove all the implicit operands from RegInfo if they need to be shifted. 625 // FIXME: Allow mixed explicit and implicit operands on inline asm. 626 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 627 // implicit-defs, but they must not be moved around. See the FIXME in 628 // InstrEmitter.cpp. 629 if (!isImpReg && !isInlineAsm()) { 630 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 631 --OpNo; 632 assert(!Operands[OpNo].isTied() && "Cannot move tied operands"); 633 if (RegInfo) 634 RegInfo->removeRegOperandFromUseList(&Operands[OpNo]); 635 } 636 } 637 638 // OpNo now points as the desired insertion point. Unless this is a variadic 639 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 640 // RegMask operands go between the explicit and implicit operands. 641 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 642 OpNo < MCID->getNumOperands()) && 643 "Trying to add an operand to a machine instr that is already done!"); 644 645 // All operands from OpNo have been removed from RegInfo. If the Operands 646 // backing store needs to be reallocated, we also need to remove any other 647 // register operands. 648 if (Reallocate) 649 for (unsigned i = 0; i != OpNo; ++i) 650 if (Operands[i].isReg()) 651 RegInfo->removeRegOperandFromUseList(&Operands[i]); 652 653 // Insert the new operand at OpNo. 654 Operands.insert(Operands.begin() + OpNo, Op); 655 Operands[OpNo].ParentMI = this; 656 657 // The Operands backing store has now been reallocated, so we can re-add the 658 // operands before OpNo. 659 if (Reallocate) 660 for (unsigned i = 0; i != OpNo; ++i) 661 if (Operands[i].isReg()) 662 RegInfo->addRegOperandToUseList(&Operands[i]); 663 664 // When adding a register operand, tell RegInfo about it. 665 if (Operands[OpNo].isReg()) { 666 // Ensure isOnRegUseList() returns false, regardless of Op's status. 667 Operands[OpNo].Contents.Reg.Prev = 0; 668 // Ignore existing ties. This is not a property that can be copied. 669 Operands[OpNo].TiedTo = 0; 670 // Add the new operand to RegInfo. 671 if (RegInfo) 672 RegInfo->addRegOperandToUseList(&Operands[OpNo]); 673 // The MCID operand information isn't accurate until we start adding 674 // explicit operands. The implicit operands are added first, then the 675 // explicits are inserted before them. 676 if (!isImpReg) { 677 // Tie uses to defs as indicated in MCInstrDesc. 678 if (Operands[OpNo].isUse()) { 679 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); 680 if (DefIdx != -1) 681 tieOperands(DefIdx, OpNo); 682 } 683 // If the register operand is flagged as early, mark the operand as such. 684 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 685 Operands[OpNo].setIsEarlyClobber(true); 686 } 687 } 688 689 // Re-add all the implicit ops. 690 if (RegInfo) { 691 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) { 692 assert(Operands[i].isReg() && "Should only be an implicit reg!"); 693 RegInfo->addRegOperandToUseList(&Operands[i]); 694 } 695 } 696} 697 698/// RemoveOperand - Erase an operand from an instruction, leaving it with one 699/// fewer operand than it started with. 700/// 701void MachineInstr::RemoveOperand(unsigned OpNo) { 702 assert(OpNo < Operands.size() && "Invalid operand number"); 703 untieRegOperand(OpNo); 704 MachineRegisterInfo *RegInfo = getRegInfo(); 705 706 // Special case removing the last one. 707 if (OpNo == Operands.size()-1) { 708 // If needed, remove from the reg def/use list. 709 if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList()) 710 RegInfo->removeRegOperandFromUseList(&Operands.back()); 711 712 Operands.pop_back(); 713 return; 714 } 715 716 // Otherwise, we are removing an interior operand. If we have reginfo to 717 // update, remove all operands that will be shifted down from their reg lists, 718 // move everything down, then re-add them. 719 if (RegInfo) { 720 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 721 if (Operands[i].isReg()) 722 RegInfo->removeRegOperandFromUseList(&Operands[i]); 723 } 724 } 725 726#ifndef NDEBUG 727 // Moving tied operands would break the ties. 728 for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) 729 if (Operands[i].isReg()) 730 assert(!Operands[i].isTied() && "Cannot move tied operands"); 731#endif 732 733 Operands.erase(Operands.begin()+OpNo); 734 735 if (RegInfo) { 736 for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) { 737 if (Operands[i].isReg()) 738 RegInfo->addRegOperandToUseList(&Operands[i]); 739 } 740 } 741} 742 743/// addMemOperand - Add a MachineMemOperand to the machine instruction. 744/// This function should be used only occasionally. The setMemRefs function 745/// is the primary method for setting up a MachineInstr's MemRefs list. 746void MachineInstr::addMemOperand(MachineFunction &MF, 747 MachineMemOperand *MO) { 748 mmo_iterator OldMemRefs = MemRefs; 749 uint16_t OldNumMemRefs = NumMemRefs; 750 751 uint16_t NewNum = NumMemRefs + 1; 752 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 753 754 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs); 755 NewMemRefs[NewNum - 1] = MO; 756 757 MemRefs = NewMemRefs; 758 NumMemRefs = NewNum; 759} 760 761bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { 762 const MachineBasicBlock *MBB = getParent(); 763 MachineBasicBlock::const_instr_iterator MII = *this; ++MII; 764 while (MII != MBB->end() && MII->isInsideBundle()) { 765 if (MII->getDesc().getFlags() & Mask) { 766 if (Type == AnyInBundle) 767 return true; 768 } else { 769 if (Type == AllInBundle) 770 return false; 771 } 772 ++MII; 773 } 774 775 return Type == AllInBundle; 776} 777 778bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 779 MICheckType Check) const { 780 // If opcodes or number of operands are not the same then the two 781 // instructions are obviously not identical. 782 if (Other->getOpcode() != getOpcode() || 783 Other->getNumOperands() != getNumOperands()) 784 return false; 785 786 if (isBundle()) { 787 // Both instructions are bundles, compare MIs inside the bundle. 788 MachineBasicBlock::const_instr_iterator I1 = *this; 789 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); 790 MachineBasicBlock::const_instr_iterator I2 = *Other; 791 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); 792 while (++I1 != E1 && I1->isInsideBundle()) { 793 ++I2; 794 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check)) 795 return false; 796 } 797 } 798 799 // Check operands to make sure they match. 800 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 801 const MachineOperand &MO = getOperand(i); 802 const MachineOperand &OMO = Other->getOperand(i); 803 if (!MO.isReg()) { 804 if (!MO.isIdenticalTo(OMO)) 805 return false; 806 continue; 807 } 808 809 // Clients may or may not want to ignore defs when testing for equality. 810 // For example, machine CSE pass only cares about finding common 811 // subexpressions, so it's safe to ignore virtual register defs. 812 if (MO.isDef()) { 813 if (Check == IgnoreDefs) 814 continue; 815 else if (Check == IgnoreVRegDefs) { 816 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 817 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 818 if (MO.getReg() != OMO.getReg()) 819 return false; 820 } else { 821 if (!MO.isIdenticalTo(OMO)) 822 return false; 823 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 824 return false; 825 } 826 } else { 827 if (!MO.isIdenticalTo(OMO)) 828 return false; 829 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 830 return false; 831 } 832 } 833 // If DebugLoc does not match then two dbg.values are not identical. 834 if (isDebugValue()) 835 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 836 && getDebugLoc() != Other->getDebugLoc()) 837 return false; 838 return true; 839} 840 841MachineInstr *MachineInstr::removeFromParent() { 842 assert(getParent() && "Not embedded in a basic block!"); 843 return getParent()->remove(this); 844} 845 846MachineInstr *MachineInstr::removeFromBundle() { 847 assert(getParent() && "Not embedded in a basic block!"); 848 return getParent()->remove_instr(this); 849} 850 851void MachineInstr::eraseFromParent() { 852 assert(getParent() && "Not embedded in a basic block!"); 853 getParent()->erase(this); 854} 855 856void MachineInstr::eraseFromBundle() { 857 assert(getParent() && "Not embedded in a basic block!"); 858 getParent()->erase_instr(this); 859} 860 861/// getNumExplicitOperands - Returns the number of non-implicit operands. 862/// 863unsigned MachineInstr::getNumExplicitOperands() const { 864 unsigned NumOperands = MCID->getNumOperands(); 865 if (!MCID->isVariadic()) 866 return NumOperands; 867 868 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 869 const MachineOperand &MO = getOperand(i); 870 if (!MO.isReg() || !MO.isImplicit()) 871 NumOperands++; 872 } 873 return NumOperands; 874} 875 876void MachineInstr::bundleWithPred() { 877 assert(!isBundledWithPred() && "MI is already bundled with its predecessor"); 878 setFlag(BundledPred); 879 MachineBasicBlock::instr_iterator Pred = this; 880 --Pred; 881 Pred->setFlag(BundledSucc); 882} 883 884void MachineInstr::bundleWithSucc() { 885 assert(!isBundledWithSucc() && "MI is already bundled with its successor"); 886 setFlag(BundledSucc); 887 MachineBasicBlock::instr_iterator Succ = this; 888 ++Succ; 889 Succ->setFlag(BundledPred); 890} 891 892void MachineInstr::unbundleFromPred() { 893 assert(isBundledWithPred() && "MI isn't bundled with its predecessor"); 894 clearFlag(BundledPred); 895 MachineBasicBlock::instr_iterator Pred = this; 896 --Pred; 897 Pred->clearFlag(BundledSucc); 898} 899 900void MachineInstr::unbundleFromSucc() { 901 assert(isBundledWithSucc() && "MI isn't bundled with its successor"); 902 clearFlag(BundledSucc); 903 MachineBasicBlock::instr_iterator Succ = this; 904 --Succ; 905 Succ->clearFlag(BundledPred); 906} 907 908/// isBundled - Return true if this instruction part of a bundle. This is true 909/// if either itself or its following instruction is marked "InsideBundle". 910bool MachineInstr::isBundled() const { 911 if (isInsideBundle()) 912 return true; 913 MachineBasicBlock::const_instr_iterator nextMI = this; 914 ++nextMI; 915 return nextMI != Parent->instr_end() && nextMI->isInsideBundle(); 916} 917 918bool MachineInstr::isStackAligningInlineAsm() const { 919 if (isInlineAsm()) { 920 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 921 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 922 return true; 923 } 924 return false; 925} 926 927InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { 928 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"); 929 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 930 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); 931} 932 933int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 934 unsigned *GroupNo) const { 935 assert(isInlineAsm() && "Expected an inline asm instruction"); 936 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 937 938 // Ignore queries about the initial operands. 939 if (OpIdx < InlineAsm::MIOp_FirstOperand) 940 return -1; 941 942 unsigned Group = 0; 943 unsigned NumOps; 944 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 945 i += NumOps) { 946 const MachineOperand &FlagMO = getOperand(i); 947 // If we reach the implicit register operands, stop looking. 948 if (!FlagMO.isImm()) 949 return -1; 950 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 951 if (i + NumOps > OpIdx) { 952 if (GroupNo) 953 *GroupNo = Group; 954 return i; 955 } 956 ++Group; 957 } 958 return -1; 959} 960 961const TargetRegisterClass* 962MachineInstr::getRegClassConstraint(unsigned OpIdx, 963 const TargetInstrInfo *TII, 964 const TargetRegisterInfo *TRI) const { 965 assert(getParent() && "Can't have an MBB reference here!"); 966 assert(getParent()->getParent() && "Can't have an MF reference here!"); 967 const MachineFunction &MF = *getParent()->getParent(); 968 969 // Most opcodes have fixed constraints in their MCInstrDesc. 970 if (!isInlineAsm()) 971 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 972 973 if (!getOperand(OpIdx).isReg()) 974 return NULL; 975 976 // For tied uses on inline asm, get the constraint from the def. 977 unsigned DefIdx; 978 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 979 OpIdx = DefIdx; 980 981 // Inline asm stores register class constraints in the flag word. 982 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 983 if (FlagIdx < 0) 984 return NULL; 985 986 unsigned Flag = getOperand(FlagIdx).getImm(); 987 unsigned RCID; 988 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 989 return TRI->getRegClass(RCID); 990 991 // Assume that all registers in a memory operand are pointers. 992 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 993 return TRI->getPointerRegClass(MF); 994 995 return NULL; 996} 997 998/// getBundleSize - Return the number of instructions inside the MI bundle. 999unsigned MachineInstr::getBundleSize() const { 1000 assert(isBundle() && "Expecting a bundle"); 1001 1002 const MachineBasicBlock *MBB = getParent(); 1003 MachineBasicBlock::const_instr_iterator I = *this, E = MBB->instr_end(); 1004 unsigned Size = 0; 1005 while ((++I != E) && I->isInsideBundle()) { 1006 ++Size; 1007 } 1008 assert(Size > 1 && "Malformed bundle"); 1009 1010 return Size; 1011} 1012 1013/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 1014/// the specific register or -1 if it is not found. It further tightens 1015/// the search criteria to a use that kills the register if isKill is true. 1016int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 1017 const TargetRegisterInfo *TRI) const { 1018 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1019 const MachineOperand &MO = getOperand(i); 1020 if (!MO.isReg() || !MO.isUse()) 1021 continue; 1022 unsigned MOReg = MO.getReg(); 1023 if (!MOReg) 1024 continue; 1025 if (MOReg == Reg || 1026 (TRI && 1027 TargetRegisterInfo::isPhysicalRegister(MOReg) && 1028 TargetRegisterInfo::isPhysicalRegister(Reg) && 1029 TRI->isSubRegister(MOReg, Reg))) 1030 if (!isKill || MO.isKill()) 1031 return i; 1032 } 1033 return -1; 1034} 1035 1036/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1037/// indicating if this instruction reads or writes Reg. This also considers 1038/// partial defines. 1039std::pair<bool,bool> 1040MachineInstr::readsWritesVirtualRegister(unsigned Reg, 1041 SmallVectorImpl<unsigned> *Ops) const { 1042 bool PartDef = false; // Partial redefine. 1043 bool FullDef = false; // Full define. 1044 bool Use = false; 1045 1046 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1047 const MachineOperand &MO = getOperand(i); 1048 if (!MO.isReg() || MO.getReg() != Reg) 1049 continue; 1050 if (Ops) 1051 Ops->push_back(i); 1052 if (MO.isUse()) 1053 Use |= !MO.isUndef(); 1054 else if (MO.getSubReg() && !MO.isUndef()) 1055 // A partial <def,undef> doesn't count as reading the register. 1056 PartDef = true; 1057 else 1058 FullDef = true; 1059 } 1060 // A partial redefine uses Reg unless there is also a full define. 1061 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1062} 1063 1064/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1065/// the specified register or -1 if it is not found. If isDead is true, defs 1066/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1067/// also checks if there is a def of a super-register. 1068int 1069MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 1070 const TargetRegisterInfo *TRI) const { 1071 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 1072 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1073 const MachineOperand &MO = getOperand(i); 1074 // Accept regmask operands when Overlap is set. 1075 // Ignore them when looking for a specific def operand (Overlap == false). 1076 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1077 return i; 1078 if (!MO.isReg() || !MO.isDef()) 1079 continue; 1080 unsigned MOReg = MO.getReg(); 1081 bool Found = (MOReg == Reg); 1082 if (!Found && TRI && isPhys && 1083 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1084 if (Overlap) 1085 Found = TRI->regsOverlap(MOReg, Reg); 1086 else 1087 Found = TRI->isSubRegister(MOReg, Reg); 1088 } 1089 if (Found && (!isDead || MO.isDead())) 1090 return i; 1091 } 1092 return -1; 1093} 1094 1095/// findFirstPredOperandIdx() - Find the index of the first operand in the 1096/// operand list that is used to represent the predicate. It returns -1 if 1097/// none is found. 1098int MachineInstr::findFirstPredOperandIdx() const { 1099 // Don't call MCID.findFirstPredOperandIdx() because this variant 1100 // is sometimes called on an instruction that's not yet complete, and 1101 // so the number of operands is less than the MCID indicates. In 1102 // particular, the PTX target does this. 1103 const MCInstrDesc &MCID = getDesc(); 1104 if (MCID.isPredicable()) { 1105 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1106 if (MCID.OpInfo[i].isPredicate()) 1107 return i; 1108 } 1109 1110 return -1; 1111} 1112 1113// MachineOperand::TiedTo is 4 bits wide. 1114const unsigned TiedMax = 15; 1115 1116/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1117/// 1118/// Use and def operands can be tied together, indicated by a non-zero TiedTo 1119/// field. TiedTo can have these values: 1120/// 1121/// 0: Operand is not tied to anything. 1122/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). 1123/// TiedMax: Tied to an operand >= TiedMax-1. 1124/// 1125/// The tied def must be one of the first TiedMax operands on a normal 1126/// instruction. INLINEASM instructions allow more tied defs. 1127/// 1128void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { 1129 MachineOperand &DefMO = getOperand(DefIdx); 1130 MachineOperand &UseMO = getOperand(UseIdx); 1131 assert(DefMO.isDef() && "DefIdx must be a def operand"); 1132 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1133 assert(!DefMO.isTied() && "Def is already tied to another use"); 1134 assert(!UseMO.isTied() && "Use is already tied to another def"); 1135 1136 if (DefIdx < TiedMax) 1137 UseMO.TiedTo = DefIdx + 1; 1138 else { 1139 // Inline asm can use the group descriptors to find tied operands, but on 1140 // normal instruction, the tied def must be within the first TiedMax 1141 // operands. 1142 assert(isInlineAsm() && "DefIdx out of range"); 1143 UseMO.TiedTo = TiedMax; 1144 } 1145 1146 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1147 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); 1148} 1149 1150/// Given the index of a tied register operand, find the operand it is tied to. 1151/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1152/// which must exist. 1153unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { 1154 const MachineOperand &MO = getOperand(OpIdx); 1155 assert(MO.isTied() && "Operand isn't tied"); 1156 1157 // Normally TiedTo is in range. 1158 if (MO.TiedTo < TiedMax) 1159 return MO.TiedTo - 1; 1160 1161 // Uses on normal instructions can be out of range. 1162 if (!isInlineAsm()) { 1163 // Normal tied defs must be in the 0..TiedMax-1 range. 1164 if (MO.isUse()) 1165 return TiedMax - 1; 1166 // MO is a def. Search for the tied use. 1167 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { 1168 const MachineOperand &UseMO = getOperand(i); 1169 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) 1170 return i; 1171 } 1172 llvm_unreachable("Can't find tied use"); 1173 } 1174 1175 // Now deal with inline asm by parsing the operand group descriptor flags. 1176 // Find the beginning of each operand group. 1177 SmallVector<unsigned, 8> GroupIdx; 1178 unsigned OpIdxGroup = ~0u; 1179 unsigned NumOps; 1180 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 1181 i += NumOps) { 1182 const MachineOperand &FlagMO = getOperand(i); 1183 assert(FlagMO.isImm() && "Invalid tied operand on inline asm"); 1184 unsigned CurGroup = GroupIdx.size(); 1185 GroupIdx.push_back(i); 1186 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 1187 // OpIdx belongs to this operand group. 1188 if (OpIdx > i && OpIdx < i + NumOps) 1189 OpIdxGroup = CurGroup; 1190 unsigned TiedGroup; 1191 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) 1192 continue; 1193 // Operands in this group are tied to operands in TiedGroup which must be 1194 // earlier. Find the number of operands between the two groups. 1195 unsigned Delta = i - GroupIdx[TiedGroup]; 1196 1197 // OpIdx is a use tied to TiedGroup. 1198 if (OpIdxGroup == CurGroup) 1199 return OpIdx - Delta; 1200 1201 // OpIdx is a def tied to this use group. 1202 if (OpIdxGroup == TiedGroup) 1203 return OpIdx + Delta; 1204 } 1205 llvm_unreachable("Invalid tied operand on inline asm"); 1206} 1207 1208/// clearKillInfo - Clears kill flags on all operands. 1209/// 1210void MachineInstr::clearKillInfo() { 1211 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1212 MachineOperand &MO = getOperand(i); 1213 if (MO.isReg() && MO.isUse()) 1214 MO.setIsKill(false); 1215 } 1216} 1217 1218/// copyKillDeadInfo - Copies kill / dead operand properties from MI. 1219/// 1220void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) { 1221 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1222 const MachineOperand &MO = MI->getOperand(i); 1223 if (!MO.isReg() || (!MO.isKill() && !MO.isDead())) 1224 continue; 1225 for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) { 1226 MachineOperand &MOp = getOperand(j); 1227 if (!MOp.isIdenticalTo(MO)) 1228 continue; 1229 if (MO.isKill()) 1230 MOp.setIsKill(); 1231 else 1232 MOp.setIsDead(); 1233 break; 1234 } 1235 } 1236} 1237 1238/// copyPredicates - Copies predicate operand(s) from MI. 1239void MachineInstr::copyPredicates(const MachineInstr *MI) { 1240 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles"); 1241 1242 const MCInstrDesc &MCID = MI->getDesc(); 1243 if (!MCID.isPredicable()) 1244 return; 1245 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1246 if (MCID.OpInfo[i].isPredicate()) { 1247 // Predicated operands must be last operands. 1248 addOperand(MI->getOperand(i)); 1249 } 1250 } 1251} 1252 1253void MachineInstr::substituteRegister(unsigned FromReg, 1254 unsigned ToReg, 1255 unsigned SubIdx, 1256 const TargetRegisterInfo &RegInfo) { 1257 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1258 if (SubIdx) 1259 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1260 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1261 MachineOperand &MO = getOperand(i); 1262 if (!MO.isReg() || MO.getReg() != FromReg) 1263 continue; 1264 MO.substPhysReg(ToReg, RegInfo); 1265 } 1266 } else { 1267 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1268 MachineOperand &MO = getOperand(i); 1269 if (!MO.isReg() || MO.getReg() != FromReg) 1270 continue; 1271 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1272 } 1273 } 1274} 1275 1276/// isSafeToMove - Return true if it is safe to move this instruction. If 1277/// SawStore is set to true, it means that there is a store (or call) between 1278/// the instruction's location and its intended destination. 1279bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1280 AliasAnalysis *AA, 1281 bool &SawStore) const { 1282 // Ignore stuff that we obviously can't move. 1283 // 1284 // Treat volatile loads as stores. This is not strictly necessary for 1285 // volatiles, but it is required for atomic loads. It is not allowed to move 1286 // a load across an atomic load with Ordering > Monotonic. 1287 if (mayStore() || isCall() || 1288 (mayLoad() && hasOrderedMemoryRef())) { 1289 SawStore = true; 1290 return false; 1291 } 1292 1293 if (isLabel() || isDebugValue() || 1294 isTerminator() || hasUnmodeledSideEffects()) 1295 return false; 1296 1297 // See if this instruction does a load. If so, we have to guarantee that the 1298 // loaded value doesn't change between the load and the its intended 1299 // destination. The check for isInvariantLoad gives the targe the chance to 1300 // classify the load as always returning a constant, e.g. a constant pool 1301 // load. 1302 if (mayLoad() && !isInvariantLoad(AA)) 1303 // Otherwise, this is a real load. If there is a store between the load and 1304 // end of block, we can't move it. 1305 return !SawStore; 1306 1307 return true; 1308} 1309 1310/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1311/// instruction which defined the specified register instead of copying it. 1312bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1313 AliasAnalysis *AA, 1314 unsigned DstReg) const { 1315 bool SawStore = false; 1316 if (!TII->isTriviallyReMaterializable(this, AA) || 1317 !isSafeToMove(TII, AA, SawStore)) 1318 return false; 1319 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1320 const MachineOperand &MO = getOperand(i); 1321 if (!MO.isReg()) 1322 continue; 1323 // FIXME: For now, do not remat any instruction with register operands. 1324 // Later on, we can loosen the restriction is the register operands have 1325 // not been modified between the def and use. Note, this is different from 1326 // MachineSink because the code is no longer in two-address form (at least 1327 // partially). 1328 if (MO.isUse()) 1329 return false; 1330 else if (!MO.isDead() && MO.getReg() != DstReg) 1331 return false; 1332 } 1333 return true; 1334} 1335 1336/// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1337/// or volatile memory reference, or if the information describing the memory 1338/// reference is not available. Return false if it is known to have no ordered 1339/// memory references. 1340bool MachineInstr::hasOrderedMemoryRef() const { 1341 // An instruction known never to access memory won't have a volatile access. 1342 if (!mayStore() && 1343 !mayLoad() && 1344 !isCall() && 1345 !hasUnmodeledSideEffects()) 1346 return false; 1347 1348 // Otherwise, if the instruction has no memory reference information, 1349 // conservatively assume it wasn't preserved. 1350 if (memoperands_empty()) 1351 return true; 1352 1353 // Check the memory reference information for ordered references. 1354 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1355 if (!(*I)->isUnordered()) 1356 return true; 1357 1358 return false; 1359} 1360 1361/// isInvariantLoad - Return true if this instruction is loading from a 1362/// location whose value is invariant across the function. For example, 1363/// loading a value from the constant pool or from the argument area 1364/// of a function if it does not change. This should only return true of 1365/// *all* loads the instruction does are invariant (if it does multiple loads). 1366bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1367 // If the instruction doesn't load at all, it isn't an invariant load. 1368 if (!mayLoad()) 1369 return false; 1370 1371 // If the instruction has lost its memoperands, conservatively assume that 1372 // it may not be an invariant load. 1373 if (memoperands_empty()) 1374 return false; 1375 1376 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1377 1378 for (mmo_iterator I = memoperands_begin(), 1379 E = memoperands_end(); I != E; ++I) { 1380 if ((*I)->isVolatile()) return false; 1381 if ((*I)->isStore()) return false; 1382 if ((*I)->isInvariant()) return true; 1383 1384 if (const Value *V = (*I)->getValue()) { 1385 // A load from a constant PseudoSourceValue is invariant. 1386 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1387 if (PSV->isConstant(MFI)) 1388 continue; 1389 // If we have an AliasAnalysis, ask it whether the memory is constant. 1390 if (AA && AA->pointsToConstantMemory( 1391 AliasAnalysis::Location(V, (*I)->getSize(), 1392 (*I)->getTBAAInfo()))) 1393 continue; 1394 } 1395 1396 // Otherwise assume conservatively. 1397 return false; 1398 } 1399 1400 // Everything checks out. 1401 return true; 1402} 1403 1404/// isConstantValuePHI - If the specified instruction is a PHI that always 1405/// merges together the same virtual register, return the register, otherwise 1406/// return 0. 1407unsigned MachineInstr::isConstantValuePHI() const { 1408 if (!isPHI()) 1409 return 0; 1410 assert(getNumOperands() >= 3 && 1411 "It's illegal to have a PHI without source operands"); 1412 1413 unsigned Reg = getOperand(1).getReg(); 1414 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1415 if (getOperand(i).getReg() != Reg) 1416 return 0; 1417 return Reg; 1418} 1419 1420bool MachineInstr::hasUnmodeledSideEffects() const { 1421 if (hasProperty(MCID::UnmodeledSideEffects)) 1422 return true; 1423 if (isInlineAsm()) { 1424 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1425 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1426 return true; 1427 } 1428 1429 return false; 1430} 1431 1432/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1433/// 1434bool MachineInstr::allDefsAreDead() const { 1435 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1436 const MachineOperand &MO = getOperand(i); 1437 if (!MO.isReg() || MO.isUse()) 1438 continue; 1439 if (!MO.isDead()) 1440 return false; 1441 } 1442 return true; 1443} 1444 1445/// copyImplicitOps - Copy implicit register operands from specified 1446/// instruction to this instruction. 1447void MachineInstr::copyImplicitOps(const MachineInstr *MI) { 1448 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1449 i != e; ++i) { 1450 const MachineOperand &MO = MI->getOperand(i); 1451 if (MO.isReg() && MO.isImplicit()) 1452 addOperand(MO); 1453 } 1454} 1455 1456void MachineInstr::dump() const { 1457#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1458 dbgs() << " " << *this; 1459#endif 1460} 1461 1462static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1463 raw_ostream &CommentOS) { 1464 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1465 if (!DL.isUnknown()) { // Print source line info. 1466 DIScope Scope(DL.getScope(Ctx)); 1467 // Omit the directory, because it's likely to be long and uninteresting. 1468 if (Scope.Verify()) 1469 CommentOS << Scope.getFilename(); 1470 else 1471 CommentOS << "<unknown>"; 1472 CommentOS << ':' << DL.getLine(); 1473 if (DL.getCol() != 0) 1474 CommentOS << ':' << DL.getCol(); 1475 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1476 if (!InlinedAtDL.isUnknown()) { 1477 CommentOS << " @[ "; 1478 printDebugLoc(InlinedAtDL, MF, CommentOS); 1479 CommentOS << " ]"; 1480 } 1481 } 1482} 1483 1484void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1485 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1486 const MachineFunction *MF = 0; 1487 const MachineRegisterInfo *MRI = 0; 1488 if (const MachineBasicBlock *MBB = getParent()) { 1489 MF = MBB->getParent(); 1490 if (!TM && MF) 1491 TM = &MF->getTarget(); 1492 if (MF) 1493 MRI = &MF->getRegInfo(); 1494 } 1495 1496 // Save a list of virtual registers. 1497 SmallVector<unsigned, 8> VirtRegs; 1498 1499 // Print explicitly defined operands on the left of an assignment syntax. 1500 unsigned StartOp = 0, e = getNumOperands(); 1501 for (; StartOp < e && getOperand(StartOp).isReg() && 1502 getOperand(StartOp).isDef() && 1503 !getOperand(StartOp).isImplicit(); 1504 ++StartOp) { 1505 if (StartOp != 0) OS << ", "; 1506 getOperand(StartOp).print(OS, TM); 1507 unsigned Reg = getOperand(StartOp).getReg(); 1508 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1509 VirtRegs.push_back(Reg); 1510 } 1511 1512 if (StartOp != 0) 1513 OS << " = "; 1514 1515 // Print the opcode name. 1516 if (TM && TM->getInstrInfo()) 1517 OS << TM->getInstrInfo()->getName(getOpcode()); 1518 else 1519 OS << "UNKNOWN"; 1520 1521 // Print the rest of the operands. 1522 bool OmittedAnyCallClobbers = false; 1523 bool FirstOp = true; 1524 unsigned AsmDescOp = ~0u; 1525 unsigned AsmOpCount = 0; 1526 1527 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1528 // Print asm string. 1529 OS << " "; 1530 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1531 1532 // Print HasSideEffects, IsAlignStack 1533 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1534 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1535 OS << " [sideeffect]"; 1536 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1537 OS << " [alignstack]"; 1538 if (getInlineAsmDialect() == InlineAsm::AD_ATT) 1539 OS << " [attdialect]"; 1540 if (getInlineAsmDialect() == InlineAsm::AD_Intel) 1541 OS << " [inteldialect]"; 1542 1543 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1544 FirstOp = false; 1545 } 1546 1547 1548 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1549 const MachineOperand &MO = getOperand(i); 1550 1551 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1552 VirtRegs.push_back(MO.getReg()); 1553 1554 // Omit call-clobbered registers which aren't used anywhere. This makes 1555 // call instructions much less noisy on targets where calls clobber lots 1556 // of registers. Don't rely on MO.isDead() because we may be called before 1557 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1558 if (MF && isCall() && 1559 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1560 unsigned Reg = MO.getReg(); 1561 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1562 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1563 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1564 bool HasAliasLive = false; 1565 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true); 1566 AI.isValid(); ++AI) { 1567 unsigned AliasReg = *AI; 1568 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1569 HasAliasLive = true; 1570 break; 1571 } 1572 } 1573 if (!HasAliasLive) { 1574 OmittedAnyCallClobbers = true; 1575 continue; 1576 } 1577 } 1578 } 1579 } 1580 1581 if (FirstOp) FirstOp = false; else OS << ","; 1582 OS << " "; 1583 if (i < getDesc().NumOperands) { 1584 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1585 if (MCOI.isPredicate()) 1586 OS << "pred:"; 1587 if (MCOI.isOptionalDef()) 1588 OS << "opt:"; 1589 } 1590 if (isDebugValue() && MO.isMetadata()) { 1591 // Pretty print DBG_VALUE instructions. 1592 const MDNode *MD = MO.getMetadata(); 1593 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1594 OS << "!\"" << MDS->getString() << '\"'; 1595 else 1596 MO.print(OS, TM); 1597 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1598 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1599 } else if (i == AsmDescOp && MO.isImm()) { 1600 // Pretty print the inline asm operand descriptor. 1601 OS << '$' << AsmOpCount++; 1602 unsigned Flag = MO.getImm(); 1603 switch (InlineAsm::getKind(Flag)) { 1604 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1605 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1606 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1607 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1608 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1609 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1610 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1611 } 1612 1613 unsigned RCID = 0; 1614 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1615 if (TM) 1616 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1617 else 1618 OS << ":RC" << RCID; 1619 } 1620 1621 unsigned TiedTo = 0; 1622 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1623 OS << " tiedto:$" << TiedTo; 1624 1625 OS << ']'; 1626 1627 // Compute the index of the next operand descriptor. 1628 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1629 } else 1630 MO.print(OS, TM); 1631 } 1632 1633 // Briefly indicate whether any call clobbers were omitted. 1634 if (OmittedAnyCallClobbers) { 1635 if (!FirstOp) OS << ","; 1636 OS << " ..."; 1637 } 1638 1639 bool HaveSemi = false; 1640 if (Flags) { 1641 if (!HaveSemi) OS << ";"; HaveSemi = true; 1642 OS << " flags: "; 1643 1644 if (Flags & FrameSetup) 1645 OS << "FrameSetup"; 1646 } 1647 1648 if (!memoperands_empty()) { 1649 if (!HaveSemi) OS << ";"; HaveSemi = true; 1650 1651 OS << " mem:"; 1652 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1653 i != e; ++i) { 1654 OS << **i; 1655 if (llvm::next(i) != e) 1656 OS << " "; 1657 } 1658 } 1659 1660 // Print the regclass of any virtual registers encountered. 1661 if (MRI && !VirtRegs.empty()) { 1662 if (!HaveSemi) OS << ";"; HaveSemi = true; 1663 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1664 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1665 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1666 for (unsigned j = i+1; j != VirtRegs.size();) { 1667 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1668 ++j; 1669 continue; 1670 } 1671 if (VirtRegs[i] != VirtRegs[j]) 1672 OS << "," << PrintReg(VirtRegs[j]); 1673 VirtRegs.erase(VirtRegs.begin()+j); 1674 } 1675 } 1676 } 1677 1678 // Print debug location information. 1679 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1680 if (!HaveSemi) OS << ";"; HaveSemi = true; 1681 DIVariable DV(getOperand(e - 1).getMetadata()); 1682 OS << " line no:" << DV.getLineNumber(); 1683 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1684 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1685 if (!InlinedAtDL.isUnknown()) { 1686 OS << " inlined @[ "; 1687 printDebugLoc(InlinedAtDL, MF, OS); 1688 OS << " ]"; 1689 } 1690 } 1691 } else if (!debugLoc.isUnknown() && MF) { 1692 if (!HaveSemi) OS << ";"; HaveSemi = true; 1693 OS << " dbg:"; 1694 printDebugLoc(debugLoc, MF, OS); 1695 } 1696 1697 OS << '\n'; 1698} 1699 1700bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1701 const TargetRegisterInfo *RegInfo, 1702 bool AddIfNotFound) { 1703 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1704 bool hasAliases = isPhysReg && 1705 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1706 bool Found = false; 1707 SmallVector<unsigned,4> DeadOps; 1708 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1709 MachineOperand &MO = getOperand(i); 1710 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1711 continue; 1712 unsigned Reg = MO.getReg(); 1713 if (!Reg) 1714 continue; 1715 1716 if (Reg == IncomingReg) { 1717 if (!Found) { 1718 if (MO.isKill()) 1719 // The register is already marked kill. 1720 return true; 1721 if (isPhysReg && isRegTiedToDefOperand(i)) 1722 // Two-address uses of physregs must not be marked kill. 1723 return true; 1724 MO.setIsKill(); 1725 Found = true; 1726 } 1727 } else if (hasAliases && MO.isKill() && 1728 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1729 // A super-register kill already exists. 1730 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1731 return true; 1732 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1733 DeadOps.push_back(i); 1734 } 1735 } 1736 1737 // Trim unneeded kill operands. 1738 while (!DeadOps.empty()) { 1739 unsigned OpIdx = DeadOps.back(); 1740 if (getOperand(OpIdx).isImplicit()) 1741 RemoveOperand(OpIdx); 1742 else 1743 getOperand(OpIdx).setIsKill(false); 1744 DeadOps.pop_back(); 1745 } 1746 1747 // If not found, this means an alias of one of the operands is killed. Add a 1748 // new implicit operand if required. 1749 if (!Found && AddIfNotFound) { 1750 addOperand(MachineOperand::CreateReg(IncomingReg, 1751 false /*IsDef*/, 1752 true /*IsImp*/, 1753 true /*IsKill*/)); 1754 return true; 1755 } 1756 return Found; 1757} 1758 1759void MachineInstr::clearRegisterKills(unsigned Reg, 1760 const TargetRegisterInfo *RegInfo) { 1761 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 1762 RegInfo = 0; 1763 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1764 MachineOperand &MO = getOperand(i); 1765 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1766 continue; 1767 unsigned OpReg = MO.getReg(); 1768 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) 1769 MO.setIsKill(false); 1770 } 1771} 1772 1773bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1774 const TargetRegisterInfo *RegInfo, 1775 bool AddIfNotFound) { 1776 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1777 bool hasAliases = isPhysReg && 1778 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1779 bool Found = false; 1780 SmallVector<unsigned,4> DeadOps; 1781 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1782 MachineOperand &MO = getOperand(i); 1783 if (!MO.isReg() || !MO.isDef()) 1784 continue; 1785 unsigned Reg = MO.getReg(); 1786 if (!Reg) 1787 continue; 1788 1789 if (Reg == IncomingReg) { 1790 MO.setIsDead(); 1791 Found = true; 1792 } else if (hasAliases && MO.isDead() && 1793 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1794 // There exists a super-register that's marked dead. 1795 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1796 return true; 1797 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1798 DeadOps.push_back(i); 1799 } 1800 } 1801 1802 // Trim unneeded dead operands. 1803 while (!DeadOps.empty()) { 1804 unsigned OpIdx = DeadOps.back(); 1805 if (getOperand(OpIdx).isImplicit()) 1806 RemoveOperand(OpIdx); 1807 else 1808 getOperand(OpIdx).setIsDead(false); 1809 DeadOps.pop_back(); 1810 } 1811 1812 // If not found, this means an alias of one of the operands is dead. Add a 1813 // new implicit operand if required. 1814 if (Found || !AddIfNotFound) 1815 return Found; 1816 1817 addOperand(MachineOperand::CreateReg(IncomingReg, 1818 true /*IsDef*/, 1819 true /*IsImp*/, 1820 false /*IsKill*/, 1821 true /*IsDead*/)); 1822 return true; 1823} 1824 1825void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1826 const TargetRegisterInfo *RegInfo) { 1827 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1828 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1829 if (MO) 1830 return; 1831 } else { 1832 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1833 const MachineOperand &MO = getOperand(i); 1834 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1835 MO.getSubReg() == 0) 1836 return; 1837 } 1838 } 1839 addOperand(MachineOperand::CreateReg(IncomingReg, 1840 true /*IsDef*/, 1841 true /*IsImp*/)); 1842} 1843 1844void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1845 const TargetRegisterInfo &TRI) { 1846 bool HasRegMask = false; 1847 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1848 MachineOperand &MO = getOperand(i); 1849 if (MO.isRegMask()) { 1850 HasRegMask = true; 1851 continue; 1852 } 1853 if (!MO.isReg() || !MO.isDef()) continue; 1854 unsigned Reg = MO.getReg(); 1855 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 1856 bool Dead = true; 1857 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1858 I != E; ++I) 1859 if (TRI.regsOverlap(*I, Reg)) { 1860 Dead = false; 1861 break; 1862 } 1863 // If there are no uses, including partial uses, the def is dead. 1864 if (Dead) MO.setIsDead(); 1865 } 1866 1867 // This is a call with a register mask operand. 1868 // Mask clobbers are always dead, so add defs for the non-dead defines. 1869 if (HasRegMask) 1870 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1871 I != E; ++I) 1872 addRegisterDefined(*I, &TRI); 1873} 1874 1875unsigned 1876MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1877 // Build up a buffer of hash code components. 1878 SmallVector<size_t, 8> HashComponents; 1879 HashComponents.reserve(MI->getNumOperands() + 1); 1880 HashComponents.push_back(MI->getOpcode()); 1881 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1882 const MachineOperand &MO = MI->getOperand(i); 1883 if (MO.isReg() && MO.isDef() && 1884 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1885 continue; // Skip virtual register defs. 1886 1887 HashComponents.push_back(hash_value(MO)); 1888 } 1889 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 1890} 1891 1892void MachineInstr::emitError(StringRef Msg) const { 1893 // Find the source location cookie. 1894 unsigned LocCookie = 0; 1895 const MDNode *LocMD = 0; 1896 for (unsigned i = getNumOperands(); i != 0; --i) { 1897 if (getOperand(i-1).isMetadata() && 1898 (LocMD = getOperand(i-1).getMetadata()) && 1899 LocMD->getNumOperands() != 0) { 1900 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1901 LocCookie = CI->getZExtValue(); 1902 break; 1903 } 1904 } 1905 } 1906 1907 if (const MachineBasicBlock *MBB = getParent()) 1908 if (const MachineFunction *MF = MBB->getParent()) 1909 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1910 report_fatal_error(Msg); 1911} 1912