MachineInstr.cpp revision a70dca156fa76d452f54829b5c5f962ddfd94ef2 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/InlineAsm.h"
17#include "llvm/Value.h"
18#include "llvm/Assembly/Writer.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/PseudoSourceValue.h"
23#include "llvm/Target/TargetMachine.h"
24#include "llvm/Target/TargetInstrInfo.h"
25#include "llvm/Target/TargetInstrDesc.h"
26#include "llvm/Target/TargetRegisterInfo.h"
27#include "llvm/Analysis/AliasAnalysis.h"
28#include "llvm/Analysis/DebugInfo.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/LeakDetector.h"
31#include "llvm/Support/MathExtras.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/ADT/FoldingSet.h"
34using namespace llvm;
35
36//===----------------------------------------------------------------------===//
37// MachineOperand Implementation
38//===----------------------------------------------------------------------===//
39
40/// AddRegOperandToRegInfo - Add this register operand to the specified
41/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
42/// explicitly nulled out.
43void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
44  assert(isReg() && "Can only add reg operand to use lists");
45
46  // If the reginfo pointer is null, just explicitly null out or next/prev
47  // pointers, to ensure they are not garbage.
48  if (RegInfo == 0) {
49    Contents.Reg.Prev = 0;
50    Contents.Reg.Next = 0;
51    return;
52  }
53
54  // Otherwise, add this operand to the head of the registers use/def list.
55  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
56
57  // For SSA values, we prefer to keep the definition at the start of the list.
58  // we do this by skipping over the definition if it is at the head of the
59  // list.
60  if (*Head && (*Head)->isDef())
61    Head = &(*Head)->Contents.Reg.Next;
62
63  Contents.Reg.Next = *Head;
64  if (Contents.Reg.Next) {
65    assert(getReg() == Contents.Reg.Next->getReg() &&
66           "Different regs on the same list!");
67    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
68  }
69
70  Contents.Reg.Prev = Head;
71  *Head = this;
72}
73
74/// RemoveRegOperandFromRegInfo - Remove this register operand from the
75/// MachineRegisterInfo it is linked with.
76void MachineOperand::RemoveRegOperandFromRegInfo() {
77  assert(isOnRegUseList() && "Reg operand is not on a use list");
78  // Unlink this from the doubly linked list of operands.
79  MachineOperand *NextOp = Contents.Reg.Next;
80  *Contents.Reg.Prev = NextOp;
81  if (NextOp) {
82    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
83    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
84  }
85  Contents.Reg.Prev = 0;
86  Contents.Reg.Next = 0;
87}
88
89void MachineOperand::setReg(unsigned Reg) {
90  if (getReg() == Reg) return; // No change.
91
92  // Otherwise, we have to change the register.  If this operand is embedded
93  // into a machine function, we need to update the old and new register's
94  // use/def lists.
95  if (MachineInstr *MI = getParent())
96    if (MachineBasicBlock *MBB = MI->getParent())
97      if (MachineFunction *MF = MBB->getParent()) {
98        RemoveRegOperandFromRegInfo();
99        Contents.Reg.RegNo = Reg;
100        AddRegOperandToRegInfo(&MF->getRegInfo());
101        return;
102      }
103
104  // Otherwise, just change the register, no problem.  :)
105  Contents.Reg.RegNo = Reg;
106}
107
108/// ChangeToImmediate - Replace this operand with a new immediate operand of
109/// the specified value.  If an operand is known to be an immediate already,
110/// the setImm method should be used.
111void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
112  // If this operand is currently a register operand, and if this is in a
113  // function, deregister the operand from the register's use/def list.
114  if (isReg() && getParent() && getParent()->getParent() &&
115      getParent()->getParent()->getParent())
116    RemoveRegOperandFromRegInfo();
117
118  OpKind = MO_Immediate;
119  Contents.ImmVal = ImmVal;
120}
121
122/// ChangeToRegister - Replace this operand with a new register operand of
123/// the specified value.  If an operand is known to be an register already,
124/// the setReg method should be used.
125void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
126                                      bool isKill, bool isDead, bool isUndef) {
127  // If this operand is already a register operand, use setReg to update the
128  // register's use/def lists.
129  if (isReg()) {
130    assert(!isEarlyClobber());
131    setReg(Reg);
132  } else {
133    // Otherwise, change this to a register and set the reg#.
134    OpKind = MO_Register;
135    Contents.Reg.RegNo = Reg;
136
137    // If this operand is embedded in a function, add the operand to the
138    // register's use/def list.
139    if (MachineInstr *MI = getParent())
140      if (MachineBasicBlock *MBB = MI->getParent())
141        if (MachineFunction *MF = MBB->getParent())
142          AddRegOperandToRegInfo(&MF->getRegInfo());
143  }
144
145  IsDef = isDef;
146  IsImp = isImp;
147  IsKill = isKill;
148  IsDead = isDead;
149  IsUndef = isUndef;
150  IsEarlyClobber = false;
151  SubReg = 0;
152}
153
154/// isIdenticalTo - Return true if this operand is identical to the specified
155/// operand.
156bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
157  if (getType() != Other.getType() ||
158      getTargetFlags() != Other.getTargetFlags())
159    return false;
160
161  switch (getType()) {
162  default: llvm_unreachable("Unrecognized operand type");
163  case MachineOperand::MO_Register:
164    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
165           getSubReg() == Other.getSubReg();
166  case MachineOperand::MO_Immediate:
167    return getImm() == Other.getImm();
168  case MachineOperand::MO_FPImmediate:
169    return getFPImm() == Other.getFPImm();
170  case MachineOperand::MO_MachineBasicBlock:
171    return getMBB() == Other.getMBB();
172  case MachineOperand::MO_FrameIndex:
173    return getIndex() == Other.getIndex();
174  case MachineOperand::MO_ConstantPoolIndex:
175    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
176  case MachineOperand::MO_JumpTableIndex:
177    return getIndex() == Other.getIndex();
178  case MachineOperand::MO_GlobalAddress:
179    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
180  case MachineOperand::MO_ExternalSymbol:
181    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
182           getOffset() == Other.getOffset();
183  }
184}
185
186/// print - Print the specified machine operand.
187///
188void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
189  switch (getType()) {
190  case MachineOperand::MO_Register:
191    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
192      OS << "%reg" << getReg();
193    } else {
194      // If the instruction is embedded into a basic block, we can find the
195      // target info for the instruction.
196      if (TM == 0)
197        if (const MachineInstr *MI = getParent())
198          if (const MachineBasicBlock *MBB = MI->getParent())
199            if (const MachineFunction *MF = MBB->getParent())
200              TM = &MF->getTarget();
201
202      if (TM)
203        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
204      else
205        OS << "%mreg" << getReg();
206    }
207
208    if (getSubReg() != 0)
209      OS << ':' << getSubReg();
210
211    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
212        isEarlyClobber()) {
213      OS << '<';
214      bool NeedComma = false;
215      if (isImplicit()) {
216        if (NeedComma) OS << ',';
217        OS << (isDef() ? "imp-def" : "imp-use");
218        NeedComma = true;
219      } else if (isDef()) {
220        if (NeedComma) OS << ',';
221        if (isEarlyClobber())
222          OS << "earlyclobber,";
223        OS << "def";
224        NeedComma = true;
225      }
226      if (isKill() || isDead() || isUndef()) {
227        if (NeedComma) OS << ',';
228        if (isKill())  OS << "kill";
229        if (isDead())  OS << "dead";
230        if (isUndef()) {
231          if (isKill() || isDead())
232            OS << ',';
233          OS << "undef";
234        }
235      }
236      OS << '>';
237    }
238    break;
239  case MachineOperand::MO_Immediate:
240    OS << getImm();
241    break;
242  case MachineOperand::MO_FPImmediate:
243    if (getFPImm()->getType()->isFloatTy())
244      OS << getFPImm()->getValueAPF().convertToFloat();
245    else
246      OS << getFPImm()->getValueAPF().convertToDouble();
247    break;
248  case MachineOperand::MO_MachineBasicBlock:
249    OS << "mbb<"
250       << ((Value*)getMBB()->getBasicBlock())->getName()
251       << "," << (void*)getMBB() << '>';
252    break;
253  case MachineOperand::MO_FrameIndex:
254    OS << "<fi#" << getIndex() << '>';
255    break;
256  case MachineOperand::MO_ConstantPoolIndex:
257    OS << "<cp#" << getIndex();
258    if (getOffset()) OS << "+" << getOffset();
259    OS << '>';
260    break;
261  case MachineOperand::MO_JumpTableIndex:
262    OS << "<jt#" << getIndex() << '>';
263    break;
264  case MachineOperand::MO_GlobalAddress:
265    OS << "<ga:" << ((Value*)getGlobal())->getName();
266    if (getOffset()) OS << "+" << getOffset();
267    OS << '>';
268    break;
269  case MachineOperand::MO_ExternalSymbol:
270    OS << "<es:" << getSymbolName();
271    if (getOffset()) OS << "+" << getOffset();
272    OS << '>';
273    break;
274  default:
275    llvm_unreachable("Unrecognized operand type");
276  }
277
278  if (unsigned TF = getTargetFlags())
279    OS << "[TF=" << TF << ']';
280}
281
282//===----------------------------------------------------------------------===//
283// MachineMemOperand Implementation
284//===----------------------------------------------------------------------===//
285
286MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
287                                     int64_t o, uint64_t s, unsigned int a)
288  : Offset(o), Size(s), V(v),
289    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
290  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
291  assert((isLoad() || isStore()) && "Not a load/store!");
292}
293
294/// Profile - Gather unique data for the object.
295///
296void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
297  ID.AddInteger(Offset);
298  ID.AddInteger(Size);
299  ID.AddPointer(V);
300  ID.AddInteger(Flags);
301}
302
303void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
304  // The Value and Offset may differ due to CSE. But the flags and size
305  // should be the same.
306  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
307  assert(MMO->getSize() == getSize() && "Size mismatch!");
308
309  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
310    // Update the alignment value.
311    Flags = (Flags & 7) | ((Log2_32(MMO->getBaseAlignment()) + 1) << 3);
312    // Also update the base and offset, because the new alignment may
313    // not be applicable with the old ones.
314    V = MMO->getValue();
315    Offset = MMO->getOffset();
316  }
317}
318
319/// getAlignment - Return the minimum known alignment in bytes of the
320/// actual memory reference.
321uint64_t MachineMemOperand::getAlignment() const {
322  return MinAlign(getBaseAlignment(), getOffset());
323}
324
325raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
326  assert((MMO.isLoad() || MMO.isStore()) &&
327         "SV has to be a load, store or both.");
328
329  if (MMO.isVolatile())
330    OS << "Volatile ";
331
332  if (MMO.isLoad())
333    OS << "LD";
334  if (MMO.isStore())
335    OS << "ST";
336  OS << MMO.getSize();
337
338  // Print the address information.
339  OS << "[";
340  if (!MMO.getValue())
341    OS << "<unknown>";
342  else
343    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
344
345  // If the alignment of the memory reference itself differs from the alignment
346  // of the base pointer, print the base alignment explicitly, next to the base
347  // pointer.
348  if (MMO.getBaseAlignment() != MMO.getAlignment())
349    OS << "(align=" << MMO.getBaseAlignment() << ")";
350
351  if (MMO.getOffset() != 0)
352    OS << "+" << MMO.getOffset();
353  OS << "]";
354
355  // Print the alignment of the reference.
356  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
357      MMO.getBaseAlignment() != MMO.getSize())
358    OS << "(align=" << MMO.getAlignment() << ")";
359
360  return OS;
361}
362
363//===----------------------------------------------------------------------===//
364// MachineInstr Implementation
365//===----------------------------------------------------------------------===//
366
367/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
368/// TID NULL and no operands.
369MachineInstr::MachineInstr()
370  : TID(0), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0),
371    Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
372  // Make sure that we get added to a machine basicblock
373  LeakDetector::addGarbageObject(this);
374}
375
376void MachineInstr::addImplicitDefUseOperands() {
377  if (TID->ImplicitDefs)
378    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
379      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
380  if (TID->ImplicitUses)
381    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
382      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
383}
384
385/// MachineInstr ctor - This constructor create a MachineInstr and add the
386/// implicit operands. It reserves space for number of operands specified by
387/// TargetInstrDesc or the numOperands if it is not zero. (for
388/// instructions with variable number of operands).
389MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
390  : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0),
391    debugLoc(DebugLoc::getUnknownLoc()) {
392  if (!NoImp && TID->getImplicitDefs())
393    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
394      NumImplicitOps++;
395  if (!NoImp && TID->getImplicitUses())
396    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
397      NumImplicitOps++;
398  Operands.reserve(NumImplicitOps + TID->getNumOperands());
399  if (!NoImp)
400    addImplicitDefUseOperands();
401  // Make sure that we get added to a machine basicblock
402  LeakDetector::addGarbageObject(this);
403}
404
405/// MachineInstr ctor - As above, but with a DebugLoc.
406MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
407                           bool NoImp)
408  : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0),
409    Parent(0), debugLoc(dl) {
410  if (!NoImp && TID->getImplicitDefs())
411    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
412      NumImplicitOps++;
413  if (!NoImp && TID->getImplicitUses())
414    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
415      NumImplicitOps++;
416  Operands.reserve(NumImplicitOps + TID->getNumOperands());
417  if (!NoImp)
418    addImplicitDefUseOperands();
419  // Make sure that we get added to a machine basicblock
420  LeakDetector::addGarbageObject(this);
421}
422
423/// MachineInstr ctor - Work exactly the same as the ctor two above, except
424/// that the MachineInstr is created and added to the end of the specified
425/// basic block.
426///
427MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
428  : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0), Parent(0),
429    debugLoc(DebugLoc::getUnknownLoc()) {
430  assert(MBB && "Cannot use inserting ctor with null basic block!");
431  if (TID->ImplicitDefs)
432    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
433      NumImplicitOps++;
434  if (TID->ImplicitUses)
435    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
436      NumImplicitOps++;
437  Operands.reserve(NumImplicitOps + TID->getNumOperands());
438  addImplicitDefUseOperands();
439  // Make sure that we get added to a machine basicblock
440  LeakDetector::addGarbageObject(this);
441  MBB->push_back(this);  // Add instruction to end of basic block!
442}
443
444/// MachineInstr ctor - As above, but with a DebugLoc.
445///
446MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
447                           const TargetInstrDesc &tid)
448  : TID(&tid), NumImplicitOps(0), MemRefs(0), MemRefsEnd(0),
449    Parent(0), debugLoc(dl) {
450  assert(MBB && "Cannot use inserting ctor with null basic block!");
451  if (TID->ImplicitDefs)
452    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
453      NumImplicitOps++;
454  if (TID->ImplicitUses)
455    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
456      NumImplicitOps++;
457  Operands.reserve(NumImplicitOps + TID->getNumOperands());
458  addImplicitDefUseOperands();
459  // Make sure that we get added to a machine basicblock
460  LeakDetector::addGarbageObject(this);
461  MBB->push_back(this);  // Add instruction to end of basic block!
462}
463
464/// MachineInstr ctor - Copies MachineInstr arg exactly
465///
466MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
467  : TID(&MI.getDesc()), NumImplicitOps(0),
468    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
469    Parent(0), debugLoc(MI.getDebugLoc()) {
470  Operands.reserve(MI.getNumOperands());
471
472  // Add operands
473  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
474    addOperand(MI.getOperand(i));
475  NumImplicitOps = MI.NumImplicitOps;
476
477  // Set parent to null.
478  Parent = 0;
479
480  LeakDetector::addGarbageObject(this);
481}
482
483MachineInstr::~MachineInstr() {
484  LeakDetector::removeGarbageObject(this);
485#ifndef NDEBUG
486  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
487    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
488    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
489           "Reg operand def/use list corrupted");
490  }
491#endif
492}
493
494/// getRegInfo - If this instruction is embedded into a MachineFunction,
495/// return the MachineRegisterInfo object for the current function, otherwise
496/// return null.
497MachineRegisterInfo *MachineInstr::getRegInfo() {
498  if (MachineBasicBlock *MBB = getParent())
499    return &MBB->getParent()->getRegInfo();
500  return 0;
501}
502
503/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
504/// this instruction from their respective use lists.  This requires that the
505/// operands already be on their use lists.
506void MachineInstr::RemoveRegOperandsFromUseLists() {
507  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
508    if (Operands[i].isReg())
509      Operands[i].RemoveRegOperandFromRegInfo();
510  }
511}
512
513/// AddRegOperandsToUseLists - Add all of the register operands in
514/// this instruction from their respective use lists.  This requires that the
515/// operands not be on their use lists yet.
516void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
517  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
518    if (Operands[i].isReg())
519      Operands[i].AddRegOperandToRegInfo(&RegInfo);
520  }
521}
522
523
524/// addOperand - Add the specified operand to the instruction.  If it is an
525/// implicit operand, it is added to the end of the operand list.  If it is
526/// an explicit operand it is added at the end of the explicit operand list
527/// (before the first implicit operand).
528void MachineInstr::addOperand(const MachineOperand &Op) {
529  bool isImpReg = Op.isReg() && Op.isImplicit();
530  assert((isImpReg || !OperandsComplete()) &&
531         "Trying to add an operand to a machine instr that is already done!");
532
533  MachineRegisterInfo *RegInfo = getRegInfo();
534
535  // If we are adding the operand to the end of the list, our job is simpler.
536  // This is true most of the time, so this is a reasonable optimization.
537  if (isImpReg || NumImplicitOps == 0) {
538    // We can only do this optimization if we know that the operand list won't
539    // reallocate.
540    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
541      Operands.push_back(Op);
542
543      // Set the parent of the operand.
544      Operands.back().ParentMI = this;
545
546      // If the operand is a register, update the operand's use list.
547      if (Op.isReg())
548        Operands.back().AddRegOperandToRegInfo(RegInfo);
549      return;
550    }
551  }
552
553  // Otherwise, we have to insert a real operand before any implicit ones.
554  unsigned OpNo = Operands.size()-NumImplicitOps;
555
556  // If this instruction isn't embedded into a function, then we don't need to
557  // update any operand lists.
558  if (RegInfo == 0) {
559    // Simple insertion, no reginfo update needed for other register operands.
560    Operands.insert(Operands.begin()+OpNo, Op);
561    Operands[OpNo].ParentMI = this;
562
563    // Do explicitly set the reginfo for this operand though, to ensure the
564    // next/prev fields are properly nulled out.
565    if (Operands[OpNo].isReg())
566      Operands[OpNo].AddRegOperandToRegInfo(0);
567
568  } else if (Operands.size()+1 <= Operands.capacity()) {
569    // Otherwise, we have to remove register operands from their register use
570    // list, add the operand, then add the register operands back to their use
571    // list.  This also must handle the case when the operand list reallocates
572    // to somewhere else.
573
574    // If insertion of this operand won't cause reallocation of the operand
575    // list, just remove the implicit operands, add the operand, then re-add all
576    // the rest of the operands.
577    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
578      assert(Operands[i].isReg() && "Should only be an implicit reg!");
579      Operands[i].RemoveRegOperandFromRegInfo();
580    }
581
582    // Add the operand.  If it is a register, add it to the reg list.
583    Operands.insert(Operands.begin()+OpNo, Op);
584    Operands[OpNo].ParentMI = this;
585
586    if (Operands[OpNo].isReg())
587      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
588
589    // Re-add all the implicit ops.
590    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
591      assert(Operands[i].isReg() && "Should only be an implicit reg!");
592      Operands[i].AddRegOperandToRegInfo(RegInfo);
593    }
594  } else {
595    // Otherwise, we will be reallocating the operand list.  Remove all reg
596    // operands from their list, then readd them after the operand list is
597    // reallocated.
598    RemoveRegOperandsFromUseLists();
599
600    Operands.insert(Operands.begin()+OpNo, Op);
601    Operands[OpNo].ParentMI = this;
602
603    // Re-add all the operands.
604    AddRegOperandsToUseLists(*RegInfo);
605  }
606}
607
608/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
609/// fewer operand than it started with.
610///
611void MachineInstr::RemoveOperand(unsigned OpNo) {
612  assert(OpNo < Operands.size() && "Invalid operand number");
613
614  // Special case removing the last one.
615  if (OpNo == Operands.size()-1) {
616    // If needed, remove from the reg def/use list.
617    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
618      Operands.back().RemoveRegOperandFromRegInfo();
619
620    Operands.pop_back();
621    return;
622  }
623
624  // Otherwise, we are removing an interior operand.  If we have reginfo to
625  // update, remove all operands that will be shifted down from their reg lists,
626  // move everything down, then re-add them.
627  MachineRegisterInfo *RegInfo = getRegInfo();
628  if (RegInfo) {
629    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
630      if (Operands[i].isReg())
631        Operands[i].RemoveRegOperandFromRegInfo();
632    }
633  }
634
635  Operands.erase(Operands.begin()+OpNo);
636
637  if (RegInfo) {
638    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
639      if (Operands[i].isReg())
640        Operands[i].AddRegOperandToRegInfo(RegInfo);
641    }
642  }
643}
644
645/// addMemOperand - Add a MachineMemOperand to the machine instruction.
646/// This function should be used only occasionally. The setMemRefs function
647/// is the primary method for setting up a MachineInstr's MemRefs list.
648void MachineInstr::addMemOperand(MachineFunction &MF,
649                                 MachineMemOperand *MO) {
650  mmo_iterator OldMemRefs = MemRefs;
651  mmo_iterator OldMemRefsEnd = MemRefsEnd;
652
653  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
654  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
655  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
656
657  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
658  NewMemRefs[NewNum - 1] = MO;
659
660  MemRefs = NewMemRefs;
661  MemRefsEnd = NewMemRefsEnd;
662}
663
664/// removeFromParent - This method unlinks 'this' from the containing basic
665/// block, and returns it, but does not delete it.
666MachineInstr *MachineInstr::removeFromParent() {
667  assert(getParent() && "Not embedded in a basic block!");
668  getParent()->remove(this);
669  return this;
670}
671
672
673/// eraseFromParent - This method unlinks 'this' from the containing basic
674/// block, and deletes it.
675void MachineInstr::eraseFromParent() {
676  assert(getParent() && "Not embedded in a basic block!");
677  getParent()->erase(this);
678}
679
680
681/// OperandComplete - Return true if it's illegal to add a new operand
682///
683bool MachineInstr::OperandsComplete() const {
684  unsigned short NumOperands = TID->getNumOperands();
685  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
686    return true;  // Broken: we have all the operands of this instruction!
687  return false;
688}
689
690/// getNumExplicitOperands - Returns the number of non-implicit operands.
691///
692unsigned MachineInstr::getNumExplicitOperands() const {
693  unsigned NumOperands = TID->getNumOperands();
694  if (!TID->isVariadic())
695    return NumOperands;
696
697  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
698    const MachineOperand &MO = getOperand(i);
699    if (!MO.isReg() || !MO.isImplicit())
700      NumOperands++;
701  }
702  return NumOperands;
703}
704
705
706/// isLabel - Returns true if the MachineInstr represents a label.
707///
708bool MachineInstr::isLabel() const {
709  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
710         getOpcode() == TargetInstrInfo::EH_LABEL ||
711         getOpcode() == TargetInstrInfo::GC_LABEL;
712}
713
714/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
715///
716bool MachineInstr::isDebugLabel() const {
717  return getOpcode() == TargetInstrInfo::DBG_LABEL;
718}
719
720/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
721/// the specific register or -1 if it is not found. It further tightens
722/// the search criteria to a use that kills the register if isKill is true.
723int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
724                                          const TargetRegisterInfo *TRI) const {
725  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
726    const MachineOperand &MO = getOperand(i);
727    if (!MO.isReg() || !MO.isUse())
728      continue;
729    unsigned MOReg = MO.getReg();
730    if (!MOReg)
731      continue;
732    if (MOReg == Reg ||
733        (TRI &&
734         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
735         TargetRegisterInfo::isPhysicalRegister(Reg) &&
736         TRI->isSubRegister(MOReg, Reg)))
737      if (!isKill || MO.isKill())
738        return i;
739  }
740  return -1;
741}
742
743/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
744/// the specified register or -1 if it is not found. If isDead is true, defs
745/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
746/// also checks if there is a def of a super-register.
747int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
748                                          const TargetRegisterInfo *TRI) const {
749  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
750    const MachineOperand &MO = getOperand(i);
751    if (!MO.isReg() || !MO.isDef())
752      continue;
753    unsigned MOReg = MO.getReg();
754    if (MOReg == Reg ||
755        (TRI &&
756         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
757         TargetRegisterInfo::isPhysicalRegister(Reg) &&
758         TRI->isSubRegister(MOReg, Reg)))
759      if (!isDead || MO.isDead())
760        return i;
761  }
762  return -1;
763}
764
765/// findFirstPredOperandIdx() - Find the index of the first operand in the
766/// operand list that is used to represent the predicate. It returns -1 if
767/// none is found.
768int MachineInstr::findFirstPredOperandIdx() const {
769  const TargetInstrDesc &TID = getDesc();
770  if (TID.isPredicable()) {
771    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
772      if (TID.OpInfo[i].isPredicate())
773        return i;
774  }
775
776  return -1;
777}
778
779/// isRegTiedToUseOperand - Given the index of a register def operand,
780/// check if the register def is tied to a source operand, due to either
781/// two-address elimination or inline assembly constraints. Returns the
782/// first tied use operand index by reference is UseOpIdx is not null.
783bool MachineInstr::
784isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
785  if (getOpcode() == TargetInstrInfo::INLINEASM) {
786    assert(DefOpIdx >= 2);
787    const MachineOperand &MO = getOperand(DefOpIdx);
788    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
789      return false;
790    // Determine the actual operand index that corresponds to this index.
791    unsigned DefNo = 0;
792    unsigned DefPart = 0;
793    for (unsigned i = 1, e = getNumOperands(); i < e; ) {
794      const MachineOperand &FMO = getOperand(i);
795      // After the normal asm operands there may be additional imp-def regs.
796      if (!FMO.isImm())
797        return false;
798      // Skip over this def.
799      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
800      unsigned PrevDef = i + 1;
801      i = PrevDef + NumOps;
802      if (i > DefOpIdx) {
803        DefPart = DefOpIdx - PrevDef;
804        break;
805      }
806      ++DefNo;
807    }
808    for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
809      const MachineOperand &FMO = getOperand(i);
810      if (!FMO.isImm())
811        continue;
812      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
813        continue;
814      unsigned Idx;
815      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
816          Idx == DefNo) {
817        if (UseOpIdx)
818          *UseOpIdx = (unsigned)i + 1 + DefPart;
819        return true;
820      }
821    }
822    return false;
823  }
824
825  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
826  const TargetInstrDesc &TID = getDesc();
827  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
828    const MachineOperand &MO = getOperand(i);
829    if (MO.isReg() && MO.isUse() &&
830        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
831      if (UseOpIdx)
832        *UseOpIdx = (unsigned)i;
833      return true;
834    }
835  }
836  return false;
837}
838
839/// isRegTiedToDefOperand - Return true if the operand of the specified index
840/// is a register use and it is tied to an def operand. It also returns the def
841/// operand index by reference.
842bool MachineInstr::
843isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
844  if (getOpcode() == TargetInstrInfo::INLINEASM) {
845    const MachineOperand &MO = getOperand(UseOpIdx);
846    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
847      return false;
848
849    // Find the flag operand corresponding to UseOpIdx
850    unsigned FlagIdx, NumOps=0;
851    for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
852      const MachineOperand &UFMO = getOperand(FlagIdx);
853      // After the normal asm operands there may be additional imp-def regs.
854      if (!UFMO.isImm())
855        return false;
856      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
857      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
858      if (UseOpIdx < FlagIdx+NumOps+1)
859        break;
860    }
861    if (FlagIdx >= UseOpIdx)
862      return false;
863    const MachineOperand &UFMO = getOperand(FlagIdx);
864    unsigned DefNo;
865    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
866      if (!DefOpIdx)
867        return true;
868
869      unsigned DefIdx = 1;
870      // Remember to adjust the index. First operand is asm string, then there
871      // is a flag for each.
872      while (DefNo) {
873        const MachineOperand &FMO = getOperand(DefIdx);
874        assert(FMO.isImm());
875        // Skip over this def.
876        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
877        --DefNo;
878      }
879      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
880      return true;
881    }
882    return false;
883  }
884
885  const TargetInstrDesc &TID = getDesc();
886  if (UseOpIdx >= TID.getNumOperands())
887    return false;
888  const MachineOperand &MO = getOperand(UseOpIdx);
889  if (!MO.isReg() || !MO.isUse())
890    return false;
891  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
892  if (DefIdx == -1)
893    return false;
894  if (DefOpIdx)
895    *DefOpIdx = (unsigned)DefIdx;
896  return true;
897}
898
899/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
900///
901void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
902  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
903    const MachineOperand &MO = MI->getOperand(i);
904    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
905      continue;
906    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
907      MachineOperand &MOp = getOperand(j);
908      if (!MOp.isIdenticalTo(MO))
909        continue;
910      if (MO.isKill())
911        MOp.setIsKill();
912      else
913        MOp.setIsDead();
914      break;
915    }
916  }
917}
918
919/// copyPredicates - Copies predicate operand(s) from MI.
920void MachineInstr::copyPredicates(const MachineInstr *MI) {
921  const TargetInstrDesc &TID = MI->getDesc();
922  if (!TID.isPredicable())
923    return;
924  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
925    if (TID.OpInfo[i].isPredicate()) {
926      // Predicated operands must be last operands.
927      addOperand(MI->getOperand(i));
928    }
929  }
930}
931
932/// isSafeToMove - Return true if it is safe to move this instruction. If
933/// SawStore is set to true, it means that there is a store (or call) between
934/// the instruction's location and its intended destination.
935bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
936                                bool &SawStore,
937                                AliasAnalysis *AA) const {
938  // Ignore stuff that we obviously can't move.
939  if (TID->mayStore() || TID->isCall()) {
940    SawStore = true;
941    return false;
942  }
943  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
944    return false;
945
946  // See if this instruction does a load.  If so, we have to guarantee that the
947  // loaded value doesn't change between the load and the its intended
948  // destination. The check for isInvariantLoad gives the targe the chance to
949  // classify the load as always returning a constant, e.g. a constant pool
950  // load.
951  if (TID->mayLoad() && !isInvariantLoad(AA))
952    // Otherwise, this is a real load.  If there is a store between the load and
953    // end of block, or if the load is volatile, we can't move it.
954    return !SawStore && !hasVolatileMemoryRef();
955
956  return true;
957}
958
959/// isSafeToReMat - Return true if it's safe to rematerialize the specified
960/// instruction which defined the specified register instead of copying it.
961bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
962                                 unsigned DstReg,
963                                 AliasAnalysis *AA) const {
964  bool SawStore = false;
965  if (!TII->isTriviallyReMaterializable(this, AA) ||
966      !isSafeToMove(TII, SawStore, AA))
967    return false;
968  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
969    const MachineOperand &MO = getOperand(i);
970    if (!MO.isReg())
971      continue;
972    // FIXME: For now, do not remat any instruction with register operands.
973    // Later on, we can loosen the restriction is the register operands have
974    // not been modified between the def and use. Note, this is different from
975    // MachineSink because the code is no longer in two-address form (at least
976    // partially).
977    if (MO.isUse())
978      return false;
979    else if (!MO.isDead() && MO.getReg() != DstReg)
980      return false;
981  }
982  return true;
983}
984
985/// hasVolatileMemoryRef - Return true if this instruction may have a
986/// volatile memory reference, or if the information describing the
987/// memory reference is not available. Return false if it is known to
988/// have no volatile memory references.
989bool MachineInstr::hasVolatileMemoryRef() const {
990  // An instruction known never to access memory won't have a volatile access.
991  if (!TID->mayStore() &&
992      !TID->mayLoad() &&
993      !TID->isCall() &&
994      !TID->hasUnmodeledSideEffects())
995    return false;
996
997  // Otherwise, if the instruction has no memory reference information,
998  // conservatively assume it wasn't preserved.
999  if (memoperands_empty())
1000    return true;
1001
1002  // Check the memory reference information for volatile references.
1003  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1004    if ((*I)->isVolatile())
1005      return true;
1006
1007  return false;
1008}
1009
1010/// isInvariantLoad - Return true if this instruction is loading from a
1011/// location whose value is invariant across the function.  For example,
1012/// loading a value from the constant pool or from from the argument area
1013/// of a function if it does not change.  This should only return true of
1014/// *all* loads the instruction does are invariant (if it does multiple loads).
1015bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1016  // If the instruction doesn't load at all, it isn't an invariant load.
1017  if (!TID->mayLoad())
1018    return false;
1019
1020  // If the instruction has lost its memoperands, conservatively assume that
1021  // it may not be an invariant load.
1022  if (memoperands_empty())
1023    return false;
1024
1025  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1026
1027  for (mmo_iterator I = memoperands_begin(),
1028       E = memoperands_end(); I != E; ++I) {
1029    if ((*I)->isVolatile()) return false;
1030    if ((*I)->isStore()) return false;
1031
1032    if (const Value *V = (*I)->getValue()) {
1033      // A load from a constant PseudoSourceValue is invariant.
1034      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1035        if (PSV->isConstant(MFI))
1036          continue;
1037      // If we have an AliasAnalysis, ask it whether the memory is constant.
1038      if (AA && AA->pointsToConstantMemory(V))
1039        continue;
1040    }
1041
1042    // Otherwise assume conservatively.
1043    return false;
1044  }
1045
1046  // Everything checks out.
1047  return true;
1048}
1049
1050void MachineInstr::dump() const {
1051  errs() << "  " << *this;
1052}
1053
1054void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1055  // Specialize printing if op#0 is definition
1056  unsigned StartOp = 0;
1057  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
1058    getOperand(0).print(OS, TM);
1059    OS << " = ";
1060    ++StartOp;   // Don't print this operand again!
1061  }
1062
1063  OS << getDesc().getName();
1064
1065  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1066    if (i != StartOp)
1067      OS << ",";
1068    OS << " ";
1069    getOperand(i).print(OS, TM);
1070  }
1071
1072  if (!memoperands_empty()) {
1073    OS << ", Mem:";
1074    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1075         i != e; ++i) {
1076      OS << **i;
1077      if (next(i) != e)
1078        OS << " ";
1079    }
1080  }
1081
1082  if (!debugLoc.isUnknown()) {
1083    const MachineFunction *MF = getParent()->getParent();
1084    DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
1085    DICompileUnit CU(DLT.CompileUnit);
1086    OS << " [dbg: "
1087       << CU.getDirectory() << '/' << CU.getFilename() << ","
1088       << DLT.Line << ","
1089       << DLT.Col  << "]";
1090  }
1091
1092  OS << "\n";
1093}
1094
1095bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1096                                     const TargetRegisterInfo *RegInfo,
1097                                     bool AddIfNotFound) {
1098  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1099  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1100  bool Found = false;
1101  SmallVector<unsigned,4> DeadOps;
1102  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1103    MachineOperand &MO = getOperand(i);
1104    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1105      continue;
1106    unsigned Reg = MO.getReg();
1107    if (!Reg)
1108      continue;
1109
1110    if (Reg == IncomingReg) {
1111      if (!Found) {
1112        if (MO.isKill())
1113          // The register is already marked kill.
1114          return true;
1115        if (isPhysReg && isRegTiedToDefOperand(i))
1116          // Two-address uses of physregs must not be marked kill.
1117          return true;
1118        MO.setIsKill();
1119        Found = true;
1120      }
1121    } else if (hasAliases && MO.isKill() &&
1122               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1123      // A super-register kill already exists.
1124      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1125        return true;
1126      if (RegInfo->isSubRegister(IncomingReg, Reg))
1127        DeadOps.push_back(i);
1128    }
1129  }
1130
1131  // Trim unneeded kill operands.
1132  while (!DeadOps.empty()) {
1133    unsigned OpIdx = DeadOps.back();
1134    if (getOperand(OpIdx).isImplicit())
1135      RemoveOperand(OpIdx);
1136    else
1137      getOperand(OpIdx).setIsKill(false);
1138    DeadOps.pop_back();
1139  }
1140
1141  // If not found, this means an alias of one of the operands is killed. Add a
1142  // new implicit operand if required.
1143  if (!Found && AddIfNotFound) {
1144    addOperand(MachineOperand::CreateReg(IncomingReg,
1145                                         false /*IsDef*/,
1146                                         true  /*IsImp*/,
1147                                         true  /*IsKill*/));
1148    return true;
1149  }
1150  return Found;
1151}
1152
1153bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1154                                   const TargetRegisterInfo *RegInfo,
1155                                   bool AddIfNotFound) {
1156  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1157  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1158  bool Found = false;
1159  SmallVector<unsigned,4> DeadOps;
1160  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1161    MachineOperand &MO = getOperand(i);
1162    if (!MO.isReg() || !MO.isDef())
1163      continue;
1164    unsigned Reg = MO.getReg();
1165    if (!Reg)
1166      continue;
1167
1168    if (Reg == IncomingReg) {
1169      if (!Found) {
1170        if (MO.isDead())
1171          // The register is already marked dead.
1172          return true;
1173        MO.setIsDead();
1174        Found = true;
1175      }
1176    } else if (hasAliases && MO.isDead() &&
1177               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1178      // There exists a super-register that's marked dead.
1179      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1180        return true;
1181      if (RegInfo->getSubRegisters(IncomingReg) &&
1182          RegInfo->getSuperRegisters(Reg) &&
1183          RegInfo->isSubRegister(IncomingReg, Reg))
1184        DeadOps.push_back(i);
1185    }
1186  }
1187
1188  // Trim unneeded dead operands.
1189  while (!DeadOps.empty()) {
1190    unsigned OpIdx = DeadOps.back();
1191    if (getOperand(OpIdx).isImplicit())
1192      RemoveOperand(OpIdx);
1193    else
1194      getOperand(OpIdx).setIsDead(false);
1195    DeadOps.pop_back();
1196  }
1197
1198  // If not found, this means an alias of one of the operands is dead. Add a
1199  // new implicit operand if required.
1200  if (Found || !AddIfNotFound)
1201    return Found;
1202
1203  addOperand(MachineOperand::CreateReg(IncomingReg,
1204                                       true  /*IsDef*/,
1205                                       true  /*IsImp*/,
1206                                       false /*IsKill*/,
1207                                       true  /*IsDead*/));
1208  return true;
1209}
1210