MachineInstr.cpp revision b11f05043465bceae4853a3bd2c01d7d664cc5e3
1561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===// 2561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// 3561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// The LLVM Compiler Infrastructure 4561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// 5561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// This file is distributed under the University of Illinois Open Source 6561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// License. See LICENSE.TXT for details. 7561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// 8561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes//===----------------------------------------------------------------------===// 9561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// 10561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// Methods common to all machine instructions. 11561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes// 12561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes//===----------------------------------------------------------------------===// 13561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 14561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/MachineInstr.h" 15561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/ADT/FoldingSet.h" 16561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/ADT/Hashing.h" 17561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Analysis/AliasAnalysis.h" 18561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Assembly/Writer.h" 19561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/MachineConstantPool.h" 20561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/MachineFunction.h" 21561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/MachineMemOperand.h" 22561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/MachineModuleInfo.h" 23561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/MachineRegisterInfo.h" 24561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/CodeGen/PseudoSourceValue.h" 25561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/DebugInfo.h" 26561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/Constants.h" 27561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/Function.h" 28561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/InlineAsm.h" 29561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/LLVMContext.h" 30561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/Metadata.h" 31561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/Module.h" 32561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/Type.h" 33561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/IR/Value.h" 34561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/MC/MCInstrDesc.h" 35561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/MC/MCSymbol.h" 36561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Support/Debug.h" 37561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Support/ErrorHandling.h" 38561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Support/MathExtras.h" 39561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Support/raw_ostream.h" 408d8858e39800de641b50f6e8e864af9cf68bedeaNarayan Kamath#include "llvm/Target/TargetInstrInfo.h" 41561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Target/TargetMachine.h" 42561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes#include "llvm/Target/TargetRegisterInfo.h" 43561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesusing namespace llvm; 44561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 45561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes//===----------------------------------------------------------------------===// 468d8858e39800de641b50f6e8e864af9cf68bedeaNarayan Kamath// MachineOperand Implementation 47561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes//===----------------------------------------------------------------------===// 48561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 49561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesvoid MachineOperand::setReg(unsigned Reg) { 50561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (getReg() == Reg) return; // No change. 51561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 52561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // Otherwise, we have to change the register. If this operand is embedded 53561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // into a machine function, we need to update the old and new register's 54561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // use/def lists. 55561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineInstr *MI = getParent()) 56561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineBasicBlock *MBB = MI->getParent()) 57561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineFunction *MF = MBB->getParent()) { 58561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MachineRegisterInfo &MRI = MF->getRegInfo(); 59561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MRI.removeRegOperandFromUseList(this); 60561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes SmallContents.RegNo = Reg; 61561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MRI.addRegOperandToUseList(this); 62561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return; 63561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes } 64561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 65561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // Otherwise, just change the register, no problem. :) 66561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes SmallContents.RegNo = Reg; 67561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes} 68561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 69561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesvoid MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 70561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes const TargetRegisterInfo &TRI) { 71561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes assert(TargetRegisterInfo::isVirtualRegister(Reg)); 72561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (SubIdx && getSubReg()) 73561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 74561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes setReg(Reg); 75561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (SubIdx) 76561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes setSubReg(SubIdx); 77561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes} 78561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 79561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesvoid MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) { 80561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes assert(TargetRegisterInfo::isPhysicalRegister(Reg)); 81561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (getSubReg()) { 82561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes Reg = TRI.getSubReg(Reg, getSubReg()); 83561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // Note that getSubReg() may return 0 if the sub-register doesn't exist. 84561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // That won't happen in legal code. 85561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes setSubReg(0); 86561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes } 87561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes setReg(Reg); 88561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes} 89561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 90561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// Change a def to a use, or a use to a def. 91561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesvoid MachineOperand::setIsDef(bool Val) { 92561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes assert(isReg() && "Wrong MachineOperand accessor"); 93561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes assert((!Val || !isDebug()) && "Marking a debug operation as def"); 94561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (IsDef == Val) 95561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return; 96561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // MRI may keep uses and defs in different list positions. 97561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineInstr *MI = getParent()) 98561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineBasicBlock *MBB = MI->getParent()) 99561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineFunction *MF = MBB->getParent()) { 100561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MachineRegisterInfo &MRI = MF->getRegInfo(); 101561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MRI.removeRegOperandFromUseList(this); 102561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsDef = Val; 103561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MRI.addRegOperandToUseList(this); 104561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return; 105561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes } 106561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsDef = Val; 107561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes} 108561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 1098d8858e39800de641b50f6e8e864af9cf68bedeaNarayan Kamath/// ChangeToImmediate - Replace this operand with a new immediate operand of 110561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// the specified value. If an operand is known to be an immediate already, 111561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// the setImm method should be used. 112561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesvoid MachineOperand::ChangeToImmediate(int64_t ImmVal) { 113561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); 114561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // If this operand is currently a register operand, and if this is in a 115561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // function, deregister the operand from the register's use/def list. 116561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (isReg() && isOnRegUseList()) 1178d8858e39800de641b50f6e8e864af9cf68bedeaNarayan Kamath if (MachineInstr *MI = getParent()) 118561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineBasicBlock *MBB = MI->getParent()) 119561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineFunction *MF = MBB->getParent()) 120561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MF->getRegInfo().removeRegOperandFromUseList(this); 121561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 122561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes OpKind = MO_Immediate; 123561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes Contents.ImmVal = ImmVal; 124561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes} 125561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 126561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// ChangeToRegister - Replace this operand with a new register operand of 127561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// the specified value. If an operand is known to be an register already, 128561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// the setReg method should be used. 129561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesvoid MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, 130561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes bool isKill, bool isDead, bool isUndef, 131561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes bool isDebug) { 132561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes MachineRegisterInfo *RegInfo = 0; 133561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineInstr *MI = getParent()) 134561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineBasicBlock *MBB = MI->getParent()) 135561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (MachineFunction *MF = MBB->getParent()) 136561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes RegInfo = &MF->getRegInfo(); 137561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // If this operand is already a register operand, remove it from the 138561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // register's use/def lists. 139561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes bool WasReg = isReg(); 140561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (RegInfo && WasReg) 141561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes RegInfo->removeRegOperandFromUseList(this); 142561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 143561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // Change this to a register and set the reg#. 144561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes OpKind = MO_Register; 145561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes SmallContents.RegNo = Reg; 146561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes SubReg_TargetFlags = 0; 147561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsDef = isDef; 148561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsImp = isImp; 149561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsKill = isKill; 150561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsDead = isDead; 151561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsUndef = isUndef; 152561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsInternalRead = false; 153561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsEarlyClobber = false; 154561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes IsDebug = isDebug; 155561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // Ensure isOnRegUseList() returns false. 156561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes Contents.Reg.Prev = 0; 157561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // Preserve the tie when the operand was already a register. 158561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (!WasReg) 159561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes TiedTo = 0; 160561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 161561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // If this operand is embedded in a function, add the operand to the 162561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes // register's use/def list. 163561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (RegInfo) 164561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes RegInfo->addRegOperandToUseList(this); 165561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes} 166561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 167561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// isIdenticalTo - Return true if this operand is identical to the specified 168561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// operand. Note that this should stay in sync with the hash_value overload 169561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes/// below. 170561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughesbool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { 171561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes if (getType() != Other.getType() || 172561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes getTargetFlags() != Other.getTargetFlags()) 173561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return false; 174561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes 175561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes switch (getType()) { 176561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_Register: 177561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getReg() == Other.getReg() && isDef() == Other.isDef() && 178561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes getSubReg() == Other.getSubReg(); 179561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_Immediate: 180561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getImm() == Other.getImm(); 181561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_CImmediate: 182561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getCImm() == Other.getCImm(); 183561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_FPImmediate: 184561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getFPImm() == Other.getFPImm(); 185561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_MachineBasicBlock: 186561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getMBB() == Other.getMBB(); 187561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_FrameIndex: 188561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getIndex() == Other.getIndex(); 189561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_ConstantPoolIndex: 190561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_TargetIndex: 191561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getIndex() == Other.getIndex() && getOffset() == Other.getOffset(); 192561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_JumpTableIndex: 193561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getIndex() == Other.getIndex(); 194561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_GlobalAddress: 195561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset(); 196561ee011997c6c2f1befbfaa9d5f0a99771c1d63Elliott Hughes case MachineOperand::MO_ExternalSymbol: 197 return !strcmp(getSymbolName(), Other.getSymbolName()) && 198 getOffset() == Other.getOffset(); 199 case MachineOperand::MO_BlockAddress: 200 return getBlockAddress() == Other.getBlockAddress() && 201 getOffset() == Other.getOffset(); 202 case MO_RegisterMask: 203 return getRegMask() == Other.getRegMask(); 204 case MachineOperand::MO_MCSymbol: 205 return getMCSymbol() == Other.getMCSymbol(); 206 case MachineOperand::MO_Metadata: 207 return getMetadata() == Other.getMetadata(); 208 } 209 llvm_unreachable("Invalid machine operand type"); 210} 211 212// Note: this must stay exactly in sync with isIdenticalTo above. 213hash_code llvm::hash_value(const MachineOperand &MO) { 214 switch (MO.getType()) { 215 case MachineOperand::MO_Register: 216 // Register operands don't have target flags. 217 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); 218 case MachineOperand::MO_Immediate: 219 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); 220 case MachineOperand::MO_CImmediate: 221 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); 222 case MachineOperand::MO_FPImmediate: 223 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); 224 case MachineOperand::MO_MachineBasicBlock: 225 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); 226 case MachineOperand::MO_FrameIndex: 227 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 228 case MachineOperand::MO_ConstantPoolIndex: 229 case MachineOperand::MO_TargetIndex: 230 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), 231 MO.getOffset()); 232 case MachineOperand::MO_JumpTableIndex: 233 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); 234 case MachineOperand::MO_ExternalSymbol: 235 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), 236 MO.getSymbolName()); 237 case MachineOperand::MO_GlobalAddress: 238 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), 239 MO.getOffset()); 240 case MachineOperand::MO_BlockAddress: 241 return hash_combine(MO.getType(), MO.getTargetFlags(), 242 MO.getBlockAddress(), MO.getOffset()); 243 case MachineOperand::MO_RegisterMask: 244 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); 245 case MachineOperand::MO_Metadata: 246 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); 247 case MachineOperand::MO_MCSymbol: 248 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); 249 } 250 llvm_unreachable("Invalid machine operand type"); 251} 252 253/// print - Print the specified machine operand. 254/// 255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const { 256 // If the instruction is embedded into a basic block, we can find the 257 // target info for the instruction. 258 if (!TM) 259 if (const MachineInstr *MI = getParent()) 260 if (const MachineBasicBlock *MBB = MI->getParent()) 261 if (const MachineFunction *MF = MBB->getParent()) 262 TM = &MF->getTarget(); 263 const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0; 264 265 switch (getType()) { 266 case MachineOperand::MO_Register: 267 OS << PrintReg(getReg(), TRI, getSubReg()); 268 269 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() || 270 isInternalRead() || isEarlyClobber() || isTied()) { 271 OS << '<'; 272 bool NeedComma = false; 273 if (isDef()) { 274 if (NeedComma) OS << ','; 275 if (isEarlyClobber()) 276 OS << "earlyclobber,"; 277 if (isImplicit()) 278 OS << "imp-"; 279 OS << "def"; 280 NeedComma = true; 281 // <def,read-undef> only makes sense when getSubReg() is set. 282 // Don't clutter the output otherwise. 283 if (isUndef() && getSubReg()) 284 OS << ",read-undef"; 285 } else if (isImplicit()) { 286 OS << "imp-use"; 287 NeedComma = true; 288 } 289 290 if (isKill()) { 291 if (NeedComma) OS << ','; 292 OS << "kill"; 293 NeedComma = true; 294 } 295 if (isDead()) { 296 if (NeedComma) OS << ','; 297 OS << "dead"; 298 NeedComma = true; 299 } 300 if (isUndef() && isUse()) { 301 if (NeedComma) OS << ','; 302 OS << "undef"; 303 NeedComma = true; 304 } 305 if (isInternalRead()) { 306 if (NeedComma) OS << ','; 307 OS << "internal"; 308 NeedComma = true; 309 } 310 if (isTied()) { 311 if (NeedComma) OS << ','; 312 OS << "tied"; 313 if (TiedTo != 15) 314 OS << unsigned(TiedTo - 1); 315 NeedComma = true; 316 } 317 OS << '>'; 318 } 319 break; 320 case MachineOperand::MO_Immediate: 321 OS << getImm(); 322 break; 323 case MachineOperand::MO_CImmediate: 324 getCImm()->getValue().print(OS, false); 325 break; 326 case MachineOperand::MO_FPImmediate: 327 if (getFPImm()->getType()->isFloatTy()) 328 OS << getFPImm()->getValueAPF().convertToFloat(); 329 else 330 OS << getFPImm()->getValueAPF().convertToDouble(); 331 break; 332 case MachineOperand::MO_MachineBasicBlock: 333 OS << "<BB#" << getMBB()->getNumber() << ">"; 334 break; 335 case MachineOperand::MO_FrameIndex: 336 OS << "<fi#" << getIndex() << '>'; 337 break; 338 case MachineOperand::MO_ConstantPoolIndex: 339 OS << "<cp#" << getIndex(); 340 if (getOffset()) OS << "+" << getOffset(); 341 OS << '>'; 342 break; 343 case MachineOperand::MO_TargetIndex: 344 OS << "<ti#" << getIndex(); 345 if (getOffset()) OS << "+" << getOffset(); 346 OS << '>'; 347 break; 348 case MachineOperand::MO_JumpTableIndex: 349 OS << "<jt#" << getIndex() << '>'; 350 break; 351 case MachineOperand::MO_GlobalAddress: 352 OS << "<ga:"; 353 WriteAsOperand(OS, getGlobal(), /*PrintType=*/false); 354 if (getOffset()) OS << "+" << getOffset(); 355 OS << '>'; 356 break; 357 case MachineOperand::MO_ExternalSymbol: 358 OS << "<es:" << getSymbolName(); 359 if (getOffset()) OS << "+" << getOffset(); 360 OS << '>'; 361 break; 362 case MachineOperand::MO_BlockAddress: 363 OS << '<'; 364 WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false); 365 if (getOffset()) OS << "+" << getOffset(); 366 OS << '>'; 367 break; 368 case MachineOperand::MO_RegisterMask: 369 OS << "<regmask>"; 370 break; 371 case MachineOperand::MO_Metadata: 372 OS << '<'; 373 WriteAsOperand(OS, getMetadata(), /*PrintType=*/false); 374 OS << '>'; 375 break; 376 case MachineOperand::MO_MCSymbol: 377 OS << "<MCSym=" << *getMCSymbol() << '>'; 378 break; 379 } 380 381 if (unsigned TF = getTargetFlags()) 382 OS << "[TF=" << TF << ']'; 383} 384 385//===----------------------------------------------------------------------===// 386// MachineMemOperand Implementation 387//===----------------------------------------------------------------------===// 388 389/// getAddrSpace - Return the LLVM IR address space number that this pointer 390/// points into. 391unsigned MachinePointerInfo::getAddrSpace() const { 392 if (V == 0) return 0; 393 return cast<PointerType>(V->getType())->getAddressSpace(); 394} 395 396/// getConstantPool - Return a MachinePointerInfo record that refers to the 397/// constant pool. 398MachinePointerInfo MachinePointerInfo::getConstantPool() { 399 return MachinePointerInfo(PseudoSourceValue::getConstantPool()); 400} 401 402/// getFixedStack - Return a MachinePointerInfo record that refers to the 403/// the specified FrameIndex. 404MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) { 405 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset); 406} 407 408MachinePointerInfo MachinePointerInfo::getJumpTable() { 409 return MachinePointerInfo(PseudoSourceValue::getJumpTable()); 410} 411 412MachinePointerInfo MachinePointerInfo::getGOT() { 413 return MachinePointerInfo(PseudoSourceValue::getGOT()); 414} 415 416MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) { 417 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset); 418} 419 420MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, 421 uint64_t s, unsigned int a, 422 const MDNode *TBAAInfo, 423 const MDNode *Ranges) 424 : PtrInfo(ptrinfo), Size(s), 425 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), 426 TBAAInfo(TBAAInfo), Ranges(Ranges) { 427 assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) && 428 "invalid pointer value"); 429 assert(getBaseAlignment() == a && "Alignment is not a power of 2!"); 430 assert((isLoad() || isStore()) && "Not a load/store!"); 431} 432 433/// Profile - Gather unique data for the object. 434/// 435void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { 436 ID.AddInteger(getOffset()); 437 ID.AddInteger(Size); 438 ID.AddPointer(getValue()); 439 ID.AddInteger(Flags); 440} 441 442void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { 443 // The Value and Offset may differ due to CSE. But the flags and size 444 // should be the same. 445 assert(MMO->getFlags() == getFlags() && "Flags mismatch!"); 446 assert(MMO->getSize() == getSize() && "Size mismatch!"); 447 448 if (MMO->getBaseAlignment() >= getBaseAlignment()) { 449 // Update the alignment value. 450 Flags = (Flags & ((1 << MOMaxBits) - 1)) | 451 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); 452 // Also update the base and offset, because the new alignment may 453 // not be applicable with the old ones. 454 PtrInfo = MMO->PtrInfo; 455 } 456} 457 458/// getAlignment - Return the minimum known alignment in bytes of the 459/// actual memory reference. 460uint64_t MachineMemOperand::getAlignment() const { 461 return MinAlign(getBaseAlignment(), getOffset()); 462} 463 464raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) { 465 assert((MMO.isLoad() || MMO.isStore()) && 466 "SV has to be a load, store or both."); 467 468 if (MMO.isVolatile()) 469 OS << "Volatile "; 470 471 if (MMO.isLoad()) 472 OS << "LD"; 473 if (MMO.isStore()) 474 OS << "ST"; 475 OS << MMO.getSize(); 476 477 // Print the address information. 478 OS << "["; 479 if (!MMO.getValue()) 480 OS << "<unknown>"; 481 else 482 WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false); 483 484 // If the alignment of the memory reference itself differs from the alignment 485 // of the base pointer, print the base alignment explicitly, next to the base 486 // pointer. 487 if (MMO.getBaseAlignment() != MMO.getAlignment()) 488 OS << "(align=" << MMO.getBaseAlignment() << ")"; 489 490 if (MMO.getOffset() != 0) 491 OS << "+" << MMO.getOffset(); 492 OS << "]"; 493 494 // Print the alignment of the reference. 495 if (MMO.getBaseAlignment() != MMO.getAlignment() || 496 MMO.getBaseAlignment() != MMO.getSize()) 497 OS << "(align=" << MMO.getAlignment() << ")"; 498 499 // Print TBAA info. 500 if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) { 501 OS << "(tbaa="; 502 if (TBAAInfo->getNumOperands() > 0) 503 WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false); 504 else 505 OS << "<unknown>"; 506 OS << ")"; 507 } 508 509 // Print nontemporal info. 510 if (MMO.isNonTemporal()) 511 OS << "(nontemporal)"; 512 513 return OS; 514} 515 516//===----------------------------------------------------------------------===// 517// MachineInstr Implementation 518//===----------------------------------------------------------------------===// 519 520void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { 521 if (MCID->ImplicitDefs) 522 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) 523 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); 524 if (MCID->ImplicitUses) 525 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) 526 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); 527} 528 529/// MachineInstr ctor - This constructor creates a MachineInstr and adds the 530/// implicit operands. It reserves space for the number of operands specified by 531/// the MCInstrDesc. 532MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, 533 const DebugLoc dl, bool NoImp) 534 : MCID(&tid), Parent(0), Operands(0), NumOperands(0), 535 Flags(0), AsmPrinterFlags(0), 536 NumMemRefs(0), MemRefs(0), debugLoc(dl) { 537 // Reserve space for the expected number of operands. 538 if (unsigned NumOps = MCID->getNumOperands() + 539 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { 540 CapOperands = OperandCapacity::get(NumOps); 541 Operands = MF.allocateOperandArray(CapOperands); 542 } 543 544 if (!NoImp) 545 addImplicitDefUseOperands(MF); 546} 547 548/// MachineInstr ctor - Copies MachineInstr arg exactly 549/// 550MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) 551 : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0), 552 Flags(0), AsmPrinterFlags(0), 553 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), 554 debugLoc(MI.getDebugLoc()) { 555 CapOperands = OperandCapacity::get(MI.getNumOperands()); 556 Operands = MF.allocateOperandArray(CapOperands); 557 558 // Copy operands. 559 for (unsigned i = 0; i != MI.getNumOperands(); ++i) 560 addOperand(MF, MI.getOperand(i)); 561 562 // Copy all the sensible flags. 563 setFlags(MI.Flags); 564} 565 566/// getRegInfo - If this instruction is embedded into a MachineFunction, 567/// return the MachineRegisterInfo object for the current function, otherwise 568/// return null. 569MachineRegisterInfo *MachineInstr::getRegInfo() { 570 if (MachineBasicBlock *MBB = getParent()) 571 return &MBB->getParent()->getRegInfo(); 572 return 0; 573} 574 575/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in 576/// this instruction from their respective use lists. This requires that the 577/// operands already be on their use lists. 578void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { 579 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 580 if (Operands[i].isReg()) 581 MRI.removeRegOperandFromUseList(&Operands[i]); 582} 583 584/// AddRegOperandsToUseLists - Add all of the register operands in 585/// this instruction from their respective use lists. This requires that the 586/// operands not be on their use lists yet. 587void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { 588 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 589 if (Operands[i].isReg()) 590 MRI.addRegOperandToUseList(&Operands[i]); 591} 592 593void MachineInstr::addOperand(const MachineOperand &Op) { 594 MachineBasicBlock *MBB = getParent(); 595 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs"); 596 MachineFunction *MF = MBB->getParent(); 597 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs"); 598 addOperand(*MF, Op); 599} 600 601/// Move NumOps MachineOperands from Src to Dst, with support for overlapping 602/// ranges. If MRI is non-null also update use-def chains. 603static void moveOperands(MachineOperand *Dst, MachineOperand *Src, 604 unsigned NumOps, MachineRegisterInfo *MRI) { 605 if (MRI) 606 return MRI->moveOperands(Dst, Src, NumOps); 607 608 // Here it would be convenient to call memmove, so that isn't allowed because 609 // MachineOperand has a constructor and so isn't a POD type. 610 if (Dst < Src) 611 for (unsigned i = 0; i != NumOps; ++i) 612 new (Dst + i) MachineOperand(Src[i]); 613 else 614 for (unsigned i = NumOps; i ; --i) 615 new (Dst + i - 1) MachineOperand(Src[i - 1]); 616} 617 618/// addOperand - Add the specified operand to the instruction. If it is an 619/// implicit operand, it is added to the end of the operand list. If it is 620/// an explicit operand it is added at the end of the explicit operand list 621/// (before the first implicit operand). 622void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { 623 assert(MCID && "Cannot add operands before providing an instr descriptor"); 624 625 // Check if we're adding one of our existing operands. 626 if (&Op >= Operands && &Op < Operands + NumOperands) { 627 // This is unusual: MI->addOperand(MI->getOperand(i)). 628 // If adding Op requires reallocating or moving existing operands around, 629 // the Op reference could go stale. Support it by copying Op. 630 MachineOperand CopyOp(Op); 631 return addOperand(MF, CopyOp); 632 } 633 634 // Find the insert location for the new operand. Implicit registers go at 635 // the end, everything else goes before the implicit regs. 636 // 637 // FIXME: Allow mixed explicit and implicit operands on inline asm. 638 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as 639 // implicit-defs, but they must not be moved around. See the FIXME in 640 // InstrEmitter.cpp. 641 unsigned OpNo = getNumOperands(); 642 bool isImpReg = Op.isReg() && Op.isImplicit(); 643 if (!isImpReg && !isInlineAsm()) { 644 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { 645 --OpNo; 646 assert(!Operands[OpNo].isTied() && "Cannot move tied operands"); 647 } 648 } 649 650 // OpNo now points as the desired insertion point. Unless this is a variadic 651 // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). 652 // RegMask operands go between the explicit and implicit operands. 653 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() || 654 OpNo < MCID->getNumOperands()) && 655 "Trying to add an operand to a machine instr that is already done!"); 656 657 MachineRegisterInfo *MRI = getRegInfo(); 658 659 // Determine if the Operands array needs to be reallocated. 660 // Save the old capacity and operand array. 661 OperandCapacity OldCap = CapOperands; 662 MachineOperand *OldOperands = Operands; 663 if (!OldOperands || OldCap.getSize() == getNumOperands()) { 664 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1); 665 Operands = MF.allocateOperandArray(CapOperands); 666 // Move the operands before the insertion point. 667 if (OpNo) 668 moveOperands(Operands, OldOperands, OpNo, MRI); 669 } 670 671 // Move the operands following the insertion point. 672 if (OpNo != NumOperands) 673 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo, 674 MRI); 675 ++NumOperands; 676 677 // Deallocate the old operand array. 678 if (OldOperands != Operands && OldOperands) 679 MF.deallocateOperandArray(OldCap, OldOperands); 680 681 // Copy Op into place. It still needs to be inserted into the MRI use lists. 682 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op); 683 NewMO->ParentMI = this; 684 685 // When adding a register operand, tell MRI about it. 686 if (NewMO->isReg()) { 687 // Ensure isOnRegUseList() returns false, regardless of Op's status. 688 NewMO->Contents.Reg.Prev = 0; 689 // Ignore existing ties. This is not a property that can be copied. 690 NewMO->TiedTo = 0; 691 // Add the new operand to MRI, but only for instructions in an MBB. 692 if (MRI) 693 MRI->addRegOperandToUseList(NewMO); 694 // The MCID operand information isn't accurate until we start adding 695 // explicit operands. The implicit operands are added first, then the 696 // explicits are inserted before them. 697 if (!isImpReg) { 698 // Tie uses to defs as indicated in MCInstrDesc. 699 if (NewMO->isUse()) { 700 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); 701 if (DefIdx != -1) 702 tieOperands(DefIdx, OpNo); 703 } 704 // If the register operand is flagged as early, mark the operand as such. 705 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) 706 NewMO->setIsEarlyClobber(true); 707 } 708 } 709} 710 711/// RemoveOperand - Erase an operand from an instruction, leaving it with one 712/// fewer operand than it started with. 713/// 714void MachineInstr::RemoveOperand(unsigned OpNo) { 715 assert(OpNo < getNumOperands() && "Invalid operand number"); 716 untieRegOperand(OpNo); 717 718#ifndef NDEBUG 719 // Moving tied operands would break the ties. 720 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i) 721 if (Operands[i].isReg()) 722 assert(!Operands[i].isTied() && "Cannot move tied operands"); 723#endif 724 725 MachineRegisterInfo *MRI = getRegInfo(); 726 if (MRI && Operands[OpNo].isReg()) 727 MRI->removeRegOperandFromUseList(Operands + OpNo); 728 729 // Don't call the MachineOperand destructor. A lot of this code depends on 730 // MachineOperand having a trivial destructor anyway, and adding a call here 731 // wouldn't make it 'destructor-correct'. 732 733 if (unsigned N = NumOperands - 1 - OpNo) 734 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI); 735 --NumOperands; 736} 737 738/// addMemOperand - Add a MachineMemOperand to the machine instruction. 739/// This function should be used only occasionally. The setMemRefs function 740/// is the primary method for setting up a MachineInstr's MemRefs list. 741void MachineInstr::addMemOperand(MachineFunction &MF, 742 MachineMemOperand *MO) { 743 mmo_iterator OldMemRefs = MemRefs; 744 unsigned OldNumMemRefs = NumMemRefs; 745 746 unsigned NewNum = NumMemRefs + 1; 747 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum); 748 749 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs); 750 NewMemRefs[NewNum - 1] = MO; 751 setMemRefs(NewMemRefs, NewMemRefs + NewNum); 752} 753 754bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { 755 for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) { 756 if (MII->getDesc().getFlags() & Mask) { 757 if (Type == AnyInBundle) 758 return true; 759 } else { 760 if (Type == AllInBundle && !MII->isBundle()) 761 return false; 762 } 763 // This was the last instruction in the bundle. 764 if (!MII->isBundledWithSucc()) 765 return Type == AllInBundle; 766 } 767} 768 769bool MachineInstr::isIdenticalTo(const MachineInstr *Other, 770 MICheckType Check) const { 771 // If opcodes or number of operands are not the same then the two 772 // instructions are obviously not identical. 773 if (Other->getOpcode() != getOpcode() || 774 Other->getNumOperands() != getNumOperands()) 775 return false; 776 777 if (isBundle()) { 778 // Both instructions are bundles, compare MIs inside the bundle. 779 MachineBasicBlock::const_instr_iterator I1 = *this; 780 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); 781 MachineBasicBlock::const_instr_iterator I2 = *Other; 782 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); 783 while (++I1 != E1 && I1->isInsideBundle()) { 784 ++I2; 785 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check)) 786 return false; 787 } 788 } 789 790 // Check operands to make sure they match. 791 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 792 const MachineOperand &MO = getOperand(i); 793 const MachineOperand &OMO = Other->getOperand(i); 794 if (!MO.isReg()) { 795 if (!MO.isIdenticalTo(OMO)) 796 return false; 797 continue; 798 } 799 800 // Clients may or may not want to ignore defs when testing for equality. 801 // For example, machine CSE pass only cares about finding common 802 // subexpressions, so it's safe to ignore virtual register defs. 803 if (MO.isDef()) { 804 if (Check == IgnoreDefs) 805 continue; 806 else if (Check == IgnoreVRegDefs) { 807 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || 808 TargetRegisterInfo::isPhysicalRegister(OMO.getReg())) 809 if (MO.getReg() != OMO.getReg()) 810 return false; 811 } else { 812 if (!MO.isIdenticalTo(OMO)) 813 return false; 814 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) 815 return false; 816 } 817 } else { 818 if (!MO.isIdenticalTo(OMO)) 819 return false; 820 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) 821 return false; 822 } 823 } 824 // If DebugLoc does not match then two dbg.values are not identical. 825 if (isDebugValue()) 826 if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown() 827 && getDebugLoc() != Other->getDebugLoc()) 828 return false; 829 return true; 830} 831 832MachineInstr *MachineInstr::removeFromParent() { 833 assert(getParent() && "Not embedded in a basic block!"); 834 return getParent()->remove(this); 835} 836 837MachineInstr *MachineInstr::removeFromBundle() { 838 assert(getParent() && "Not embedded in a basic block!"); 839 return getParent()->remove_instr(this); 840} 841 842void MachineInstr::eraseFromParent() { 843 assert(getParent() && "Not embedded in a basic block!"); 844 getParent()->erase(this); 845} 846 847void MachineInstr::eraseFromBundle() { 848 assert(getParent() && "Not embedded in a basic block!"); 849 getParent()->erase_instr(this); 850} 851 852/// getNumExplicitOperands - Returns the number of non-implicit operands. 853/// 854unsigned MachineInstr::getNumExplicitOperands() const { 855 unsigned NumOperands = MCID->getNumOperands(); 856 if (!MCID->isVariadic()) 857 return NumOperands; 858 859 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { 860 const MachineOperand &MO = getOperand(i); 861 if (!MO.isReg() || !MO.isImplicit()) 862 NumOperands++; 863 } 864 return NumOperands; 865} 866 867void MachineInstr::bundleWithPred() { 868 assert(!isBundledWithPred() && "MI is already bundled with its predecessor"); 869 setFlag(BundledPred); 870 MachineBasicBlock::instr_iterator Pred = this; 871 --Pred; 872 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags"); 873 Pred->setFlag(BundledSucc); 874} 875 876void MachineInstr::bundleWithSucc() { 877 assert(!isBundledWithSucc() && "MI is already bundled with its successor"); 878 setFlag(BundledSucc); 879 MachineBasicBlock::instr_iterator Succ = this; 880 ++Succ; 881 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags"); 882 Succ->setFlag(BundledPred); 883} 884 885void MachineInstr::unbundleFromPred() { 886 assert(isBundledWithPred() && "MI isn't bundled with its predecessor"); 887 clearFlag(BundledPred); 888 MachineBasicBlock::instr_iterator Pred = this; 889 --Pred; 890 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags"); 891 Pred->clearFlag(BundledSucc); 892} 893 894void MachineInstr::unbundleFromSucc() { 895 assert(isBundledWithSucc() && "MI isn't bundled with its successor"); 896 clearFlag(BundledSucc); 897 MachineBasicBlock::instr_iterator Succ = this; 898 ++Succ; 899 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags"); 900 Succ->clearFlag(BundledPred); 901} 902 903bool MachineInstr::isStackAligningInlineAsm() const { 904 if (isInlineAsm()) { 905 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 906 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 907 return true; 908 } 909 return false; 910} 911 912InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { 913 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"); 914 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 915 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); 916} 917 918int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, 919 unsigned *GroupNo) const { 920 assert(isInlineAsm() && "Expected an inline asm instruction"); 921 assert(OpIdx < getNumOperands() && "OpIdx out of range"); 922 923 // Ignore queries about the initial operands. 924 if (OpIdx < InlineAsm::MIOp_FirstOperand) 925 return -1; 926 927 unsigned Group = 0; 928 unsigned NumOps; 929 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 930 i += NumOps) { 931 const MachineOperand &FlagMO = getOperand(i); 932 // If we reach the implicit register operands, stop looking. 933 if (!FlagMO.isImm()) 934 return -1; 935 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 936 if (i + NumOps > OpIdx) { 937 if (GroupNo) 938 *GroupNo = Group; 939 return i; 940 } 941 ++Group; 942 } 943 return -1; 944} 945 946const TargetRegisterClass* 947MachineInstr::getRegClassConstraint(unsigned OpIdx, 948 const TargetInstrInfo *TII, 949 const TargetRegisterInfo *TRI) const { 950 assert(getParent() && "Can't have an MBB reference here!"); 951 assert(getParent()->getParent() && "Can't have an MF reference here!"); 952 const MachineFunction &MF = *getParent()->getParent(); 953 954 // Most opcodes have fixed constraints in their MCInstrDesc. 955 if (!isInlineAsm()) 956 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); 957 958 if (!getOperand(OpIdx).isReg()) 959 return NULL; 960 961 // For tied uses on inline asm, get the constraint from the def. 962 unsigned DefIdx; 963 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) 964 OpIdx = DefIdx; 965 966 // Inline asm stores register class constraints in the flag word. 967 int FlagIdx = findInlineAsmFlagIdx(OpIdx); 968 if (FlagIdx < 0) 969 return NULL; 970 971 unsigned Flag = getOperand(FlagIdx).getImm(); 972 unsigned RCID; 973 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) 974 return TRI->getRegClass(RCID); 975 976 // Assume that all registers in a memory operand are pointers. 977 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) 978 return TRI->getPointerRegClass(MF); 979 980 return NULL; 981} 982 983/// Return the number of instructions inside the MI bundle, not counting the 984/// header instruction. 985unsigned MachineInstr::getBundleSize() const { 986 MachineBasicBlock::const_instr_iterator I = this; 987 unsigned Size = 0; 988 while (I->isBundledWithSucc()) 989 ++Size, ++I; 990 return Size; 991} 992 993/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of 994/// the specific register or -1 if it is not found. It further tightens 995/// the search criteria to a use that kills the register if isKill is true. 996int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill, 997 const TargetRegisterInfo *TRI) const { 998 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 999 const MachineOperand &MO = getOperand(i); 1000 if (!MO.isReg() || !MO.isUse()) 1001 continue; 1002 unsigned MOReg = MO.getReg(); 1003 if (!MOReg) 1004 continue; 1005 if (MOReg == Reg || 1006 (TRI && 1007 TargetRegisterInfo::isPhysicalRegister(MOReg) && 1008 TargetRegisterInfo::isPhysicalRegister(Reg) && 1009 TRI->isSubRegister(MOReg, Reg))) 1010 if (!isKill || MO.isKill()) 1011 return i; 1012 } 1013 return -1; 1014} 1015 1016/// readsWritesVirtualRegister - Return a pair of bools (reads, writes) 1017/// indicating if this instruction reads or writes Reg. This also considers 1018/// partial defines. 1019std::pair<bool,bool> 1020MachineInstr::readsWritesVirtualRegister(unsigned Reg, 1021 SmallVectorImpl<unsigned> *Ops) const { 1022 bool PartDef = false; // Partial redefine. 1023 bool FullDef = false; // Full define. 1024 bool Use = false; 1025 1026 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1027 const MachineOperand &MO = getOperand(i); 1028 if (!MO.isReg() || MO.getReg() != Reg) 1029 continue; 1030 if (Ops) 1031 Ops->push_back(i); 1032 if (MO.isUse()) 1033 Use |= !MO.isUndef(); 1034 else if (MO.getSubReg() && !MO.isUndef()) 1035 // A partial <def,undef> doesn't count as reading the register. 1036 PartDef = true; 1037 else 1038 FullDef = true; 1039 } 1040 // A partial redefine uses Reg unless there is also a full define. 1041 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); 1042} 1043 1044/// findRegisterDefOperandIdx() - Returns the operand index that is a def of 1045/// the specified register or -1 if it is not found. If isDead is true, defs 1046/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it 1047/// also checks if there is a def of a super-register. 1048int 1049MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, 1050 const TargetRegisterInfo *TRI) const { 1051 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); 1052 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1053 const MachineOperand &MO = getOperand(i); 1054 // Accept regmask operands when Overlap is set. 1055 // Ignore them when looking for a specific def operand (Overlap == false). 1056 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) 1057 return i; 1058 if (!MO.isReg() || !MO.isDef()) 1059 continue; 1060 unsigned MOReg = MO.getReg(); 1061 bool Found = (MOReg == Reg); 1062 if (!Found && TRI && isPhys && 1063 TargetRegisterInfo::isPhysicalRegister(MOReg)) { 1064 if (Overlap) 1065 Found = TRI->regsOverlap(MOReg, Reg); 1066 else 1067 Found = TRI->isSubRegister(MOReg, Reg); 1068 } 1069 if (Found && (!isDead || MO.isDead())) 1070 return i; 1071 } 1072 return -1; 1073} 1074 1075/// findFirstPredOperandIdx() - Find the index of the first operand in the 1076/// operand list that is used to represent the predicate. It returns -1 if 1077/// none is found. 1078int MachineInstr::findFirstPredOperandIdx() const { 1079 // Don't call MCID.findFirstPredOperandIdx() because this variant 1080 // is sometimes called on an instruction that's not yet complete, and 1081 // so the number of operands is less than the MCID indicates. In 1082 // particular, the PTX target does this. 1083 const MCInstrDesc &MCID = getDesc(); 1084 if (MCID.isPredicable()) { 1085 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 1086 if (MCID.OpInfo[i].isPredicate()) 1087 return i; 1088 } 1089 1090 return -1; 1091} 1092 1093// MachineOperand::TiedTo is 4 bits wide. 1094const unsigned TiedMax = 15; 1095 1096/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1097/// 1098/// Use and def operands can be tied together, indicated by a non-zero TiedTo 1099/// field. TiedTo can have these values: 1100/// 1101/// 0: Operand is not tied to anything. 1102/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). 1103/// TiedMax: Tied to an operand >= TiedMax-1. 1104/// 1105/// The tied def must be one of the first TiedMax operands on a normal 1106/// instruction. INLINEASM instructions allow more tied defs. 1107/// 1108void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { 1109 MachineOperand &DefMO = getOperand(DefIdx); 1110 MachineOperand &UseMO = getOperand(UseIdx); 1111 assert(DefMO.isDef() && "DefIdx must be a def operand"); 1112 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1113 assert(!DefMO.isTied() && "Def is already tied to another use"); 1114 assert(!UseMO.isTied() && "Use is already tied to another def"); 1115 1116 if (DefIdx < TiedMax) 1117 UseMO.TiedTo = DefIdx + 1; 1118 else { 1119 // Inline asm can use the group descriptors to find tied operands, but on 1120 // normal instruction, the tied def must be within the first TiedMax 1121 // operands. 1122 assert(isInlineAsm() && "DefIdx out of range"); 1123 UseMO.TiedTo = TiedMax; 1124 } 1125 1126 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1127 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); 1128} 1129 1130/// Given the index of a tied register operand, find the operand it is tied to. 1131/// Defs are tied to uses and vice versa. Returns the index of the tied operand 1132/// which must exist. 1133unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { 1134 const MachineOperand &MO = getOperand(OpIdx); 1135 assert(MO.isTied() && "Operand isn't tied"); 1136 1137 // Normally TiedTo is in range. 1138 if (MO.TiedTo < TiedMax) 1139 return MO.TiedTo - 1; 1140 1141 // Uses on normal instructions can be out of range. 1142 if (!isInlineAsm()) { 1143 // Normal tied defs must be in the 0..TiedMax-1 range. 1144 if (MO.isUse()) 1145 return TiedMax - 1; 1146 // MO is a def. Search for the tied use. 1147 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { 1148 const MachineOperand &UseMO = getOperand(i); 1149 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) 1150 return i; 1151 } 1152 llvm_unreachable("Can't find tied use"); 1153 } 1154 1155 // Now deal with inline asm by parsing the operand group descriptor flags. 1156 // Find the beginning of each operand group. 1157 SmallVector<unsigned, 8> GroupIdx; 1158 unsigned OpIdxGroup = ~0u; 1159 unsigned NumOps; 1160 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; 1161 i += NumOps) { 1162 const MachineOperand &FlagMO = getOperand(i); 1163 assert(FlagMO.isImm() && "Invalid tied operand on inline asm"); 1164 unsigned CurGroup = GroupIdx.size(); 1165 GroupIdx.push_back(i); 1166 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); 1167 // OpIdx belongs to this operand group. 1168 if (OpIdx > i && OpIdx < i + NumOps) 1169 OpIdxGroup = CurGroup; 1170 unsigned TiedGroup; 1171 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) 1172 continue; 1173 // Operands in this group are tied to operands in TiedGroup which must be 1174 // earlier. Find the number of operands between the two groups. 1175 unsigned Delta = i - GroupIdx[TiedGroup]; 1176 1177 // OpIdx is a use tied to TiedGroup. 1178 if (OpIdxGroup == CurGroup) 1179 return OpIdx - Delta; 1180 1181 // OpIdx is a def tied to this use group. 1182 if (OpIdxGroup == TiedGroup) 1183 return OpIdx + Delta; 1184 } 1185 llvm_unreachable("Invalid tied operand on inline asm"); 1186} 1187 1188/// clearKillInfo - Clears kill flags on all operands. 1189/// 1190void MachineInstr::clearKillInfo() { 1191 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1192 MachineOperand &MO = getOperand(i); 1193 if (MO.isReg() && MO.isUse()) 1194 MO.setIsKill(false); 1195 } 1196} 1197 1198void MachineInstr::substituteRegister(unsigned FromReg, 1199 unsigned ToReg, 1200 unsigned SubIdx, 1201 const TargetRegisterInfo &RegInfo) { 1202 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { 1203 if (SubIdx) 1204 ToReg = RegInfo.getSubReg(ToReg, SubIdx); 1205 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1206 MachineOperand &MO = getOperand(i); 1207 if (!MO.isReg() || MO.getReg() != FromReg) 1208 continue; 1209 MO.substPhysReg(ToReg, RegInfo); 1210 } 1211 } else { 1212 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1213 MachineOperand &MO = getOperand(i); 1214 if (!MO.isReg() || MO.getReg() != FromReg) 1215 continue; 1216 MO.substVirtReg(ToReg, SubIdx, RegInfo); 1217 } 1218 } 1219} 1220 1221/// isSafeToMove - Return true if it is safe to move this instruction. If 1222/// SawStore is set to true, it means that there is a store (or call) between 1223/// the instruction's location and its intended destination. 1224bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII, 1225 AliasAnalysis *AA, 1226 bool &SawStore) const { 1227 // Ignore stuff that we obviously can't move. 1228 // 1229 // Treat volatile loads as stores. This is not strictly necessary for 1230 // volatiles, but it is required for atomic loads. It is not allowed to move 1231 // a load across an atomic load with Ordering > Monotonic. 1232 if (mayStore() || isCall() || 1233 (mayLoad() && hasOrderedMemoryRef())) { 1234 SawStore = true; 1235 return false; 1236 } 1237 1238 if (isLabel() || isDebugValue() || 1239 isTerminator() || hasUnmodeledSideEffects()) 1240 return false; 1241 1242 // See if this instruction does a load. If so, we have to guarantee that the 1243 // loaded value doesn't change between the load and the its intended 1244 // destination. The check for isInvariantLoad gives the targe the chance to 1245 // classify the load as always returning a constant, e.g. a constant pool 1246 // load. 1247 if (mayLoad() && !isInvariantLoad(AA)) 1248 // Otherwise, this is a real load. If there is a store between the load and 1249 // end of block, we can't move it. 1250 return !SawStore; 1251 1252 return true; 1253} 1254 1255/// isSafeToReMat - Return true if it's safe to rematerialize the specified 1256/// instruction which defined the specified register instead of copying it. 1257bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII, 1258 AliasAnalysis *AA, 1259 unsigned DstReg) const { 1260 bool SawStore = false; 1261 if (!TII->isTriviallyReMaterializable(this, AA) || 1262 !isSafeToMove(TII, AA, SawStore)) 1263 return false; 1264 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1265 const MachineOperand &MO = getOperand(i); 1266 if (!MO.isReg()) 1267 continue; 1268 // FIXME: For now, do not remat any instruction with register operands. 1269 // Later on, we can loosen the restriction is the register operands have 1270 // not been modified between the def and use. Note, this is different from 1271 // MachineSink because the code is no longer in two-address form (at least 1272 // partially). 1273 if (MO.isUse()) 1274 return false; 1275 else if (!MO.isDead() && MO.getReg() != DstReg) 1276 return false; 1277 } 1278 return true; 1279} 1280 1281/// hasOrderedMemoryRef - Return true if this instruction may have an ordered 1282/// or volatile memory reference, or if the information describing the memory 1283/// reference is not available. Return false if it is known to have no ordered 1284/// memory references. 1285bool MachineInstr::hasOrderedMemoryRef() const { 1286 // An instruction known never to access memory won't have a volatile access. 1287 if (!mayStore() && 1288 !mayLoad() && 1289 !isCall() && 1290 !hasUnmodeledSideEffects()) 1291 return false; 1292 1293 // Otherwise, if the instruction has no memory reference information, 1294 // conservatively assume it wasn't preserved. 1295 if (memoperands_empty()) 1296 return true; 1297 1298 // Check the memory reference information for ordered references. 1299 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) 1300 if (!(*I)->isUnordered()) 1301 return true; 1302 1303 return false; 1304} 1305 1306/// isInvariantLoad - Return true if this instruction is loading from a 1307/// location whose value is invariant across the function. For example, 1308/// loading a value from the constant pool or from the argument area 1309/// of a function if it does not change. This should only return true of 1310/// *all* loads the instruction does are invariant (if it does multiple loads). 1311bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { 1312 // If the instruction doesn't load at all, it isn't an invariant load. 1313 if (!mayLoad()) 1314 return false; 1315 1316 // If the instruction has lost its memoperands, conservatively assume that 1317 // it may not be an invariant load. 1318 if (memoperands_empty()) 1319 return false; 1320 1321 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); 1322 1323 for (mmo_iterator I = memoperands_begin(), 1324 E = memoperands_end(); I != E; ++I) { 1325 if ((*I)->isVolatile()) return false; 1326 if ((*I)->isStore()) return false; 1327 if ((*I)->isInvariant()) return true; 1328 1329 if (const Value *V = (*I)->getValue()) { 1330 // A load from a constant PseudoSourceValue is invariant. 1331 if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) 1332 if (PSV->isConstant(MFI)) 1333 continue; 1334 // If we have an AliasAnalysis, ask it whether the memory is constant. 1335 if (AA && AA->pointsToConstantMemory( 1336 AliasAnalysis::Location(V, (*I)->getSize(), 1337 (*I)->getTBAAInfo()))) 1338 continue; 1339 } 1340 1341 // Otherwise assume conservatively. 1342 return false; 1343 } 1344 1345 // Everything checks out. 1346 return true; 1347} 1348 1349/// isConstantValuePHI - If the specified instruction is a PHI that always 1350/// merges together the same virtual register, return the register, otherwise 1351/// return 0. 1352unsigned MachineInstr::isConstantValuePHI() const { 1353 if (!isPHI()) 1354 return 0; 1355 assert(getNumOperands() >= 3 && 1356 "It's illegal to have a PHI without source operands"); 1357 1358 unsigned Reg = getOperand(1).getReg(); 1359 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) 1360 if (getOperand(i).getReg() != Reg) 1361 return 0; 1362 return Reg; 1363} 1364 1365bool MachineInstr::hasUnmodeledSideEffects() const { 1366 if (hasProperty(MCID::UnmodeledSideEffects)) 1367 return true; 1368 if (isInlineAsm()) { 1369 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1370 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1371 return true; 1372 } 1373 1374 return false; 1375} 1376 1377/// allDefsAreDead - Return true if all the defs of this instruction are dead. 1378/// 1379bool MachineInstr::allDefsAreDead() const { 1380 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) { 1381 const MachineOperand &MO = getOperand(i); 1382 if (!MO.isReg() || MO.isUse()) 1383 continue; 1384 if (!MO.isDead()) 1385 return false; 1386 } 1387 return true; 1388} 1389 1390/// copyImplicitOps - Copy implicit register operands from specified 1391/// instruction to this instruction. 1392void MachineInstr::copyImplicitOps(MachineFunction &MF, 1393 const MachineInstr *MI) { 1394 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); 1395 i != e; ++i) { 1396 const MachineOperand &MO = MI->getOperand(i); 1397 if (MO.isReg() && MO.isImplicit()) 1398 addOperand(MF, MO); 1399 } 1400} 1401 1402void MachineInstr::dump() const { 1403#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 1404 dbgs() << " " << *this; 1405#endif 1406} 1407 1408static void printDebugLoc(DebugLoc DL, const MachineFunction *MF, 1409 raw_ostream &CommentOS) { 1410 const LLVMContext &Ctx = MF->getFunction()->getContext(); 1411 if (!DL.isUnknown()) { // Print source line info. 1412 DIScope Scope(DL.getScope(Ctx)); 1413 // Omit the directory, because it's likely to be long and uninteresting. 1414 if (Scope.Verify()) 1415 CommentOS << Scope.getFilename(); 1416 else 1417 CommentOS << "<unknown>"; 1418 CommentOS << ':' << DL.getLine(); 1419 if (DL.getCol() != 0) 1420 CommentOS << ':' << DL.getCol(); 1421 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx)); 1422 if (!InlinedAtDL.isUnknown()) { 1423 CommentOS << " @[ "; 1424 printDebugLoc(InlinedAtDL, MF, CommentOS); 1425 CommentOS << " ]"; 1426 } 1427 } 1428} 1429 1430void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const { 1431 // We can be a bit tidier if we know the TargetMachine and/or MachineFunction. 1432 const MachineFunction *MF = 0; 1433 const MachineRegisterInfo *MRI = 0; 1434 if (const MachineBasicBlock *MBB = getParent()) { 1435 MF = MBB->getParent(); 1436 if (!TM && MF) 1437 TM = &MF->getTarget(); 1438 if (MF) 1439 MRI = &MF->getRegInfo(); 1440 } 1441 1442 // Save a list of virtual registers. 1443 SmallVector<unsigned, 8> VirtRegs; 1444 1445 // Print explicitly defined operands on the left of an assignment syntax. 1446 unsigned StartOp = 0, e = getNumOperands(); 1447 for (; StartOp < e && getOperand(StartOp).isReg() && 1448 getOperand(StartOp).isDef() && 1449 !getOperand(StartOp).isImplicit(); 1450 ++StartOp) { 1451 if (StartOp != 0) OS << ", "; 1452 getOperand(StartOp).print(OS, TM); 1453 unsigned Reg = getOperand(StartOp).getReg(); 1454 if (TargetRegisterInfo::isVirtualRegister(Reg)) 1455 VirtRegs.push_back(Reg); 1456 } 1457 1458 if (StartOp != 0) 1459 OS << " = "; 1460 1461 // Print the opcode name. 1462 if (TM && TM->getInstrInfo()) 1463 OS << TM->getInstrInfo()->getName(getOpcode()); 1464 else 1465 OS << "UNKNOWN"; 1466 1467 // Print the rest of the operands. 1468 bool OmittedAnyCallClobbers = false; 1469 bool FirstOp = true; 1470 unsigned AsmDescOp = ~0u; 1471 unsigned AsmOpCount = 0; 1472 1473 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { 1474 // Print asm string. 1475 OS << " "; 1476 getOperand(InlineAsm::MIOp_AsmString).print(OS, TM); 1477 1478 // Print HasSideEffects, IsAlignStack 1479 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1480 if (ExtraInfo & InlineAsm::Extra_HasSideEffects) 1481 OS << " [sideeffect]"; 1482 if (ExtraInfo & InlineAsm::Extra_IsAlignStack) 1483 OS << " [alignstack]"; 1484 if (getInlineAsmDialect() == InlineAsm::AD_ATT) 1485 OS << " [attdialect]"; 1486 if (getInlineAsmDialect() == InlineAsm::AD_Intel) 1487 OS << " [inteldialect]"; 1488 1489 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; 1490 FirstOp = false; 1491 } 1492 1493 1494 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 1495 const MachineOperand &MO = getOperand(i); 1496 1497 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1498 VirtRegs.push_back(MO.getReg()); 1499 1500 // Omit call-clobbered registers which aren't used anywhere. This makes 1501 // call instructions much less noisy on targets where calls clobber lots 1502 // of registers. Don't rely on MO.isDead() because we may be called before 1503 // LiveVariables is run, or we may be looking at a non-allocatable reg. 1504 if (MF && isCall() && 1505 MO.isReg() && MO.isImplicit() && MO.isDef()) { 1506 unsigned Reg = MO.getReg(); 1507 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { 1508 const MachineRegisterInfo &MRI = MF->getRegInfo(); 1509 if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) { 1510 bool HasAliasLive = false; 1511 for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true); 1512 AI.isValid(); ++AI) { 1513 unsigned AliasReg = *AI; 1514 if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) { 1515 HasAliasLive = true; 1516 break; 1517 } 1518 } 1519 if (!HasAliasLive) { 1520 OmittedAnyCallClobbers = true; 1521 continue; 1522 } 1523 } 1524 } 1525 } 1526 1527 if (FirstOp) FirstOp = false; else OS << ","; 1528 OS << " "; 1529 if (i < getDesc().NumOperands) { 1530 const MCOperandInfo &MCOI = getDesc().OpInfo[i]; 1531 if (MCOI.isPredicate()) 1532 OS << "pred:"; 1533 if (MCOI.isOptionalDef()) 1534 OS << "opt:"; 1535 } 1536 if (isDebugValue() && MO.isMetadata()) { 1537 // Pretty print DBG_VALUE instructions. 1538 const MDNode *MD = MO.getMetadata(); 1539 if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2))) 1540 OS << "!\"" << MDS->getString() << '\"'; 1541 else 1542 MO.print(OS, TM); 1543 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { 1544 OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm()); 1545 } else if (i == AsmDescOp && MO.isImm()) { 1546 // Pretty print the inline asm operand descriptor. 1547 OS << '$' << AsmOpCount++; 1548 unsigned Flag = MO.getImm(); 1549 switch (InlineAsm::getKind(Flag)) { 1550 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; 1551 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; 1552 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; 1553 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; 1554 case InlineAsm::Kind_Imm: OS << ":[imm"; break; 1555 case InlineAsm::Kind_Mem: OS << ":[mem"; break; 1556 default: OS << ":[??" << InlineAsm::getKind(Flag); break; 1557 } 1558 1559 unsigned RCID = 0; 1560 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { 1561 if (TM) 1562 OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName(); 1563 else 1564 OS << ":RC" << RCID; 1565 } 1566 1567 unsigned TiedTo = 0; 1568 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) 1569 OS << " tiedto:$" << TiedTo; 1570 1571 OS << ']'; 1572 1573 // Compute the index of the next operand descriptor. 1574 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); 1575 } else 1576 MO.print(OS, TM); 1577 } 1578 1579 // Briefly indicate whether any call clobbers were omitted. 1580 if (OmittedAnyCallClobbers) { 1581 if (!FirstOp) OS << ","; 1582 OS << " ..."; 1583 } 1584 1585 bool HaveSemi = false; 1586 const unsigned PrintableFlags = FrameSetup; 1587 if (Flags & PrintableFlags) { 1588 if (!HaveSemi) OS << ";"; HaveSemi = true; 1589 OS << " flags: "; 1590 1591 if (Flags & FrameSetup) 1592 OS << "FrameSetup"; 1593 } 1594 1595 if (!memoperands_empty()) { 1596 if (!HaveSemi) OS << ";"; HaveSemi = true; 1597 1598 OS << " mem:"; 1599 for (mmo_iterator i = memoperands_begin(), e = memoperands_end(); 1600 i != e; ++i) { 1601 OS << **i; 1602 if (llvm::next(i) != e) 1603 OS << " "; 1604 } 1605 } 1606 1607 // Print the regclass of any virtual registers encountered. 1608 if (MRI && !VirtRegs.empty()) { 1609 if (!HaveSemi) OS << ";"; HaveSemi = true; 1610 for (unsigned i = 0; i != VirtRegs.size(); ++i) { 1611 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); 1612 OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]); 1613 for (unsigned j = i+1; j != VirtRegs.size();) { 1614 if (MRI->getRegClass(VirtRegs[j]) != RC) { 1615 ++j; 1616 continue; 1617 } 1618 if (VirtRegs[i] != VirtRegs[j]) 1619 OS << "," << PrintReg(VirtRegs[j]); 1620 VirtRegs.erase(VirtRegs.begin()+j); 1621 } 1622 } 1623 } 1624 1625 // Print debug location information. 1626 if (isDebugValue() && getOperand(e - 1).isMetadata()) { 1627 if (!HaveSemi) OS << ";"; HaveSemi = true; 1628 DIVariable DV(getOperand(e - 1).getMetadata()); 1629 OS << " line no:" << DV.getLineNumber(); 1630 if (MDNode *InlinedAt = DV.getInlinedAt()) { 1631 DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt); 1632 if (!InlinedAtDL.isUnknown()) { 1633 OS << " inlined @[ "; 1634 printDebugLoc(InlinedAtDL, MF, OS); 1635 OS << " ]"; 1636 } 1637 } 1638 } else if (!debugLoc.isUnknown() && MF) { 1639 if (!HaveSemi) OS << ";"; HaveSemi = true; 1640 OS << " dbg:"; 1641 printDebugLoc(debugLoc, MF, OS); 1642 } 1643 1644 OS << '\n'; 1645} 1646 1647bool MachineInstr::addRegisterKilled(unsigned IncomingReg, 1648 const TargetRegisterInfo *RegInfo, 1649 bool AddIfNotFound) { 1650 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1651 bool hasAliases = isPhysReg && 1652 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1653 bool Found = false; 1654 SmallVector<unsigned,4> DeadOps; 1655 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1656 MachineOperand &MO = getOperand(i); 1657 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) 1658 continue; 1659 unsigned Reg = MO.getReg(); 1660 if (!Reg) 1661 continue; 1662 1663 if (Reg == IncomingReg) { 1664 if (!Found) { 1665 if (MO.isKill()) 1666 // The register is already marked kill. 1667 return true; 1668 if (isPhysReg && isRegTiedToDefOperand(i)) 1669 // Two-address uses of physregs must not be marked kill. 1670 return true; 1671 MO.setIsKill(); 1672 Found = true; 1673 } 1674 } else if (hasAliases && MO.isKill() && 1675 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1676 // A super-register kill already exists. 1677 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1678 return true; 1679 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1680 DeadOps.push_back(i); 1681 } 1682 } 1683 1684 // Trim unneeded kill operands. 1685 while (!DeadOps.empty()) { 1686 unsigned OpIdx = DeadOps.back(); 1687 if (getOperand(OpIdx).isImplicit()) 1688 RemoveOperand(OpIdx); 1689 else 1690 getOperand(OpIdx).setIsKill(false); 1691 DeadOps.pop_back(); 1692 } 1693 1694 // If not found, this means an alias of one of the operands is killed. Add a 1695 // new implicit operand if required. 1696 if (!Found && AddIfNotFound) { 1697 addOperand(MachineOperand::CreateReg(IncomingReg, 1698 false /*IsDef*/, 1699 true /*IsImp*/, 1700 true /*IsKill*/)); 1701 return true; 1702 } 1703 return Found; 1704} 1705 1706void MachineInstr::clearRegisterKills(unsigned Reg, 1707 const TargetRegisterInfo *RegInfo) { 1708 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) 1709 RegInfo = 0; 1710 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1711 MachineOperand &MO = getOperand(i); 1712 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) 1713 continue; 1714 unsigned OpReg = MO.getReg(); 1715 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) 1716 MO.setIsKill(false); 1717 } 1718} 1719 1720bool MachineInstr::addRegisterDead(unsigned IncomingReg, 1721 const TargetRegisterInfo *RegInfo, 1722 bool AddIfNotFound) { 1723 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); 1724 bool hasAliases = isPhysReg && 1725 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); 1726 bool Found = false; 1727 SmallVector<unsigned,4> DeadOps; 1728 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1729 MachineOperand &MO = getOperand(i); 1730 if (!MO.isReg() || !MO.isDef()) 1731 continue; 1732 unsigned Reg = MO.getReg(); 1733 if (!Reg) 1734 continue; 1735 1736 if (Reg == IncomingReg) { 1737 MO.setIsDead(); 1738 Found = true; 1739 } else if (hasAliases && MO.isDead() && 1740 TargetRegisterInfo::isPhysicalRegister(Reg)) { 1741 // There exists a super-register that's marked dead. 1742 if (RegInfo->isSuperRegister(IncomingReg, Reg)) 1743 return true; 1744 if (RegInfo->isSubRegister(IncomingReg, Reg)) 1745 DeadOps.push_back(i); 1746 } 1747 } 1748 1749 // Trim unneeded dead operands. 1750 while (!DeadOps.empty()) { 1751 unsigned OpIdx = DeadOps.back(); 1752 if (getOperand(OpIdx).isImplicit()) 1753 RemoveOperand(OpIdx); 1754 else 1755 getOperand(OpIdx).setIsDead(false); 1756 DeadOps.pop_back(); 1757 } 1758 1759 // If not found, this means an alias of one of the operands is dead. Add a 1760 // new implicit operand if required. 1761 if (Found || !AddIfNotFound) 1762 return Found; 1763 1764 addOperand(MachineOperand::CreateReg(IncomingReg, 1765 true /*IsDef*/, 1766 true /*IsImp*/, 1767 false /*IsKill*/, 1768 true /*IsDead*/)); 1769 return true; 1770} 1771 1772void MachineInstr::addRegisterDefined(unsigned IncomingReg, 1773 const TargetRegisterInfo *RegInfo) { 1774 if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { 1775 MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo); 1776 if (MO) 1777 return; 1778 } else { 1779 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1780 const MachineOperand &MO = getOperand(i); 1781 if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() && 1782 MO.getSubReg() == 0) 1783 return; 1784 } 1785 } 1786 addOperand(MachineOperand::CreateReg(IncomingReg, 1787 true /*IsDef*/, 1788 true /*IsImp*/)); 1789} 1790 1791void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, 1792 const TargetRegisterInfo &TRI) { 1793 bool HasRegMask = false; 1794 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { 1795 MachineOperand &MO = getOperand(i); 1796 if (MO.isRegMask()) { 1797 HasRegMask = true; 1798 continue; 1799 } 1800 if (!MO.isReg() || !MO.isDef()) continue; 1801 unsigned Reg = MO.getReg(); 1802 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; 1803 bool Dead = true; 1804 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1805 I != E; ++I) 1806 if (TRI.regsOverlap(*I, Reg)) { 1807 Dead = false; 1808 break; 1809 } 1810 // If there are no uses, including partial uses, the def is dead. 1811 if (Dead) MO.setIsDead(); 1812 } 1813 1814 // This is a call with a register mask operand. 1815 // Mask clobbers are always dead, so add defs for the non-dead defines. 1816 if (HasRegMask) 1817 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); 1818 I != E; ++I) 1819 addRegisterDefined(*I, &TRI); 1820} 1821 1822unsigned 1823MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { 1824 // Build up a buffer of hash code components. 1825 SmallVector<size_t, 8> HashComponents; 1826 HashComponents.reserve(MI->getNumOperands() + 1); 1827 HashComponents.push_back(MI->getOpcode()); 1828 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1829 const MachineOperand &MO = MI->getOperand(i); 1830 if (MO.isReg() && MO.isDef() && 1831 TargetRegisterInfo::isVirtualRegister(MO.getReg())) 1832 continue; // Skip virtual register defs. 1833 1834 HashComponents.push_back(hash_value(MO)); 1835 } 1836 return hash_combine_range(HashComponents.begin(), HashComponents.end()); 1837} 1838 1839void MachineInstr::emitError(StringRef Msg) const { 1840 // Find the source location cookie. 1841 unsigned LocCookie = 0; 1842 const MDNode *LocMD = 0; 1843 for (unsigned i = getNumOperands(); i != 0; --i) { 1844 if (getOperand(i-1).isMetadata() && 1845 (LocMD = getOperand(i-1).getMetadata()) && 1846 LocMD->getNumOperands() != 0) { 1847 if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) { 1848 LocCookie = CI->getZExtValue(); 1849 break; 1850 } 1851 } 1852 } 1853 1854 if (const MachineBasicBlock *MBB = getParent()) 1855 if (const MachineFunction *MF = MBB->getParent()) 1856 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); 1857 report_fatal_error(Msg); 1858} 1859