MachineInstr.cpp revision b47a4f7a0a780eb256cf090e01c5a002fff6684e 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/FoldingSet.h"
16#include "llvm/ADT/Hashing.h"
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/Assembly/Writer.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/Constants.h"
26#include "llvm/DebugInfo.h"
27#include "llvm/Function.h"
28#include "llvm/InlineAsm.h"
29#include "llvm/LLVMContext.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Metadata.h"
33#include "llvm/Module.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetMachine.h"
41#include "llvm/Target/TargetRegisterInfo.h"
42#include "llvm/Type.h"
43#include "llvm/Value.h"
44using namespace llvm;
45
46//===----------------------------------------------------------------------===//
47// MachineOperand Implementation
48//===----------------------------------------------------------------------===//
49
50void MachineOperand::setReg(unsigned Reg) {
51  if (getReg() == Reg) return; // No change.
52
53  // Otherwise, we have to change the register.  If this operand is embedded
54  // into a machine function, we need to update the old and new register's
55  // use/def lists.
56  if (MachineInstr *MI = getParent())
57    if (MachineBasicBlock *MBB = MI->getParent())
58      if (MachineFunction *MF = MBB->getParent()) {
59        MachineRegisterInfo &MRI = MF->getRegInfo();
60        MRI.removeRegOperandFromUseList(this);
61        SmallContents.RegNo = Reg;
62        MRI.addRegOperandToUseList(this);
63        return;
64      }
65
66  // Otherwise, just change the register, no problem.  :)
67  SmallContents.RegNo = Reg;
68}
69
70void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71                                  const TargetRegisterInfo &TRI) {
72  assert(TargetRegisterInfo::isVirtualRegister(Reg));
73  if (SubIdx && getSubReg())
74    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75  setReg(Reg);
76  if (SubIdx)
77    setSubReg(SubIdx);
78}
79
80void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
82  if (getSubReg()) {
83    Reg = TRI.getSubReg(Reg, getSubReg());
84    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85    // That won't happen in legal code.
86    setSubReg(0);
87  }
88  setReg(Reg);
89}
90
91/// Change a def to a use, or a use to a def.
92void MachineOperand::setIsDef(bool Val) {
93  assert(isReg() && "Wrong MachineOperand accessor");
94  assert((!Val || !isDebug()) && "Marking a debug operation as def");
95  if (IsDef == Val)
96    return;
97  // MRI may keep uses and defs in different list positions.
98  if (MachineInstr *MI = getParent())
99    if (MachineBasicBlock *MBB = MI->getParent())
100      if (MachineFunction *MF = MBB->getParent()) {
101        MachineRegisterInfo &MRI = MF->getRegInfo();
102        MRI.removeRegOperandFromUseList(this);
103        IsDef = Val;
104        MRI.addRegOperandToUseList(this);
105        return;
106      }
107  IsDef = Val;
108}
109
110/// ChangeToImmediate - Replace this operand with a new immediate operand of
111/// the specified value.  If an operand is known to be an immediate already,
112/// the setImm method should be used.
113void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
114  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
115  // If this operand is currently a register operand, and if this is in a
116  // function, deregister the operand from the register's use/def list.
117  if (isReg() && isOnRegUseList())
118    if (MachineInstr *MI = getParent())
119      if (MachineBasicBlock *MBB = MI->getParent())
120        if (MachineFunction *MF = MBB->getParent())
121          MF->getRegInfo().removeRegOperandFromUseList(this);
122
123  OpKind = MO_Immediate;
124  Contents.ImmVal = ImmVal;
125}
126
127/// ChangeToRegister - Replace this operand with a new register operand of
128/// the specified value.  If an operand is known to be an register already,
129/// the setReg method should be used.
130void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
131                                      bool isKill, bool isDead, bool isUndef,
132                                      bool isDebug) {
133  MachineRegisterInfo *RegInfo = 0;
134  if (MachineInstr *MI = getParent())
135    if (MachineBasicBlock *MBB = MI->getParent())
136      if (MachineFunction *MF = MBB->getParent())
137        RegInfo = &MF->getRegInfo();
138  // If this operand is already a register operand, remove it from the
139  // register's use/def lists.
140  bool WasReg = isReg();
141  if (RegInfo && WasReg)
142    RegInfo->removeRegOperandFromUseList(this);
143
144  // Change this to a register and set the reg#.
145  OpKind = MO_Register;
146  SmallContents.RegNo = Reg;
147  SubReg = 0;
148  IsDef = isDef;
149  IsImp = isImp;
150  IsKill = isKill;
151  IsDead = isDead;
152  IsUndef = isUndef;
153  IsInternalRead = false;
154  IsEarlyClobber = false;
155  IsDebug = isDebug;
156  // Ensure isOnRegUseList() returns false.
157  Contents.Reg.Prev = 0;
158  // Preserve the tie when the operand was already a register.
159  if (!WasReg)
160    TiedTo = 0;
161
162  // If this operand is embedded in a function, add the operand to the
163  // register's use/def list.
164  if (RegInfo)
165    RegInfo->addRegOperandToUseList(this);
166}
167
168/// isIdenticalTo - Return true if this operand is identical to the specified
169/// operand. Note that this should stay in sync with the hash_value overload
170/// below.
171bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
172  if (getType() != Other.getType() ||
173      getTargetFlags() != Other.getTargetFlags())
174    return false;
175
176  switch (getType()) {
177  case MachineOperand::MO_Register:
178    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
179           getSubReg() == Other.getSubReg();
180  case MachineOperand::MO_Immediate:
181    return getImm() == Other.getImm();
182  case MachineOperand::MO_CImmediate:
183    return getCImm() == Other.getCImm();
184  case MachineOperand::MO_FPImmediate:
185    return getFPImm() == Other.getFPImm();
186  case MachineOperand::MO_MachineBasicBlock:
187    return getMBB() == Other.getMBB();
188  case MachineOperand::MO_FrameIndex:
189    return getIndex() == Other.getIndex();
190  case MachineOperand::MO_ConstantPoolIndex:
191  case MachineOperand::MO_TargetIndex:
192    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
193  case MachineOperand::MO_JumpTableIndex:
194    return getIndex() == Other.getIndex();
195  case MachineOperand::MO_GlobalAddress:
196    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
197  case MachineOperand::MO_ExternalSymbol:
198    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
199           getOffset() == Other.getOffset();
200  case MachineOperand::MO_BlockAddress:
201    return getBlockAddress() == Other.getBlockAddress() &&
202           getOffset() == Other.getOffset();
203  case MO_RegisterMask:
204    return getRegMask() == Other.getRegMask();
205  case MachineOperand::MO_MCSymbol:
206    return getMCSymbol() == Other.getMCSymbol();
207  case MachineOperand::MO_Metadata:
208    return getMetadata() == Other.getMetadata();
209  }
210  llvm_unreachable("Invalid machine operand type");
211}
212
213// Note: this must stay exactly in sync with isIdenticalTo above.
214hash_code llvm::hash_value(const MachineOperand &MO) {
215  switch (MO.getType()) {
216  case MachineOperand::MO_Register:
217    // Register operands don't have target flags.
218    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
219  case MachineOperand::MO_Immediate:
220    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
221  case MachineOperand::MO_CImmediate:
222    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
223  case MachineOperand::MO_FPImmediate:
224    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
225  case MachineOperand::MO_MachineBasicBlock:
226    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
227  case MachineOperand::MO_FrameIndex:
228    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
229  case MachineOperand::MO_ConstantPoolIndex:
230  case MachineOperand::MO_TargetIndex:
231    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
232                        MO.getOffset());
233  case MachineOperand::MO_JumpTableIndex:
234    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
235  case MachineOperand::MO_ExternalSymbol:
236    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
237                        MO.getSymbolName());
238  case MachineOperand::MO_GlobalAddress:
239    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
240                        MO.getOffset());
241  case MachineOperand::MO_BlockAddress:
242    return hash_combine(MO.getType(), MO.getTargetFlags(),
243                        MO.getBlockAddress(), MO.getOffset());
244  case MachineOperand::MO_RegisterMask:
245    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
246  case MachineOperand::MO_Metadata:
247    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
248  case MachineOperand::MO_MCSymbol:
249    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
250  }
251  llvm_unreachable("Invalid machine operand type");
252}
253
254/// print - Print the specified machine operand.
255///
256void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
257  // If the instruction is embedded into a basic block, we can find the
258  // target info for the instruction.
259  if (!TM)
260    if (const MachineInstr *MI = getParent())
261      if (const MachineBasicBlock *MBB = MI->getParent())
262        if (const MachineFunction *MF = MBB->getParent())
263          TM = &MF->getTarget();
264  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
265
266  switch (getType()) {
267  case MachineOperand::MO_Register:
268    OS << PrintReg(getReg(), TRI, getSubReg());
269
270    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
271        isInternalRead() || isEarlyClobber() || isTied()) {
272      OS << '<';
273      bool NeedComma = false;
274      if (isDef()) {
275        if (NeedComma) OS << ',';
276        if (isEarlyClobber())
277          OS << "earlyclobber,";
278        if (isImplicit())
279          OS << "imp-";
280        OS << "def";
281        NeedComma = true;
282        // <def,read-undef> only makes sense when getSubReg() is set.
283        // Don't clutter the output otherwise.
284        if (isUndef() && getSubReg())
285          OS << ",read-undef";
286      } else if (isImplicit()) {
287          OS << "imp-use";
288          NeedComma = true;
289      }
290
291      if (isKill()) {
292        if (NeedComma) OS << ',';
293        OS << "kill";
294        NeedComma = true;
295      }
296      if (isDead()) {
297        if (NeedComma) OS << ',';
298        OS << "dead";
299        NeedComma = true;
300      }
301      if (isUndef() && isUse()) {
302        if (NeedComma) OS << ',';
303        OS << "undef";
304        NeedComma = true;
305      }
306      if (isInternalRead()) {
307        if (NeedComma) OS << ',';
308        OS << "internal";
309        NeedComma = true;
310      }
311      if (isTied()) {
312        if (NeedComma) OS << ',';
313        OS << "tied";
314        if (TiedTo != 15)
315          OS << unsigned(TiedTo - 1);
316        NeedComma = true;
317      }
318      OS << '>';
319    }
320    break;
321  case MachineOperand::MO_Immediate:
322    OS << getImm();
323    break;
324  case MachineOperand::MO_CImmediate:
325    getCImm()->getValue().print(OS, false);
326    break;
327  case MachineOperand::MO_FPImmediate:
328    if (getFPImm()->getType()->isFloatTy())
329      OS << getFPImm()->getValueAPF().convertToFloat();
330    else
331      OS << getFPImm()->getValueAPF().convertToDouble();
332    break;
333  case MachineOperand::MO_MachineBasicBlock:
334    OS << "<BB#" << getMBB()->getNumber() << ">";
335    break;
336  case MachineOperand::MO_FrameIndex:
337    OS << "<fi#" << getIndex() << '>';
338    break;
339  case MachineOperand::MO_ConstantPoolIndex:
340    OS << "<cp#" << getIndex();
341    if (getOffset()) OS << "+" << getOffset();
342    OS << '>';
343    break;
344  case MachineOperand::MO_TargetIndex:
345    OS << "<ti#" << getIndex();
346    if (getOffset()) OS << "+" << getOffset();
347    OS << '>';
348    break;
349  case MachineOperand::MO_JumpTableIndex:
350    OS << "<jt#" << getIndex() << '>';
351    break;
352  case MachineOperand::MO_GlobalAddress:
353    OS << "<ga:";
354    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
355    if (getOffset()) OS << "+" << getOffset();
356    OS << '>';
357    break;
358  case MachineOperand::MO_ExternalSymbol:
359    OS << "<es:" << getSymbolName();
360    if (getOffset()) OS << "+" << getOffset();
361    OS << '>';
362    break;
363  case MachineOperand::MO_BlockAddress:
364    OS << '<';
365    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
366    if (getOffset()) OS << "+" << getOffset();
367    OS << '>';
368    break;
369  case MachineOperand::MO_RegisterMask:
370    OS << "<regmask>";
371    break;
372  case MachineOperand::MO_Metadata:
373    OS << '<';
374    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
375    OS << '>';
376    break;
377  case MachineOperand::MO_MCSymbol:
378    OS << "<MCSym=" << *getMCSymbol() << '>';
379    break;
380  }
381
382  if (unsigned TF = getTargetFlags())
383    OS << "[TF=" << TF << ']';
384}
385
386//===----------------------------------------------------------------------===//
387// MachineMemOperand Implementation
388//===----------------------------------------------------------------------===//
389
390/// getAddrSpace - Return the LLVM IR address space number that this pointer
391/// points into.
392unsigned MachinePointerInfo::getAddrSpace() const {
393  if (V == 0) return 0;
394  return cast<PointerType>(V->getType())->getAddressSpace();
395}
396
397/// getConstantPool - Return a MachinePointerInfo record that refers to the
398/// constant pool.
399MachinePointerInfo MachinePointerInfo::getConstantPool() {
400  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
401}
402
403/// getFixedStack - Return a MachinePointerInfo record that refers to the
404/// the specified FrameIndex.
405MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
406  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
407}
408
409MachinePointerInfo MachinePointerInfo::getJumpTable() {
410  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
411}
412
413MachinePointerInfo MachinePointerInfo::getGOT() {
414  return MachinePointerInfo(PseudoSourceValue::getGOT());
415}
416
417MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
418  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
419}
420
421MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
422                                     uint64_t s, unsigned int a,
423                                     const MDNode *TBAAInfo,
424                                     const MDNode *Ranges)
425  : PtrInfo(ptrinfo), Size(s),
426    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
427    TBAAInfo(TBAAInfo), Ranges(Ranges) {
428  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
429         "invalid pointer value");
430  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
431  assert((isLoad() || isStore()) && "Not a load/store!");
432}
433
434/// Profile - Gather unique data for the object.
435///
436void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
437  ID.AddInteger(getOffset());
438  ID.AddInteger(Size);
439  ID.AddPointer(getValue());
440  ID.AddInteger(Flags);
441}
442
443void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
444  // The Value and Offset may differ due to CSE. But the flags and size
445  // should be the same.
446  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
447  assert(MMO->getSize() == getSize() && "Size mismatch!");
448
449  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
450    // Update the alignment value.
451    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
452      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
453    // Also update the base and offset, because the new alignment may
454    // not be applicable with the old ones.
455    PtrInfo = MMO->PtrInfo;
456  }
457}
458
459/// getAlignment - Return the minimum known alignment in bytes of the
460/// actual memory reference.
461uint64_t MachineMemOperand::getAlignment() const {
462  return MinAlign(getBaseAlignment(), getOffset());
463}
464
465raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
466  assert((MMO.isLoad() || MMO.isStore()) &&
467         "SV has to be a load, store or both.");
468
469  if (MMO.isVolatile())
470    OS << "Volatile ";
471
472  if (MMO.isLoad())
473    OS << "LD";
474  if (MMO.isStore())
475    OS << "ST";
476  OS << MMO.getSize();
477
478  // Print the address information.
479  OS << "[";
480  if (!MMO.getValue())
481    OS << "<unknown>";
482  else
483    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
484
485  // If the alignment of the memory reference itself differs from the alignment
486  // of the base pointer, print the base alignment explicitly, next to the base
487  // pointer.
488  if (MMO.getBaseAlignment() != MMO.getAlignment())
489    OS << "(align=" << MMO.getBaseAlignment() << ")";
490
491  if (MMO.getOffset() != 0)
492    OS << "+" << MMO.getOffset();
493  OS << "]";
494
495  // Print the alignment of the reference.
496  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
497      MMO.getBaseAlignment() != MMO.getSize())
498    OS << "(align=" << MMO.getAlignment() << ")";
499
500  // Print TBAA info.
501  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
502    OS << "(tbaa=";
503    if (TBAAInfo->getNumOperands() > 0)
504      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
505    else
506      OS << "<unknown>";
507    OS << ")";
508  }
509
510  // Print nontemporal info.
511  if (MMO.isNonTemporal())
512    OS << "(nontemporal)";
513
514  return OS;
515}
516
517//===----------------------------------------------------------------------===//
518// MachineInstr Implementation
519//===----------------------------------------------------------------------===//
520
521void MachineInstr::addImplicitDefUseOperands() {
522  if (MCID->ImplicitDefs)
523    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
524      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
525  if (MCID->ImplicitUses)
526    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
527      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
528}
529
530/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
531/// implicit operands. It reserves space for the number of operands specified by
532/// the MCInstrDesc.
533MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
534                           bool NoImp)
535  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
536    NumMemRefs(0), MemRefs(0), Parent(0), debugLoc(dl) {
537  unsigned NumImplicitOps = 0;
538  if (!NoImp)
539    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
540  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
541  if (!NoImp)
542    addImplicitDefUseOperands();
543  // Make sure that we get added to a machine basicblock
544  LeakDetector::addGarbageObject(this);
545}
546
547/// MachineInstr ctor - Copies MachineInstr arg exactly
548///
549MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
550  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
551    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
552    Parent(0), debugLoc(MI.getDebugLoc()) {
553  Operands.reserve(MI.getNumOperands());
554
555  // Add operands
556  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
557    addOperand(MI.getOperand(i));
558
559  // Copy all the flags.
560  Flags = MI.Flags;
561
562  // Set parent to null.
563  Parent = 0;
564
565  LeakDetector::addGarbageObject(this);
566}
567
568MachineInstr::~MachineInstr() {
569  LeakDetector::removeGarbageObject(this);
570#ifndef NDEBUG
571  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
572    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
573    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
574           "Reg operand def/use list corrupted");
575  }
576#endif
577}
578
579/// getRegInfo - If this instruction is embedded into a MachineFunction,
580/// return the MachineRegisterInfo object for the current function, otherwise
581/// return null.
582MachineRegisterInfo *MachineInstr::getRegInfo() {
583  if (MachineBasicBlock *MBB = getParent())
584    return &MBB->getParent()->getRegInfo();
585  return 0;
586}
587
588/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
589/// this instruction from their respective use lists.  This requires that the
590/// operands already be on their use lists.
591void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
592  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
593    if (Operands[i].isReg())
594      MRI.removeRegOperandFromUseList(&Operands[i]);
595}
596
597/// AddRegOperandsToUseLists - Add all of the register operands in
598/// this instruction from their respective use lists.  This requires that the
599/// operands not be on their use lists yet.
600void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
601  for (unsigned i = 0, e = Operands.size(); i != e; ++i)
602    if (Operands[i].isReg())
603      MRI.addRegOperandToUseList(&Operands[i]);
604}
605
606/// addOperand - Add the specified operand to the instruction.  If it is an
607/// implicit operand, it is added to the end of the operand list.  If it is
608/// an explicit operand it is added at the end of the explicit operand list
609/// (before the first implicit operand).
610void MachineInstr::addOperand(const MachineOperand &Op) {
611  assert(MCID && "Cannot add operands before providing an instr descriptor");
612  bool isImpReg = Op.isReg() && Op.isImplicit();
613  MachineRegisterInfo *RegInfo = getRegInfo();
614
615  // If the Operands backing store is reallocated, all register operands must
616  // be removed and re-added to RegInfo.  It is storing pointers to operands.
617  bool Reallocate = RegInfo &&
618    !Operands.empty() && Operands.size() == Operands.capacity();
619
620  // Find the insert location for the new operand.  Implicit registers go at
621  // the end, everything goes before the implicit regs.
622  unsigned OpNo = Operands.size();
623
624  // Remove all the implicit operands from RegInfo if they need to be shifted.
625  // FIXME: Allow mixed explicit and implicit operands on inline asm.
626  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
627  // implicit-defs, but they must not be moved around.  See the FIXME in
628  // InstrEmitter.cpp.
629  if (!isImpReg && !isInlineAsm()) {
630    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
631      --OpNo;
632      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
633      if (RegInfo)
634        RegInfo->removeRegOperandFromUseList(&Operands[OpNo]);
635    }
636  }
637
638  // OpNo now points as the desired insertion point.  Unless this is a variadic
639  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
640  // RegMask operands go between the explicit and implicit operands.
641  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
642          OpNo < MCID->getNumOperands()) &&
643         "Trying to add an operand to a machine instr that is already done!");
644
645  // All operands from OpNo have been removed from RegInfo.  If the Operands
646  // backing store needs to be reallocated, we also need to remove any other
647  // register operands.
648  if (Reallocate)
649    for (unsigned i = 0; i != OpNo; ++i)
650      if (Operands[i].isReg())
651        RegInfo->removeRegOperandFromUseList(&Operands[i]);
652
653  // Insert the new operand at OpNo.
654  Operands.insert(Operands.begin() + OpNo, Op);
655  Operands[OpNo].ParentMI = this;
656
657  // The Operands backing store has now been reallocated, so we can re-add the
658  // operands before OpNo.
659  if (Reallocate)
660    for (unsigned i = 0; i != OpNo; ++i)
661      if (Operands[i].isReg())
662        RegInfo->addRegOperandToUseList(&Operands[i]);
663
664  // When adding a register operand, tell RegInfo about it.
665  if (Operands[OpNo].isReg()) {
666    // Ensure isOnRegUseList() returns false, regardless of Op's status.
667    Operands[OpNo].Contents.Reg.Prev = 0;
668    // Ignore existing ties. This is not a property that can be copied.
669    Operands[OpNo].TiedTo = 0;
670    // Add the new operand to RegInfo.
671    if (RegInfo)
672      RegInfo->addRegOperandToUseList(&Operands[OpNo]);
673    // The MCID operand information isn't accurate until we start adding
674    // explicit operands. The implicit operands are added first, then the
675    // explicits are inserted before them.
676    if (!isImpReg) {
677      // Tie uses to defs as indicated in MCInstrDesc.
678      if (Operands[OpNo].isUse()) {
679        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
680        if (DefIdx != -1)
681          tieOperands(DefIdx, OpNo);
682      }
683      // If the register operand is flagged as early, mark the operand as such.
684      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
685        Operands[OpNo].setIsEarlyClobber(true);
686    }
687  }
688
689  // Re-add all the implicit ops.
690  if (RegInfo) {
691    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
692      assert(Operands[i].isReg() && "Should only be an implicit reg!");
693      RegInfo->addRegOperandToUseList(&Operands[i]);
694    }
695  }
696}
697
698/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
699/// fewer operand than it started with.
700///
701void MachineInstr::RemoveOperand(unsigned OpNo) {
702  assert(OpNo < Operands.size() && "Invalid operand number");
703  untieRegOperand(OpNo);
704  MachineRegisterInfo *RegInfo = getRegInfo();
705
706  // Special case removing the last one.
707  if (OpNo == Operands.size()-1) {
708    // If needed, remove from the reg def/use list.
709    if (RegInfo && Operands.back().isReg() && Operands.back().isOnRegUseList())
710      RegInfo->removeRegOperandFromUseList(&Operands.back());
711
712    Operands.pop_back();
713    return;
714  }
715
716  // Otherwise, we are removing an interior operand.  If we have reginfo to
717  // update, remove all operands that will be shifted down from their reg lists,
718  // move everything down, then re-add them.
719  if (RegInfo) {
720    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
721      if (Operands[i].isReg())
722        RegInfo->removeRegOperandFromUseList(&Operands[i]);
723    }
724  }
725
726#ifndef NDEBUG
727  // Moving tied operands would break the ties.
728  for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i)
729    if (Operands[i].isReg())
730      assert(!Operands[i].isTied() && "Cannot move tied operands");
731#endif
732
733  Operands.erase(Operands.begin()+OpNo);
734
735  if (RegInfo) {
736    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
737      if (Operands[i].isReg())
738        RegInfo->addRegOperandToUseList(&Operands[i]);
739    }
740  }
741}
742
743/// addMemOperand - Add a MachineMemOperand to the machine instruction.
744/// This function should be used only occasionally. The setMemRefs function
745/// is the primary method for setting up a MachineInstr's MemRefs list.
746void MachineInstr::addMemOperand(MachineFunction &MF,
747                                 MachineMemOperand *MO) {
748  mmo_iterator OldMemRefs = MemRefs;
749  uint16_t OldNumMemRefs = NumMemRefs;
750
751  uint16_t NewNum = NumMemRefs + 1;
752  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
753
754  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
755  NewMemRefs[NewNum - 1] = MO;
756
757  MemRefs = NewMemRefs;
758  NumMemRefs = NewNum;
759}
760
761bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
762  const MachineBasicBlock *MBB = getParent();
763  MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
764  while (MII != MBB->end() && MII->isInsideBundle()) {
765    if (MII->getDesc().getFlags() & Mask) {
766      if (Type == AnyInBundle)
767        return true;
768    } else {
769      if (Type == AllInBundle)
770        return false;
771    }
772    ++MII;
773  }
774
775  return Type == AllInBundle;
776}
777
778bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
779                                 MICheckType Check) const {
780  // If opcodes or number of operands are not the same then the two
781  // instructions are obviously not identical.
782  if (Other->getOpcode() != getOpcode() ||
783      Other->getNumOperands() != getNumOperands())
784    return false;
785
786  if (isBundle()) {
787    // Both instructions are bundles, compare MIs inside the bundle.
788    MachineBasicBlock::const_instr_iterator I1 = *this;
789    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
790    MachineBasicBlock::const_instr_iterator I2 = *Other;
791    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
792    while (++I1 != E1 && I1->isInsideBundle()) {
793      ++I2;
794      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
795        return false;
796    }
797  }
798
799  // Check operands to make sure they match.
800  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
801    const MachineOperand &MO = getOperand(i);
802    const MachineOperand &OMO = Other->getOperand(i);
803    if (!MO.isReg()) {
804      if (!MO.isIdenticalTo(OMO))
805        return false;
806      continue;
807    }
808
809    // Clients may or may not want to ignore defs when testing for equality.
810    // For example, machine CSE pass only cares about finding common
811    // subexpressions, so it's safe to ignore virtual register defs.
812    if (MO.isDef()) {
813      if (Check == IgnoreDefs)
814        continue;
815      else if (Check == IgnoreVRegDefs) {
816        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
817            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
818          if (MO.getReg() != OMO.getReg())
819            return false;
820      } else {
821        if (!MO.isIdenticalTo(OMO))
822          return false;
823        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
824          return false;
825      }
826    } else {
827      if (!MO.isIdenticalTo(OMO))
828        return false;
829      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
830        return false;
831    }
832  }
833  // If DebugLoc does not match then two dbg.values are not identical.
834  if (isDebugValue())
835    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
836        && getDebugLoc() != Other->getDebugLoc())
837      return false;
838  return true;
839}
840
841/// removeFromParent - This method unlinks 'this' from the containing basic
842/// block, and returns it, but does not delete it.
843MachineInstr *MachineInstr::removeFromParent() {
844  assert(getParent() && "Not embedded in a basic block!");
845
846  // If it's a bundle then remove the MIs inside the bundle as well.
847  if (isBundle()) {
848    MachineBasicBlock *MBB = getParent();
849    MachineBasicBlock::instr_iterator MII = *this; ++MII;
850    MachineBasicBlock::instr_iterator E = MBB->instr_end();
851    while (MII != E && MII->isInsideBundle()) {
852      MachineInstr *MI = &*MII;
853      ++MII;
854      MBB->remove(MI);
855    }
856  }
857  getParent()->remove(this);
858  return this;
859}
860
861
862/// eraseFromParent - This method unlinks 'this' from the containing basic
863/// block, and deletes it.
864void MachineInstr::eraseFromParent() {
865  assert(getParent() && "Not embedded in a basic block!");
866  // If it's a bundle then remove the MIs inside the bundle as well.
867  if (isBundle()) {
868    MachineBasicBlock *MBB = getParent();
869    MachineBasicBlock::instr_iterator MII = *this; ++MII;
870    MachineBasicBlock::instr_iterator E = MBB->instr_end();
871    while (MII != E && MII->isInsideBundle()) {
872      MachineInstr *MI = &*MII;
873      ++MII;
874      MBB->erase(MI);
875    }
876  }
877  // Erase the individual instruction, which may itself be inside a bundle.
878  getParent()->erase_instr(this);
879}
880
881
882/// getNumExplicitOperands - Returns the number of non-implicit operands.
883///
884unsigned MachineInstr::getNumExplicitOperands() const {
885  unsigned NumOperands = MCID->getNumOperands();
886  if (!MCID->isVariadic())
887    return NumOperands;
888
889  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
890    const MachineOperand &MO = getOperand(i);
891    if (!MO.isReg() || !MO.isImplicit())
892      NumOperands++;
893  }
894  return NumOperands;
895}
896
897/// isBundled - Return true if this instruction part of a bundle. This is true
898/// if either itself or its following instruction is marked "InsideBundle".
899bool MachineInstr::isBundled() const {
900  if (isInsideBundle())
901    return true;
902  MachineBasicBlock::const_instr_iterator nextMI = this;
903  ++nextMI;
904  return nextMI != Parent->instr_end() && nextMI->isInsideBundle();
905}
906
907bool MachineInstr::isStackAligningInlineAsm() const {
908  if (isInlineAsm()) {
909    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
910    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
911      return true;
912  }
913  return false;
914}
915
916InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
917  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
918  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
919  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
920}
921
922int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
923                                       unsigned *GroupNo) const {
924  assert(isInlineAsm() && "Expected an inline asm instruction");
925  assert(OpIdx < getNumOperands() && "OpIdx out of range");
926
927  // Ignore queries about the initial operands.
928  if (OpIdx < InlineAsm::MIOp_FirstOperand)
929    return -1;
930
931  unsigned Group = 0;
932  unsigned NumOps;
933  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
934       i += NumOps) {
935    const MachineOperand &FlagMO = getOperand(i);
936    // If we reach the implicit register operands, stop looking.
937    if (!FlagMO.isImm())
938      return -1;
939    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
940    if (i + NumOps > OpIdx) {
941      if (GroupNo)
942        *GroupNo = Group;
943      return i;
944    }
945    ++Group;
946  }
947  return -1;
948}
949
950const TargetRegisterClass*
951MachineInstr::getRegClassConstraint(unsigned OpIdx,
952                                    const TargetInstrInfo *TII,
953                                    const TargetRegisterInfo *TRI) const {
954  assert(getParent() && "Can't have an MBB reference here!");
955  assert(getParent()->getParent() && "Can't have an MF reference here!");
956  const MachineFunction &MF = *getParent()->getParent();
957
958  // Most opcodes have fixed constraints in their MCInstrDesc.
959  if (!isInlineAsm())
960    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
961
962  if (!getOperand(OpIdx).isReg())
963    return NULL;
964
965  // For tied uses on inline asm, get the constraint from the def.
966  unsigned DefIdx;
967  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
968    OpIdx = DefIdx;
969
970  // Inline asm stores register class constraints in the flag word.
971  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
972  if (FlagIdx < 0)
973    return NULL;
974
975  unsigned Flag = getOperand(FlagIdx).getImm();
976  unsigned RCID;
977  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
978    return TRI->getRegClass(RCID);
979
980  // Assume that all registers in a memory operand are pointers.
981  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
982    return TRI->getPointerRegClass(MF);
983
984  return NULL;
985}
986
987/// getBundleSize - Return the number of instructions inside the MI bundle.
988unsigned MachineInstr::getBundleSize() const {
989  assert(isBundle() && "Expecting a bundle");
990
991  const MachineBasicBlock *MBB = getParent();
992  MachineBasicBlock::const_instr_iterator I = *this, E = MBB->instr_end();
993  unsigned Size = 0;
994  while ((++I != E) && I->isInsideBundle()) {
995    ++Size;
996  }
997  assert(Size > 1 && "Malformed bundle");
998
999  return Size;
1000}
1001
1002/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1003/// the specific register or -1 if it is not found. It further tightens
1004/// the search criteria to a use that kills the register if isKill is true.
1005int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1006                                          const TargetRegisterInfo *TRI) const {
1007  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1008    const MachineOperand &MO = getOperand(i);
1009    if (!MO.isReg() || !MO.isUse())
1010      continue;
1011    unsigned MOReg = MO.getReg();
1012    if (!MOReg)
1013      continue;
1014    if (MOReg == Reg ||
1015        (TRI &&
1016         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1017         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1018         TRI->isSubRegister(MOReg, Reg)))
1019      if (!isKill || MO.isKill())
1020        return i;
1021  }
1022  return -1;
1023}
1024
1025/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1026/// indicating if this instruction reads or writes Reg. This also considers
1027/// partial defines.
1028std::pair<bool,bool>
1029MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1030                                         SmallVectorImpl<unsigned> *Ops) const {
1031  bool PartDef = false; // Partial redefine.
1032  bool FullDef = false; // Full define.
1033  bool Use = false;
1034
1035  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1036    const MachineOperand &MO = getOperand(i);
1037    if (!MO.isReg() || MO.getReg() != Reg)
1038      continue;
1039    if (Ops)
1040      Ops->push_back(i);
1041    if (MO.isUse())
1042      Use |= !MO.isUndef();
1043    else if (MO.getSubReg() && !MO.isUndef())
1044      // A partial <def,undef> doesn't count as reading the register.
1045      PartDef = true;
1046    else
1047      FullDef = true;
1048  }
1049  // A partial redefine uses Reg unless there is also a full define.
1050  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1051}
1052
1053/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1054/// the specified register or -1 if it is not found. If isDead is true, defs
1055/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1056/// also checks if there is a def of a super-register.
1057int
1058MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1059                                        const TargetRegisterInfo *TRI) const {
1060  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1061  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1062    const MachineOperand &MO = getOperand(i);
1063    // Accept regmask operands when Overlap is set.
1064    // Ignore them when looking for a specific def operand (Overlap == false).
1065    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1066      return i;
1067    if (!MO.isReg() || !MO.isDef())
1068      continue;
1069    unsigned MOReg = MO.getReg();
1070    bool Found = (MOReg == Reg);
1071    if (!Found && TRI && isPhys &&
1072        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1073      if (Overlap)
1074        Found = TRI->regsOverlap(MOReg, Reg);
1075      else
1076        Found = TRI->isSubRegister(MOReg, Reg);
1077    }
1078    if (Found && (!isDead || MO.isDead()))
1079      return i;
1080  }
1081  return -1;
1082}
1083
1084/// findFirstPredOperandIdx() - Find the index of the first operand in the
1085/// operand list that is used to represent the predicate. It returns -1 if
1086/// none is found.
1087int MachineInstr::findFirstPredOperandIdx() const {
1088  // Don't call MCID.findFirstPredOperandIdx() because this variant
1089  // is sometimes called on an instruction that's not yet complete, and
1090  // so the number of operands is less than the MCID indicates. In
1091  // particular, the PTX target does this.
1092  const MCInstrDesc &MCID = getDesc();
1093  if (MCID.isPredicable()) {
1094    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1095      if (MCID.OpInfo[i].isPredicate())
1096        return i;
1097  }
1098
1099  return -1;
1100}
1101
1102// MachineOperand::TiedTo is 4 bits wide.
1103const unsigned TiedMax = 15;
1104
1105/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1106///
1107/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1108/// field. TiedTo can have these values:
1109///
1110/// 0:              Operand is not tied to anything.
1111/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1112/// TiedMax:        Tied to an operand >= TiedMax-1.
1113///
1114/// The tied def must be one of the first TiedMax operands on a normal
1115/// instruction. INLINEASM instructions allow more tied defs.
1116///
1117void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1118  MachineOperand &DefMO = getOperand(DefIdx);
1119  MachineOperand &UseMO = getOperand(UseIdx);
1120  assert(DefMO.isDef() && "DefIdx must be a def operand");
1121  assert(UseMO.isUse() && "UseIdx must be a use operand");
1122  assert(!DefMO.isTied() && "Def is already tied to another use");
1123  assert(!UseMO.isTied() && "Use is already tied to another def");
1124
1125  if (DefIdx < TiedMax)
1126    UseMO.TiedTo = DefIdx + 1;
1127  else {
1128    // Inline asm can use the group descriptors to find tied operands, but on
1129    // normal instruction, the tied def must be within the first TiedMax
1130    // operands.
1131    assert(isInlineAsm() && "DefIdx out of range");
1132    UseMO.TiedTo = TiedMax;
1133  }
1134
1135  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1136  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1137}
1138
1139/// Given the index of a tied register operand, find the operand it is tied to.
1140/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1141/// which must exist.
1142unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1143  const MachineOperand &MO = getOperand(OpIdx);
1144  assert(MO.isTied() && "Operand isn't tied");
1145
1146  // Normally TiedTo is in range.
1147  if (MO.TiedTo < TiedMax)
1148    return MO.TiedTo - 1;
1149
1150  // Uses on normal instructions can be out of range.
1151  if (!isInlineAsm()) {
1152    // Normal tied defs must be in the 0..TiedMax-1 range.
1153    if (MO.isUse())
1154      return TiedMax - 1;
1155    // MO is a def. Search for the tied use.
1156    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1157      const MachineOperand &UseMO = getOperand(i);
1158      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1159        return i;
1160    }
1161    llvm_unreachable("Can't find tied use");
1162  }
1163
1164  // Now deal with inline asm by parsing the operand group descriptor flags.
1165  // Find the beginning of each operand group.
1166  SmallVector<unsigned, 8> GroupIdx;
1167  unsigned OpIdxGroup = ~0u;
1168  unsigned NumOps;
1169  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1170       i += NumOps) {
1171    const MachineOperand &FlagMO = getOperand(i);
1172    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1173    unsigned CurGroup = GroupIdx.size();
1174    GroupIdx.push_back(i);
1175    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1176    // OpIdx belongs to this operand group.
1177    if (OpIdx > i && OpIdx < i + NumOps)
1178      OpIdxGroup = CurGroup;
1179    unsigned TiedGroup;
1180    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1181      continue;
1182    // Operands in this group are tied to operands in TiedGroup which must be
1183    // earlier. Find the number of operands between the two groups.
1184    unsigned Delta = i - GroupIdx[TiedGroup];
1185
1186    // OpIdx is a use tied to TiedGroup.
1187    if (OpIdxGroup == CurGroup)
1188      return OpIdx - Delta;
1189
1190    // OpIdx is a def tied to this use group.
1191    if (OpIdxGroup == TiedGroup)
1192      return OpIdx + Delta;
1193  }
1194  llvm_unreachable("Invalid tied operand on inline asm");
1195}
1196
1197/// clearKillInfo - Clears kill flags on all operands.
1198///
1199void MachineInstr::clearKillInfo() {
1200  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1201    MachineOperand &MO = getOperand(i);
1202    if (MO.isReg() && MO.isUse())
1203      MO.setIsKill(false);
1204  }
1205}
1206
1207/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1208///
1209void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1210  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1211    const MachineOperand &MO = MI->getOperand(i);
1212    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1213      continue;
1214    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1215      MachineOperand &MOp = getOperand(j);
1216      if (!MOp.isIdenticalTo(MO))
1217        continue;
1218      if (MO.isKill())
1219        MOp.setIsKill();
1220      else
1221        MOp.setIsDead();
1222      break;
1223    }
1224  }
1225}
1226
1227/// copyPredicates - Copies predicate operand(s) from MI.
1228void MachineInstr::copyPredicates(const MachineInstr *MI) {
1229  assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
1230
1231  const MCInstrDesc &MCID = MI->getDesc();
1232  if (!MCID.isPredicable())
1233    return;
1234  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1235    if (MCID.OpInfo[i].isPredicate()) {
1236      // Predicated operands must be last operands.
1237      addOperand(MI->getOperand(i));
1238    }
1239  }
1240}
1241
1242void MachineInstr::substituteRegister(unsigned FromReg,
1243                                      unsigned ToReg,
1244                                      unsigned SubIdx,
1245                                      const TargetRegisterInfo &RegInfo) {
1246  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1247    if (SubIdx)
1248      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1249    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1250      MachineOperand &MO = getOperand(i);
1251      if (!MO.isReg() || MO.getReg() != FromReg)
1252        continue;
1253      MO.substPhysReg(ToReg, RegInfo);
1254    }
1255  } else {
1256    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1257      MachineOperand &MO = getOperand(i);
1258      if (!MO.isReg() || MO.getReg() != FromReg)
1259        continue;
1260      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1261    }
1262  }
1263}
1264
1265/// isSafeToMove - Return true if it is safe to move this instruction. If
1266/// SawStore is set to true, it means that there is a store (or call) between
1267/// the instruction's location and its intended destination.
1268bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1269                                AliasAnalysis *AA,
1270                                bool &SawStore) const {
1271  // Ignore stuff that we obviously can't move.
1272  //
1273  // Treat volatile loads as stores. This is not strictly necessary for
1274  // volatiles, but it is required for atomic loads. It is not allowed to move
1275  // a load across an atomic load with Ordering > Monotonic.
1276  if (mayStore() || isCall() ||
1277      (mayLoad() && hasOrderedMemoryRef())) {
1278    SawStore = true;
1279    return false;
1280  }
1281
1282  if (isLabel() || isDebugValue() ||
1283      isTerminator() || hasUnmodeledSideEffects())
1284    return false;
1285
1286  // See if this instruction does a load.  If so, we have to guarantee that the
1287  // loaded value doesn't change between the load and the its intended
1288  // destination. The check for isInvariantLoad gives the targe the chance to
1289  // classify the load as always returning a constant, e.g. a constant pool
1290  // load.
1291  if (mayLoad() && !isInvariantLoad(AA))
1292    // Otherwise, this is a real load.  If there is a store between the load and
1293    // end of block, we can't move it.
1294    return !SawStore;
1295
1296  return true;
1297}
1298
1299/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1300/// instruction which defined the specified register instead of copying it.
1301bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1302                                 AliasAnalysis *AA,
1303                                 unsigned DstReg) const {
1304  bool SawStore = false;
1305  if (!TII->isTriviallyReMaterializable(this, AA) ||
1306      !isSafeToMove(TII, AA, SawStore))
1307    return false;
1308  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1309    const MachineOperand &MO = getOperand(i);
1310    if (!MO.isReg())
1311      continue;
1312    // FIXME: For now, do not remat any instruction with register operands.
1313    // Later on, we can loosen the restriction is the register operands have
1314    // not been modified between the def and use. Note, this is different from
1315    // MachineSink because the code is no longer in two-address form (at least
1316    // partially).
1317    if (MO.isUse())
1318      return false;
1319    else if (!MO.isDead() && MO.getReg() != DstReg)
1320      return false;
1321  }
1322  return true;
1323}
1324
1325/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1326/// or volatile memory reference, or if the information describing the memory
1327/// reference is not available. Return false if it is known to have no ordered
1328/// memory references.
1329bool MachineInstr::hasOrderedMemoryRef() const {
1330  // An instruction known never to access memory won't have a volatile access.
1331  if (!mayStore() &&
1332      !mayLoad() &&
1333      !isCall() &&
1334      !hasUnmodeledSideEffects())
1335    return false;
1336
1337  // Otherwise, if the instruction has no memory reference information,
1338  // conservatively assume it wasn't preserved.
1339  if (memoperands_empty())
1340    return true;
1341
1342  // Check the memory reference information for ordered references.
1343  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1344    if (!(*I)->isUnordered())
1345      return true;
1346
1347  return false;
1348}
1349
1350/// isInvariantLoad - Return true if this instruction is loading from a
1351/// location whose value is invariant across the function.  For example,
1352/// loading a value from the constant pool or from the argument area
1353/// of a function if it does not change.  This should only return true of
1354/// *all* loads the instruction does are invariant (if it does multiple loads).
1355bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1356  // If the instruction doesn't load at all, it isn't an invariant load.
1357  if (!mayLoad())
1358    return false;
1359
1360  // If the instruction has lost its memoperands, conservatively assume that
1361  // it may not be an invariant load.
1362  if (memoperands_empty())
1363    return false;
1364
1365  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1366
1367  for (mmo_iterator I = memoperands_begin(),
1368       E = memoperands_end(); I != E; ++I) {
1369    if ((*I)->isVolatile()) return false;
1370    if ((*I)->isStore()) return false;
1371    if ((*I)->isInvariant()) return true;
1372
1373    if (const Value *V = (*I)->getValue()) {
1374      // A load from a constant PseudoSourceValue is invariant.
1375      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1376        if (PSV->isConstant(MFI))
1377          continue;
1378      // If we have an AliasAnalysis, ask it whether the memory is constant.
1379      if (AA && AA->pointsToConstantMemory(
1380                      AliasAnalysis::Location(V, (*I)->getSize(),
1381                                              (*I)->getTBAAInfo())))
1382        continue;
1383    }
1384
1385    // Otherwise assume conservatively.
1386    return false;
1387  }
1388
1389  // Everything checks out.
1390  return true;
1391}
1392
1393/// isConstantValuePHI - If the specified instruction is a PHI that always
1394/// merges together the same virtual register, return the register, otherwise
1395/// return 0.
1396unsigned MachineInstr::isConstantValuePHI() const {
1397  if (!isPHI())
1398    return 0;
1399  assert(getNumOperands() >= 3 &&
1400         "It's illegal to have a PHI without source operands");
1401
1402  unsigned Reg = getOperand(1).getReg();
1403  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1404    if (getOperand(i).getReg() != Reg)
1405      return 0;
1406  return Reg;
1407}
1408
1409bool MachineInstr::hasUnmodeledSideEffects() const {
1410  if (hasProperty(MCID::UnmodeledSideEffects))
1411    return true;
1412  if (isInlineAsm()) {
1413    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1414    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1415      return true;
1416  }
1417
1418  return false;
1419}
1420
1421/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1422///
1423bool MachineInstr::allDefsAreDead() const {
1424  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1425    const MachineOperand &MO = getOperand(i);
1426    if (!MO.isReg() || MO.isUse())
1427      continue;
1428    if (!MO.isDead())
1429      return false;
1430  }
1431  return true;
1432}
1433
1434/// copyImplicitOps - Copy implicit register operands from specified
1435/// instruction to this instruction.
1436void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1437  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1438       i != e; ++i) {
1439    const MachineOperand &MO = MI->getOperand(i);
1440    if (MO.isReg() && MO.isImplicit())
1441      addOperand(MO);
1442  }
1443}
1444
1445void MachineInstr::dump() const {
1446#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1447  dbgs() << "  " << *this;
1448#endif
1449}
1450
1451static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1452                         raw_ostream &CommentOS) {
1453  const LLVMContext &Ctx = MF->getFunction()->getContext();
1454  if (!DL.isUnknown()) {          // Print source line info.
1455    DIScope Scope(DL.getScope(Ctx));
1456    // Omit the directory, because it's likely to be long and uninteresting.
1457    if (Scope.Verify())
1458      CommentOS << Scope.getFilename();
1459    else
1460      CommentOS << "<unknown>";
1461    CommentOS << ':' << DL.getLine();
1462    if (DL.getCol() != 0)
1463      CommentOS << ':' << DL.getCol();
1464    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1465    if (!InlinedAtDL.isUnknown()) {
1466      CommentOS << " @[ ";
1467      printDebugLoc(InlinedAtDL, MF, CommentOS);
1468      CommentOS << " ]";
1469    }
1470  }
1471}
1472
1473void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1474  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1475  const MachineFunction *MF = 0;
1476  const MachineRegisterInfo *MRI = 0;
1477  if (const MachineBasicBlock *MBB = getParent()) {
1478    MF = MBB->getParent();
1479    if (!TM && MF)
1480      TM = &MF->getTarget();
1481    if (MF)
1482      MRI = &MF->getRegInfo();
1483  }
1484
1485  // Save a list of virtual registers.
1486  SmallVector<unsigned, 8> VirtRegs;
1487
1488  // Print explicitly defined operands on the left of an assignment syntax.
1489  unsigned StartOp = 0, e = getNumOperands();
1490  for (; StartOp < e && getOperand(StartOp).isReg() &&
1491         getOperand(StartOp).isDef() &&
1492         !getOperand(StartOp).isImplicit();
1493       ++StartOp) {
1494    if (StartOp != 0) OS << ", ";
1495    getOperand(StartOp).print(OS, TM);
1496    unsigned Reg = getOperand(StartOp).getReg();
1497    if (TargetRegisterInfo::isVirtualRegister(Reg))
1498      VirtRegs.push_back(Reg);
1499  }
1500
1501  if (StartOp != 0)
1502    OS << " = ";
1503
1504  // Print the opcode name.
1505  if (TM && TM->getInstrInfo())
1506    OS << TM->getInstrInfo()->getName(getOpcode());
1507  else
1508    OS << "UNKNOWN";
1509
1510  // Print the rest of the operands.
1511  bool OmittedAnyCallClobbers = false;
1512  bool FirstOp = true;
1513  unsigned AsmDescOp = ~0u;
1514  unsigned AsmOpCount = 0;
1515
1516  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1517    // Print asm string.
1518    OS << " ";
1519    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1520
1521    // Print HasSideEffects, IsAlignStack
1522    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1523    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1524      OS << " [sideeffect]";
1525    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1526      OS << " [alignstack]";
1527    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1528      OS << " [attdialect]";
1529    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1530      OS << " [inteldialect]";
1531
1532    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1533    FirstOp = false;
1534  }
1535
1536
1537  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1538    const MachineOperand &MO = getOperand(i);
1539
1540    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1541      VirtRegs.push_back(MO.getReg());
1542
1543    // Omit call-clobbered registers which aren't used anywhere. This makes
1544    // call instructions much less noisy on targets where calls clobber lots
1545    // of registers. Don't rely on MO.isDead() because we may be called before
1546    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1547    if (MF && isCall() &&
1548        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1549      unsigned Reg = MO.getReg();
1550      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1551        const MachineRegisterInfo &MRI = MF->getRegInfo();
1552        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1553          bool HasAliasLive = false;
1554          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1555               AI.isValid(); ++AI) {
1556            unsigned AliasReg = *AI;
1557            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1558              HasAliasLive = true;
1559              break;
1560            }
1561          }
1562          if (!HasAliasLive) {
1563            OmittedAnyCallClobbers = true;
1564            continue;
1565          }
1566        }
1567      }
1568    }
1569
1570    if (FirstOp) FirstOp = false; else OS << ",";
1571    OS << " ";
1572    if (i < getDesc().NumOperands) {
1573      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1574      if (MCOI.isPredicate())
1575        OS << "pred:";
1576      if (MCOI.isOptionalDef())
1577        OS << "opt:";
1578    }
1579    if (isDebugValue() && MO.isMetadata()) {
1580      // Pretty print DBG_VALUE instructions.
1581      const MDNode *MD = MO.getMetadata();
1582      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1583        OS << "!\"" << MDS->getString() << '\"';
1584      else
1585        MO.print(OS, TM);
1586    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1587      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1588    } else if (i == AsmDescOp && MO.isImm()) {
1589      // Pretty print the inline asm operand descriptor.
1590      OS << '$' << AsmOpCount++;
1591      unsigned Flag = MO.getImm();
1592      switch (InlineAsm::getKind(Flag)) {
1593      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1594      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1595      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1596      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1597      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1598      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1599      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1600      }
1601
1602      unsigned RCID = 0;
1603      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1604        if (TM)
1605          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1606        else
1607          OS << ":RC" << RCID;
1608      }
1609
1610      unsigned TiedTo = 0;
1611      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1612        OS << " tiedto:$" << TiedTo;
1613
1614      OS << ']';
1615
1616      // Compute the index of the next operand descriptor.
1617      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1618    } else
1619      MO.print(OS, TM);
1620  }
1621
1622  // Briefly indicate whether any call clobbers were omitted.
1623  if (OmittedAnyCallClobbers) {
1624    if (!FirstOp) OS << ",";
1625    OS << " ...";
1626  }
1627
1628  bool HaveSemi = false;
1629  if (Flags) {
1630    if (!HaveSemi) OS << ";"; HaveSemi = true;
1631    OS << " flags: ";
1632
1633    if (Flags & FrameSetup)
1634      OS << "FrameSetup";
1635  }
1636
1637  if (!memoperands_empty()) {
1638    if (!HaveSemi) OS << ";"; HaveSemi = true;
1639
1640    OS << " mem:";
1641    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1642         i != e; ++i) {
1643      OS << **i;
1644      if (llvm::next(i) != e)
1645        OS << " ";
1646    }
1647  }
1648
1649  // Print the regclass of any virtual registers encountered.
1650  if (MRI && !VirtRegs.empty()) {
1651    if (!HaveSemi) OS << ";"; HaveSemi = true;
1652    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1653      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1654      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1655      for (unsigned j = i+1; j != VirtRegs.size();) {
1656        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1657          ++j;
1658          continue;
1659        }
1660        if (VirtRegs[i] != VirtRegs[j])
1661          OS << "," << PrintReg(VirtRegs[j]);
1662        VirtRegs.erase(VirtRegs.begin()+j);
1663      }
1664    }
1665  }
1666
1667  // Print debug location information.
1668  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1669    if (!HaveSemi) OS << ";"; HaveSemi = true;
1670    DIVariable DV(getOperand(e - 1).getMetadata());
1671    OS << " line no:" <<  DV.getLineNumber();
1672    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1673      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1674      if (!InlinedAtDL.isUnknown()) {
1675        OS << " inlined @[ ";
1676        printDebugLoc(InlinedAtDL, MF, OS);
1677        OS << " ]";
1678      }
1679    }
1680  } else if (!debugLoc.isUnknown() && MF) {
1681    if (!HaveSemi) OS << ";"; HaveSemi = true;
1682    OS << " dbg:";
1683    printDebugLoc(debugLoc, MF, OS);
1684  }
1685
1686  OS << '\n';
1687}
1688
1689bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1690                                     const TargetRegisterInfo *RegInfo,
1691                                     bool AddIfNotFound) {
1692  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1693  bool hasAliases = isPhysReg &&
1694    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1695  bool Found = false;
1696  SmallVector<unsigned,4> DeadOps;
1697  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1698    MachineOperand &MO = getOperand(i);
1699    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1700      continue;
1701    unsigned Reg = MO.getReg();
1702    if (!Reg)
1703      continue;
1704
1705    if (Reg == IncomingReg) {
1706      if (!Found) {
1707        if (MO.isKill())
1708          // The register is already marked kill.
1709          return true;
1710        if (isPhysReg && isRegTiedToDefOperand(i))
1711          // Two-address uses of physregs must not be marked kill.
1712          return true;
1713        MO.setIsKill();
1714        Found = true;
1715      }
1716    } else if (hasAliases && MO.isKill() &&
1717               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1718      // A super-register kill already exists.
1719      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1720        return true;
1721      if (RegInfo->isSubRegister(IncomingReg, Reg))
1722        DeadOps.push_back(i);
1723    }
1724  }
1725
1726  // Trim unneeded kill operands.
1727  while (!DeadOps.empty()) {
1728    unsigned OpIdx = DeadOps.back();
1729    if (getOperand(OpIdx).isImplicit())
1730      RemoveOperand(OpIdx);
1731    else
1732      getOperand(OpIdx).setIsKill(false);
1733    DeadOps.pop_back();
1734  }
1735
1736  // If not found, this means an alias of one of the operands is killed. Add a
1737  // new implicit operand if required.
1738  if (!Found && AddIfNotFound) {
1739    addOperand(MachineOperand::CreateReg(IncomingReg,
1740                                         false /*IsDef*/,
1741                                         true  /*IsImp*/,
1742                                         true  /*IsKill*/));
1743    return true;
1744  }
1745  return Found;
1746}
1747
1748void MachineInstr::clearRegisterKills(unsigned Reg,
1749                                      const TargetRegisterInfo *RegInfo) {
1750  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1751    RegInfo = 0;
1752  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1753    MachineOperand &MO = getOperand(i);
1754    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1755      continue;
1756    unsigned OpReg = MO.getReg();
1757    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1758      MO.setIsKill(false);
1759  }
1760}
1761
1762bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1763                                   const TargetRegisterInfo *RegInfo,
1764                                   bool AddIfNotFound) {
1765  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1766  bool hasAliases = isPhysReg &&
1767    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1768  bool Found = false;
1769  SmallVector<unsigned,4> DeadOps;
1770  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1771    MachineOperand &MO = getOperand(i);
1772    if (!MO.isReg() || !MO.isDef())
1773      continue;
1774    unsigned Reg = MO.getReg();
1775    if (!Reg)
1776      continue;
1777
1778    if (Reg == IncomingReg) {
1779      MO.setIsDead();
1780      Found = true;
1781    } else if (hasAliases && MO.isDead() &&
1782               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1783      // There exists a super-register that's marked dead.
1784      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1785        return true;
1786      if (RegInfo->isSubRegister(IncomingReg, Reg))
1787        DeadOps.push_back(i);
1788    }
1789  }
1790
1791  // Trim unneeded dead operands.
1792  while (!DeadOps.empty()) {
1793    unsigned OpIdx = DeadOps.back();
1794    if (getOperand(OpIdx).isImplicit())
1795      RemoveOperand(OpIdx);
1796    else
1797      getOperand(OpIdx).setIsDead(false);
1798    DeadOps.pop_back();
1799  }
1800
1801  // If not found, this means an alias of one of the operands is dead. Add a
1802  // new implicit operand if required.
1803  if (Found || !AddIfNotFound)
1804    return Found;
1805
1806  addOperand(MachineOperand::CreateReg(IncomingReg,
1807                                       true  /*IsDef*/,
1808                                       true  /*IsImp*/,
1809                                       false /*IsKill*/,
1810                                       true  /*IsDead*/));
1811  return true;
1812}
1813
1814void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1815                                      const TargetRegisterInfo *RegInfo) {
1816  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1817    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1818    if (MO)
1819      return;
1820  } else {
1821    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1822      const MachineOperand &MO = getOperand(i);
1823      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1824          MO.getSubReg() == 0)
1825        return;
1826    }
1827  }
1828  addOperand(MachineOperand::CreateReg(IncomingReg,
1829                                       true  /*IsDef*/,
1830                                       true  /*IsImp*/));
1831}
1832
1833void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1834                                         const TargetRegisterInfo &TRI) {
1835  bool HasRegMask = false;
1836  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1837    MachineOperand &MO = getOperand(i);
1838    if (MO.isRegMask()) {
1839      HasRegMask = true;
1840      continue;
1841    }
1842    if (!MO.isReg() || !MO.isDef()) continue;
1843    unsigned Reg = MO.getReg();
1844    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1845    bool Dead = true;
1846    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1847         I != E; ++I)
1848      if (TRI.regsOverlap(*I, Reg)) {
1849        Dead = false;
1850        break;
1851      }
1852    // If there are no uses, including partial uses, the def is dead.
1853    if (Dead) MO.setIsDead();
1854  }
1855
1856  // This is a call with a register mask operand.
1857  // Mask clobbers are always dead, so add defs for the non-dead defines.
1858  if (HasRegMask)
1859    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1860         I != E; ++I)
1861      addRegisterDefined(*I, &TRI);
1862}
1863
1864unsigned
1865MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1866  // Build up a buffer of hash code components.
1867  SmallVector<size_t, 8> HashComponents;
1868  HashComponents.reserve(MI->getNumOperands() + 1);
1869  HashComponents.push_back(MI->getOpcode());
1870  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1871    const MachineOperand &MO = MI->getOperand(i);
1872    if (MO.isReg() && MO.isDef() &&
1873        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1874      continue;  // Skip virtual register defs.
1875
1876    HashComponents.push_back(hash_value(MO));
1877  }
1878  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1879}
1880
1881void MachineInstr::emitError(StringRef Msg) const {
1882  // Find the source location cookie.
1883  unsigned LocCookie = 0;
1884  const MDNode *LocMD = 0;
1885  for (unsigned i = getNumOperands(); i != 0; --i) {
1886    if (getOperand(i-1).isMetadata() &&
1887        (LocMD = getOperand(i-1).getMetadata()) &&
1888        LocMD->getNumOperands() != 0) {
1889      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1890        LocCookie = CI->getZExtValue();
1891        break;
1892      }
1893    }
1894  }
1895
1896  if (const MachineBasicBlock *MBB = getParent())
1897    if (const MachineFunction *MF = MBB->getParent())
1898      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1899  report_fatal_error(Msg);
1900}
1901