MachineInstr.cpp revision b7596d2b13212e23f89e47a8fd508a6fffd186c1 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetInstrDesc.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Support/LeakDetector.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/Streams.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/ADT/FoldingSet.h"
29#include <ostream>
30using namespace llvm;
31
32//===----------------------------------------------------------------------===//
33// MachineOperand Implementation
34//===----------------------------------------------------------------------===//
35
36/// AddRegOperandToRegInfo - Add this register operand to the specified
37/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
38/// explicitly nulled out.
39void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
40  assert(isReg() && "Can only add reg operand to use lists");
41
42  // If the reginfo pointer is null, just explicitly null out or next/prev
43  // pointers, to ensure they are not garbage.
44  if (RegInfo == 0) {
45    Contents.Reg.Prev = 0;
46    Contents.Reg.Next = 0;
47    return;
48  }
49
50  // Otherwise, add this operand to the head of the registers use/def list.
51  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
52
53  // For SSA values, we prefer to keep the definition at the start of the list.
54  // we do this by skipping over the definition if it is at the head of the
55  // list.
56  if (*Head && (*Head)->isDef())
57    Head = &(*Head)->Contents.Reg.Next;
58
59  Contents.Reg.Next = *Head;
60  if (Contents.Reg.Next) {
61    assert(getReg() == Contents.Reg.Next->getReg() &&
62           "Different regs on the same list!");
63    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
64  }
65
66  Contents.Reg.Prev = Head;
67  *Head = this;
68}
69
70void MachineOperand::setReg(unsigned Reg) {
71  if (getReg() == Reg) return; // No change.
72
73  // Otherwise, we have to change the register.  If this operand is embedded
74  // into a machine function, we need to update the old and new register's
75  // use/def lists.
76  if (MachineInstr *MI = getParent())
77    if (MachineBasicBlock *MBB = MI->getParent())
78      if (MachineFunction *MF = MBB->getParent()) {
79        RemoveRegOperandFromRegInfo();
80        Contents.Reg.RegNo = Reg;
81        AddRegOperandToRegInfo(&MF->getRegInfo());
82        return;
83      }
84
85  // Otherwise, just change the register, no problem.  :)
86  Contents.Reg.RegNo = Reg;
87}
88
89/// ChangeToImmediate - Replace this operand with a new immediate operand of
90/// the specified value.  If an operand is known to be an immediate already,
91/// the setImm method should be used.
92void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
93  // If this operand is currently a register operand, and if this is in a
94  // function, deregister the operand from the register's use/def list.
95  if (isReg() && getParent() && getParent()->getParent() &&
96      getParent()->getParent()->getParent())
97    RemoveRegOperandFromRegInfo();
98
99  OpKind = MO_Immediate;
100  Contents.ImmVal = ImmVal;
101}
102
103/// ChangeToRegister - Replace this operand with a new register operand of
104/// the specified value.  If an operand is known to be an register already,
105/// the setReg method should be used.
106void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
107                                      bool isKill, bool isDead) {
108  // If this operand is already a register operand, use setReg to update the
109  // register's use/def lists.
110  if (isReg()) {
111    assert(!isEarlyClobber());
112    setReg(Reg);
113  } else {
114    // Otherwise, change this to a register and set the reg#.
115    OpKind = MO_Register;
116    Contents.Reg.RegNo = Reg;
117
118    // If this operand is embedded in a function, add the operand to the
119    // register's use/def list.
120    if (MachineInstr *MI = getParent())
121      if (MachineBasicBlock *MBB = MI->getParent())
122        if (MachineFunction *MF = MBB->getParent())
123          AddRegOperandToRegInfo(&MF->getRegInfo());
124  }
125
126  IsDef = isDef;
127  IsImp = isImp;
128  IsKill = isKill;
129  IsDead = isDead;
130  IsEarlyClobber = false;
131  SubReg = 0;
132}
133
134/// isIdenticalTo - Return true if this operand is identical to the specified
135/// operand.
136bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
137  if (getType() != Other.getType()) return false;
138
139  switch (getType()) {
140  default: assert(0 && "Unrecognized operand type");
141  case MachineOperand::MO_Register:
142    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
143           getSubReg() == Other.getSubReg();
144  case MachineOperand::MO_Immediate:
145    return getImm() == Other.getImm();
146  case MachineOperand::MO_FPImmediate:
147    return getFPImm() == Other.getFPImm();
148  case MachineOperand::MO_MachineBasicBlock:
149    return getMBB() == Other.getMBB();
150  case MachineOperand::MO_FrameIndex:
151    return getIndex() == Other.getIndex();
152  case MachineOperand::MO_ConstantPoolIndex:
153    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
154  case MachineOperand::MO_JumpTableIndex:
155    return getIndex() == Other.getIndex();
156  case MachineOperand::MO_GlobalAddress:
157    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
158  case MachineOperand::MO_ExternalSymbol:
159    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
160           getOffset() == Other.getOffset();
161  }
162}
163
164/// print - Print the specified machine operand.
165///
166void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
167  raw_os_ostream RawOS(OS);
168  print(RawOS, TM);
169}
170
171void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
172  switch (getType()) {
173  case MachineOperand::MO_Register:
174    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
175      OS << "%reg" << getReg();
176    } else {
177      // If the instruction is embedded into a basic block, we can find the
178      // target info for the instruction.
179      if (TM == 0)
180        if (const MachineInstr *MI = getParent())
181          if (const MachineBasicBlock *MBB = MI->getParent())
182            if (const MachineFunction *MF = MBB->getParent())
183              TM = &MF->getTarget();
184
185      if (TM)
186        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
187      else
188        OS << "%mreg" << getReg();
189    }
190
191    if (getSubReg() != 0) {
192      OS << ":" << getSubReg();
193    }
194
195    if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
196      OS << "<";
197      bool NeedComma = false;
198      if (isImplicit()) {
199        if (NeedComma) OS << ",";
200        OS << (isDef() ? "imp-def" : "imp-use");
201        NeedComma = true;
202      } else if (isDef()) {
203        if (NeedComma) OS << ",";
204        if (isEarlyClobber())
205          OS << "earlyclobber,";
206        OS << "def";
207        NeedComma = true;
208      }
209      if (isKill() || isDead()) {
210        if (NeedComma) OS << ",";
211        if (isKill())  OS << "kill";
212        if (isDead())  OS << "dead";
213      }
214      OS << ">";
215    }
216    break;
217  case MachineOperand::MO_Immediate:
218    OS << getImm();
219    break;
220  case MachineOperand::MO_FPImmediate:
221    if (getFPImm()->getType() == Type::FloatTy) {
222      OS << getFPImm()->getValueAPF().convertToFloat();
223    } else {
224      OS << getFPImm()->getValueAPF().convertToDouble();
225    }
226    break;
227  case MachineOperand::MO_MachineBasicBlock:
228    OS << "mbb<"
229       << ((Value*)getMBB()->getBasicBlock())->getName()
230       << "," << (void*)getMBB() << ">";
231    break;
232  case MachineOperand::MO_FrameIndex:
233    OS << "<fi#" << getIndex() << ">";
234    break;
235  case MachineOperand::MO_ConstantPoolIndex:
236    OS << "<cp#" << getIndex();
237    if (getOffset()) OS << "+" << getOffset();
238    OS << ">";
239    break;
240  case MachineOperand::MO_JumpTableIndex:
241    OS << "<jt#" << getIndex() << ">";
242    break;
243  case MachineOperand::MO_GlobalAddress:
244    OS << "<ga:" << ((Value*)getGlobal())->getName();
245    if (getOffset()) OS << "+" << getOffset();
246    OS << ">";
247    break;
248  case MachineOperand::MO_ExternalSymbol:
249    OS << "<es:" << getSymbolName();
250    if (getOffset()) OS << "+" << getOffset();
251    OS << ">";
252    break;
253  default:
254    assert(0 && "Unrecognized operand type");
255  }
256}
257
258//===----------------------------------------------------------------------===//
259// MachineMemOperand Implementation
260//===----------------------------------------------------------------------===//
261
262MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
263                                     int64_t o, uint64_t s, unsigned int a)
264  : Offset(o), Size(s), V(v),
265    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
266  assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
267  assert((isLoad() || isStore()) && "Not a load/store!");
268}
269
270/// Profile - Gather unique data for the object.
271///
272void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
273  ID.AddInteger(Offset);
274  ID.AddInteger(Size);
275  ID.AddPointer(V);
276  ID.AddInteger(Flags);
277}
278
279//===----------------------------------------------------------------------===//
280// MachineInstr Implementation
281//===----------------------------------------------------------------------===//
282
283/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
284/// TID NULL and no operands.
285MachineInstr::MachineInstr()
286  : TID(0), NumImplicitOps(0), Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
287  // Make sure that we get added to a machine basicblock
288  LeakDetector::addGarbageObject(this);
289}
290
291void MachineInstr::addImplicitDefUseOperands() {
292  if (TID->ImplicitDefs)
293    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
294      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
295  if (TID->ImplicitUses)
296    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
297      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
298}
299
300/// MachineInstr ctor - This constructor create a MachineInstr and add the
301/// implicit operands. It reserves space for number of operands specified by
302/// TargetInstrDesc or the numOperands if it is not zero. (for
303/// instructions with variable number of operands).
304MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
305  : TID(&tid), NumImplicitOps(0), Parent(0),
306    debugLoc(DebugLoc::getUnknownLoc()) {
307  if (!NoImp && TID->getImplicitDefs())
308    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
309      NumImplicitOps++;
310  if (!NoImp && TID->getImplicitUses())
311    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
312      NumImplicitOps++;
313  Operands.reserve(NumImplicitOps + TID->getNumOperands());
314  if (!NoImp)
315    addImplicitDefUseOperands();
316  // Make sure that we get added to a machine basicblock
317  LeakDetector::addGarbageObject(this);
318}
319
320/// MachineInstr ctor - As above, but with a DebugLoc.
321MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
322                           bool NoImp)
323  : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
324  if (!NoImp && TID->getImplicitDefs())
325    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
326      NumImplicitOps++;
327  if (!NoImp && TID->getImplicitUses())
328    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
329      NumImplicitOps++;
330  Operands.reserve(NumImplicitOps + TID->getNumOperands());
331  if (!NoImp)
332    addImplicitDefUseOperands();
333  // Make sure that we get added to a machine basicblock
334  LeakDetector::addGarbageObject(this);
335}
336
337/// MachineInstr ctor - Work exactly the same as the ctor two above, except
338/// that the MachineInstr is created and added to the end of the specified
339/// basic block.
340///
341MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
342  : TID(&tid), NumImplicitOps(0), Parent(0),
343    debugLoc(DebugLoc::getUnknownLoc()) {
344  assert(MBB && "Cannot use inserting ctor with null basic block!");
345  if (TID->ImplicitDefs)
346    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
347      NumImplicitOps++;
348  if (TID->ImplicitUses)
349    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
350      NumImplicitOps++;
351  Operands.reserve(NumImplicitOps + TID->getNumOperands());
352  addImplicitDefUseOperands();
353  // Make sure that we get added to a machine basicblock
354  LeakDetector::addGarbageObject(this);
355  MBB->push_back(this);  // Add instruction to end of basic block!
356}
357
358/// MachineInstr ctor - As above, but with a DebugLoc.
359///
360MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
361                           const TargetInstrDesc &tid)
362  : TID(&tid), NumImplicitOps(0), Parent(0), debugLoc(dl) {
363  assert(MBB && "Cannot use inserting ctor with null basic block!");
364  if (TID->ImplicitDefs)
365    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
366      NumImplicitOps++;
367  if (TID->ImplicitUses)
368    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
369      NumImplicitOps++;
370  Operands.reserve(NumImplicitOps + TID->getNumOperands());
371  addImplicitDefUseOperands();
372  // Make sure that we get added to a machine basicblock
373  LeakDetector::addGarbageObject(this);
374  MBB->push_back(this);  // Add instruction to end of basic block!
375}
376
377/// MachineInstr ctor - Copies MachineInstr arg exactly
378///
379MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
380  : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0),
381        debugLoc(MI.getDebugLoc()) {
382  Operands.reserve(MI.getNumOperands());
383
384  // Add operands
385  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
386    addOperand(MI.getOperand(i));
387  NumImplicitOps = MI.NumImplicitOps;
388
389  // Add memory operands.
390  for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
391       j = MI.memoperands_end(); i != j; ++i)
392    addMemOperand(MF, *i);
393
394  // Set parent to null.
395  Parent = 0;
396
397  LeakDetector::addGarbageObject(this);
398}
399
400MachineInstr::~MachineInstr() {
401  LeakDetector::removeGarbageObject(this);
402  assert(MemOperands.empty() &&
403         "MachineInstr being deleted with live memoperands!");
404#ifndef NDEBUG
405  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
406    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
407    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
408           "Reg operand def/use list corrupted");
409  }
410#endif
411}
412
413/// getRegInfo - If this instruction is embedded into a MachineFunction,
414/// return the MachineRegisterInfo object for the current function, otherwise
415/// return null.
416MachineRegisterInfo *MachineInstr::getRegInfo() {
417  if (MachineBasicBlock *MBB = getParent())
418    return &MBB->getParent()->getRegInfo();
419  return 0;
420}
421
422/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
423/// this instruction from their respective use lists.  This requires that the
424/// operands already be on their use lists.
425void MachineInstr::RemoveRegOperandsFromUseLists() {
426  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
427    if (Operands[i].isReg())
428      Operands[i].RemoveRegOperandFromRegInfo();
429  }
430}
431
432/// AddRegOperandsToUseLists - Add all of the register operands in
433/// this instruction from their respective use lists.  This requires that the
434/// operands not be on their use lists yet.
435void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
436  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
437    if (Operands[i].isReg())
438      Operands[i].AddRegOperandToRegInfo(&RegInfo);
439  }
440}
441
442
443/// addOperand - Add the specified operand to the instruction.  If it is an
444/// implicit operand, it is added to the end of the operand list.  If it is
445/// an explicit operand it is added at the end of the explicit operand list
446/// (before the first implicit operand).
447void MachineInstr::addOperand(const MachineOperand &Op) {
448  bool isImpReg = Op.isReg() && Op.isImplicit();
449  assert((isImpReg || !OperandsComplete()) &&
450         "Trying to add an operand to a machine instr that is already done!");
451
452  MachineRegisterInfo *RegInfo = getRegInfo();
453
454  // If we are adding the operand to the end of the list, our job is simpler.
455  // This is true most of the time, so this is a reasonable optimization.
456  if (isImpReg || NumImplicitOps == 0) {
457    // We can only do this optimization if we know that the operand list won't
458    // reallocate.
459    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
460      Operands.push_back(Op);
461
462      // Set the parent of the operand.
463      Operands.back().ParentMI = this;
464
465      // If the operand is a register, update the operand's use list.
466      if (Op.isReg())
467        Operands.back().AddRegOperandToRegInfo(RegInfo);
468      return;
469    }
470  }
471
472  // Otherwise, we have to insert a real operand before any implicit ones.
473  unsigned OpNo = Operands.size()-NumImplicitOps;
474
475  // If this instruction isn't embedded into a function, then we don't need to
476  // update any operand lists.
477  if (RegInfo == 0) {
478    // Simple insertion, no reginfo update needed for other register operands.
479    Operands.insert(Operands.begin()+OpNo, Op);
480    Operands[OpNo].ParentMI = this;
481
482    // Do explicitly set the reginfo for this operand though, to ensure the
483    // next/prev fields are properly nulled out.
484    if (Operands[OpNo].isReg())
485      Operands[OpNo].AddRegOperandToRegInfo(0);
486
487  } else if (Operands.size()+1 <= Operands.capacity()) {
488    // Otherwise, we have to remove register operands from their register use
489    // list, add the operand, then add the register operands back to their use
490    // list.  This also must handle the case when the operand list reallocates
491    // to somewhere else.
492
493    // If insertion of this operand won't cause reallocation of the operand
494    // list, just remove the implicit operands, add the operand, then re-add all
495    // the rest of the operands.
496    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
497      assert(Operands[i].isReg() && "Should only be an implicit reg!");
498      Operands[i].RemoveRegOperandFromRegInfo();
499    }
500
501    // Add the operand.  If it is a register, add it to the reg list.
502    Operands.insert(Operands.begin()+OpNo, Op);
503    Operands[OpNo].ParentMI = this;
504
505    if (Operands[OpNo].isReg())
506      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
507
508    // Re-add all the implicit ops.
509    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
510      assert(Operands[i].isReg() && "Should only be an implicit reg!");
511      Operands[i].AddRegOperandToRegInfo(RegInfo);
512    }
513  } else {
514    // Otherwise, we will be reallocating the operand list.  Remove all reg
515    // operands from their list, then readd them after the operand list is
516    // reallocated.
517    RemoveRegOperandsFromUseLists();
518
519    Operands.insert(Operands.begin()+OpNo, Op);
520    Operands[OpNo].ParentMI = this;
521
522    // Re-add all the operands.
523    AddRegOperandsToUseLists(*RegInfo);
524  }
525}
526
527/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
528/// fewer operand than it started with.
529///
530void MachineInstr::RemoveOperand(unsigned OpNo) {
531  assert(OpNo < Operands.size() && "Invalid operand number");
532
533  // Special case removing the last one.
534  if (OpNo == Operands.size()-1) {
535    // If needed, remove from the reg def/use list.
536    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
537      Operands.back().RemoveRegOperandFromRegInfo();
538
539    Operands.pop_back();
540    return;
541  }
542
543  // Otherwise, we are removing an interior operand.  If we have reginfo to
544  // update, remove all operands that will be shifted down from their reg lists,
545  // move everything down, then re-add them.
546  MachineRegisterInfo *RegInfo = getRegInfo();
547  if (RegInfo) {
548    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
549      if (Operands[i].isReg())
550        Operands[i].RemoveRegOperandFromRegInfo();
551    }
552  }
553
554  Operands.erase(Operands.begin()+OpNo);
555
556  if (RegInfo) {
557    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
558      if (Operands[i].isReg())
559        Operands[i].AddRegOperandToRegInfo(RegInfo);
560    }
561  }
562}
563
564/// addMemOperand - Add a MachineMemOperand to the machine instruction,
565/// referencing arbitrary storage.
566void MachineInstr::addMemOperand(MachineFunction &MF,
567                                 const MachineMemOperand &MO) {
568  MemOperands.push_back(MO);
569}
570
571/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
572void MachineInstr::clearMemOperands(MachineFunction &MF) {
573  MemOperands.clear();
574}
575
576
577/// removeFromParent - This method unlinks 'this' from the containing basic
578/// block, and returns it, but does not delete it.
579MachineInstr *MachineInstr::removeFromParent() {
580  assert(getParent() && "Not embedded in a basic block!");
581  getParent()->remove(this);
582  return this;
583}
584
585
586/// eraseFromParent - This method unlinks 'this' from the containing basic
587/// block, and deletes it.
588void MachineInstr::eraseFromParent() {
589  assert(getParent() && "Not embedded in a basic block!");
590  getParent()->erase(this);
591}
592
593
594/// OperandComplete - Return true if it's illegal to add a new operand
595///
596bool MachineInstr::OperandsComplete() const {
597  unsigned short NumOperands = TID->getNumOperands();
598  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
599    return true;  // Broken: we have all the operands of this instruction!
600  return false;
601}
602
603/// getNumExplicitOperands - Returns the number of non-implicit operands.
604///
605unsigned MachineInstr::getNumExplicitOperands() const {
606  unsigned NumOperands = TID->getNumOperands();
607  if (!TID->isVariadic())
608    return NumOperands;
609
610  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
611    const MachineOperand &MO = getOperand(NumOperands);
612    if (!MO.isReg() || !MO.isImplicit())
613      NumOperands++;
614  }
615  return NumOperands;
616}
617
618
619/// isLabel - Returns true if the MachineInstr represents a label.
620///
621bool MachineInstr::isLabel() const {
622  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
623         getOpcode() == TargetInstrInfo::EH_LABEL ||
624         getOpcode() == TargetInstrInfo::GC_LABEL;
625}
626
627/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
628///
629bool MachineInstr::isDebugLabel() const {
630  return getOpcode() == TargetInstrInfo::DBG_LABEL;
631}
632
633/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
634/// the specific register or -1 if it is not found. It further tightening
635/// the search criteria to a use that kills the register if isKill is true.
636int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
637                                          const TargetRegisterInfo *TRI) const {
638  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
639    const MachineOperand &MO = getOperand(i);
640    if (!MO.isReg() || !MO.isUse())
641      continue;
642    unsigned MOReg = MO.getReg();
643    if (!MOReg)
644      continue;
645    if (MOReg == Reg ||
646        (TRI &&
647         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
648         TargetRegisterInfo::isPhysicalRegister(Reg) &&
649         TRI->isSubRegister(MOReg, Reg)))
650      if (!isKill || MO.isKill())
651        return i;
652  }
653  return -1;
654}
655
656/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
657/// the specified register or -1 if it is not found. If isDead is true, defs
658/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
659/// also checks if there is a def of a super-register.
660int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
661                                          const TargetRegisterInfo *TRI) const {
662  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
663    const MachineOperand &MO = getOperand(i);
664    if (!MO.isReg() || !MO.isDef())
665      continue;
666    unsigned MOReg = MO.getReg();
667    if (MOReg == Reg ||
668        (TRI &&
669         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
670         TargetRegisterInfo::isPhysicalRegister(Reg) &&
671         TRI->isSubRegister(MOReg, Reg)))
672      if (!isDead || MO.isDead())
673        return i;
674  }
675  return -1;
676}
677
678/// findFirstPredOperandIdx() - Find the index of the first operand in the
679/// operand list that is used to represent the predicate. It returns -1 if
680/// none is found.
681int MachineInstr::findFirstPredOperandIdx() const {
682  const TargetInstrDesc &TID = getDesc();
683  if (TID.isPredicable()) {
684    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
685      if (TID.OpInfo[i].isPredicate())
686        return i;
687  }
688
689  return -1;
690}
691
692/// isRegReDefinedByTwoAddr - Given the index of a register def operand,
693/// check if the register def is a re-definition due to two addr elimination.
694bool MachineInstr::isRegReDefinedByTwoAddr(unsigned DefIdx) const{
695  assert(getOperand(DefIdx).isDef() && "DefIdx is not a def!");
696  const TargetInstrDesc &TID = getDesc();
697  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
698    const MachineOperand &MO = getOperand(i);
699    if (MO.isReg() && MO.isUse() &&
700        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
701      return true;
702  }
703  return false;
704}
705
706/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
707///
708void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
709  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
710    const MachineOperand &MO = MI->getOperand(i);
711    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
712      continue;
713    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
714      MachineOperand &MOp = getOperand(j);
715      if (!MOp.isIdenticalTo(MO))
716        continue;
717      if (MO.isKill())
718        MOp.setIsKill();
719      else
720        MOp.setIsDead();
721      break;
722    }
723  }
724}
725
726/// copyPredicates - Copies predicate operand(s) from MI.
727void MachineInstr::copyPredicates(const MachineInstr *MI) {
728  const TargetInstrDesc &TID = MI->getDesc();
729  if (!TID.isPredicable())
730    return;
731  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
732    if (TID.OpInfo[i].isPredicate()) {
733      // Predicated operands must be last operands.
734      addOperand(MI->getOperand(i));
735    }
736  }
737}
738
739/// isSafeToMove - Return true if it is safe to move this instruction. If
740/// SawStore is set to true, it means that there is a store (or call) between
741/// the instruction's location and its intended destination.
742bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
743                                bool &SawStore) const {
744  // Ignore stuff that we obviously can't move.
745  if (TID->mayStore() || TID->isCall()) {
746    SawStore = true;
747    return false;
748  }
749  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
750    return false;
751
752  // See if this instruction does a load.  If so, we have to guarantee that the
753  // loaded value doesn't change between the load and the its intended
754  // destination. The check for isInvariantLoad gives the targe the chance to
755  // classify the load as always returning a constant, e.g. a constant pool
756  // load.
757  if (TID->mayLoad() && !TII->isInvariantLoad(this))
758    // Otherwise, this is a real load.  If there is a store between the load and
759    // end of block, or if the laod is volatile, we can't move it.
760    return !SawStore && !hasVolatileMemoryRef();
761
762  return true;
763}
764
765/// isSafeToReMat - Return true if it's safe to rematerialize the specified
766/// instruction which defined the specified register instead of copying it.
767bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
768                                 unsigned DstReg) const {
769  bool SawStore = false;
770  if (!getDesc().isRematerializable() ||
771      !TII->isTriviallyReMaterializable(this) ||
772      !isSafeToMove(TII, SawStore))
773    return false;
774  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
775    const MachineOperand &MO = getOperand(i);
776    if (!MO.isReg())
777      continue;
778    // FIXME: For now, do not remat any instruction with register operands.
779    // Later on, we can loosen the restriction is the register operands have
780    // not been modified between the def and use. Note, this is different from
781    // MachineSink because the code is no longer in two-address form (at least
782    // partially).
783    if (MO.isUse())
784      return false;
785    else if (!MO.isDead() && MO.getReg() != DstReg)
786      return false;
787  }
788  return true;
789}
790
791/// hasVolatileMemoryRef - Return true if this instruction may have a
792/// volatile memory reference, or if the information describing the
793/// memory reference is not available. Return false if it is known to
794/// have no volatile memory references.
795bool MachineInstr::hasVolatileMemoryRef() const {
796  // An instruction known never to access memory won't have a volatile access.
797  if (!TID->mayStore() &&
798      !TID->mayLoad() &&
799      !TID->isCall() &&
800      !TID->hasUnmodeledSideEffects())
801    return false;
802
803  // Otherwise, if the instruction has no memory reference information,
804  // conservatively assume it wasn't preserved.
805  if (memoperands_empty())
806    return true;
807
808  // Check the memory reference information for volatile references.
809  for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
810       E = memoperands_end(); I != E; ++I)
811    if (I->isVolatile())
812      return true;
813
814  return false;
815}
816
817void MachineInstr::dump() const {
818  cerr << "  " << *this;
819}
820
821void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
822  raw_os_ostream RawOS(OS);
823  print(RawOS, TM);
824}
825
826void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
827  // Specialize printing if op#0 is definition
828  unsigned StartOp = 0;
829  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
830    getOperand(0).print(OS, TM);
831    OS << " = ";
832    ++StartOp;   // Don't print this operand again!
833  }
834
835  OS << getDesc().getName();
836
837  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
838    if (i != StartOp)
839      OS << ",";
840    OS << " ";
841    getOperand(i).print(OS, TM);
842  }
843
844  if (!memoperands_empty()) {
845    OS << ", Mem:";
846    for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
847         e = memoperands_end(); i != e; ++i) {
848      const MachineMemOperand &MRO = *i;
849      const Value *V = MRO.getValue();
850
851      assert((MRO.isLoad() || MRO.isStore()) &&
852             "SV has to be a load, store or both.");
853
854      if (MRO.isVolatile())
855        OS << "Volatile ";
856
857      if (MRO.isLoad())
858        OS << "LD";
859      if (MRO.isStore())
860        OS << "ST";
861
862      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
863
864      if (!V)
865        OS << "<unknown>";
866      else if (!V->getName().empty())
867        OS << V->getName();
868      else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
869        PSV->print(OS);
870      } else
871        OS << V;
872
873      OS << " + " << MRO.getOffset() << "]";
874    }
875  }
876
877  if (!debugLoc.isUnknown()) {
878    const MachineFunction *MF = getParent()->getParent();
879    DebugLocTuple DLT = MF->getDebugLocTuple(debugLoc);
880    OS << " [dbg: "
881       << DLT.Src  << ","
882       << DLT.Line << ","
883       << DLT.Col  << "]";
884  }
885
886  OS << "\n";
887}
888
889bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
890                                     const TargetRegisterInfo *RegInfo,
891                                     bool AddIfNotFound) {
892  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
893  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
894  bool Found = false;
895  SmallVector<unsigned,4> DeadOps;
896  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
897    MachineOperand &MO = getOperand(i);
898    if (!MO.isReg() || !MO.isUse())
899      continue;
900    unsigned Reg = MO.getReg();
901    if (!Reg)
902      continue;
903
904    if (Reg == IncomingReg) {
905      if (!Found) {
906        if (MO.isKill())
907          // The register is already marked kill.
908          return true;
909        MO.setIsKill();
910        Found = true;
911      }
912    } else if (hasAliases && MO.isKill() &&
913               TargetRegisterInfo::isPhysicalRegister(Reg)) {
914      // A super-register kill already exists.
915      if (RegInfo->isSuperRegister(IncomingReg, Reg))
916        return true;
917      if (RegInfo->isSubRegister(IncomingReg, Reg))
918        DeadOps.push_back(i);
919    }
920  }
921
922  // Trim unneeded kill operands.
923  while (!DeadOps.empty()) {
924    unsigned OpIdx = DeadOps.back();
925    if (getOperand(OpIdx).isImplicit())
926      RemoveOperand(OpIdx);
927    else
928      getOperand(OpIdx).setIsKill(false);
929    DeadOps.pop_back();
930  }
931
932  // If not found, this means an alias of one of the operands is killed. Add a
933  // new implicit operand if required.
934  if (!Found && AddIfNotFound) {
935    addOperand(MachineOperand::CreateReg(IncomingReg,
936                                         false /*IsDef*/,
937                                         true  /*IsImp*/,
938                                         true  /*IsKill*/));
939    return true;
940  }
941  return Found;
942}
943
944bool MachineInstr::addRegisterDead(unsigned IncomingReg,
945                                   const TargetRegisterInfo *RegInfo,
946                                   bool AddIfNotFound) {
947  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
948  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
949  bool Found = false;
950  SmallVector<unsigned,4> DeadOps;
951  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
952    MachineOperand &MO = getOperand(i);
953    if (!MO.isReg() || !MO.isDef())
954      continue;
955    unsigned Reg = MO.getReg();
956    if (!Reg)
957      continue;
958
959    if (Reg == IncomingReg) {
960      if (!Found) {
961        if (MO.isDead())
962          // The register is already marked dead.
963          return true;
964        MO.setIsDead();
965        Found = true;
966      }
967    } else if (hasAliases && MO.isDead() &&
968               TargetRegisterInfo::isPhysicalRegister(Reg)) {
969      // There exists a super-register that's marked dead.
970      if (RegInfo->isSuperRegister(IncomingReg, Reg))
971        return true;
972      if (RegInfo->getSubRegisters(IncomingReg) &&
973          RegInfo->getSuperRegisters(Reg) &&
974          RegInfo->isSubRegister(IncomingReg, Reg))
975        DeadOps.push_back(i);
976    }
977  }
978
979  // Trim unneeded dead operands.
980  while (!DeadOps.empty()) {
981    unsigned OpIdx = DeadOps.back();
982    if (getOperand(OpIdx).isImplicit())
983      RemoveOperand(OpIdx);
984    else
985      getOperand(OpIdx).setIsDead(false);
986    DeadOps.pop_back();
987  }
988
989  // If not found, this means an alias of one of the operands is dead. Add a
990  // new implicit operand if required.
991  if (!Found && AddIfNotFound) {
992    addOperand(MachineOperand::CreateReg(IncomingReg,
993                                         true  /*IsDef*/,
994                                         true  /*IsImp*/,
995                                         false /*IsKill*/,
996                                         true  /*IsDead*/));
997    return true;
998  }
999  return Found;
1000}
1001