MachineInstr.cpp revision c6ada8e5f38168f13830e448f2b9e2d8e3eac72b 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/FoldingSet.h"
16#include "llvm/ADT/Hashing.h"
17#include "llvm/Analysis/AliasAnalysis.h"
18#include "llvm/Assembly/Writer.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineMemOperand.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PseudoSourceValue.h"
25#include "llvm/DebugInfo.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/IR/Function.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/LLVMContext.h"
30#include "llvm/IR/Metadata.h"
31#include "llvm/IR/Module.h"
32#include "llvm/IR/Type.h"
33#include "llvm/IR/Value.h"
34#include "llvm/MC/MCInstrDesc.h"
35#include "llvm/MC/MCSymbol.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/MathExtras.h"
39#include "llvm/Support/raw_ostream.h"
40#include "llvm/Target/TargetInstrInfo.h"
41#include "llvm/Target/TargetMachine.h"
42#include "llvm/Target/TargetRegisterInfo.h"
43using namespace llvm;
44
45//===----------------------------------------------------------------------===//
46// MachineOperand Implementation
47//===----------------------------------------------------------------------===//
48
49void MachineOperand::setReg(unsigned Reg) {
50  if (getReg() == Reg) return; // No change.
51
52  // Otherwise, we have to change the register.  If this operand is embedded
53  // into a machine function, we need to update the old and new register's
54  // use/def lists.
55  if (MachineInstr *MI = getParent())
56    if (MachineBasicBlock *MBB = MI->getParent())
57      if (MachineFunction *MF = MBB->getParent()) {
58        MachineRegisterInfo &MRI = MF->getRegInfo();
59        MRI.removeRegOperandFromUseList(this);
60        SmallContents.RegNo = Reg;
61        MRI.addRegOperandToUseList(this);
62        return;
63      }
64
65  // Otherwise, just change the register, no problem.  :)
66  SmallContents.RegNo = Reg;
67}
68
69void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
70                                  const TargetRegisterInfo &TRI) {
71  assert(TargetRegisterInfo::isVirtualRegister(Reg));
72  if (SubIdx && getSubReg())
73    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
74  setReg(Reg);
75  if (SubIdx)
76    setSubReg(SubIdx);
77}
78
79void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
80  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
81  if (getSubReg()) {
82    Reg = TRI.getSubReg(Reg, getSubReg());
83    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
84    // That won't happen in legal code.
85    setSubReg(0);
86  }
87  setReg(Reg);
88}
89
90/// Change a def to a use, or a use to a def.
91void MachineOperand::setIsDef(bool Val) {
92  assert(isReg() && "Wrong MachineOperand accessor");
93  assert((!Val || !isDebug()) && "Marking a debug operation as def");
94  if (IsDef == Val)
95    return;
96  // MRI may keep uses and defs in different list positions.
97  if (MachineInstr *MI = getParent())
98    if (MachineBasicBlock *MBB = MI->getParent())
99      if (MachineFunction *MF = MBB->getParent()) {
100        MachineRegisterInfo &MRI = MF->getRegInfo();
101        MRI.removeRegOperandFromUseList(this);
102        IsDef = Val;
103        MRI.addRegOperandToUseList(this);
104        return;
105      }
106  IsDef = Val;
107}
108
109/// ChangeToImmediate - Replace this operand with a new immediate operand of
110/// the specified value.  If an operand is known to be an immediate already,
111/// the setImm method should be used.
112void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
113  assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
114  // If this operand is currently a register operand, and if this is in a
115  // function, deregister the operand from the register's use/def list.
116  if (isReg() && isOnRegUseList())
117    if (MachineInstr *MI = getParent())
118      if (MachineBasicBlock *MBB = MI->getParent())
119        if (MachineFunction *MF = MBB->getParent())
120          MF->getRegInfo().removeRegOperandFromUseList(this);
121
122  OpKind = MO_Immediate;
123  Contents.ImmVal = ImmVal;
124}
125
126/// ChangeToRegister - Replace this operand with a new register operand of
127/// the specified value.  If an operand is known to be an register already,
128/// the setReg method should be used.
129void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
130                                      bool isKill, bool isDead, bool isUndef,
131                                      bool isDebug) {
132  MachineRegisterInfo *RegInfo = 0;
133  if (MachineInstr *MI = getParent())
134    if (MachineBasicBlock *MBB = MI->getParent())
135      if (MachineFunction *MF = MBB->getParent())
136        RegInfo = &MF->getRegInfo();
137  // If this operand is already a register operand, remove it from the
138  // register's use/def lists.
139  bool WasReg = isReg();
140  if (RegInfo && WasReg)
141    RegInfo->removeRegOperandFromUseList(this);
142
143  // Change this to a register and set the reg#.
144  OpKind = MO_Register;
145  SmallContents.RegNo = Reg;
146  SubReg_TargetFlags = 0;
147  IsDef = isDef;
148  IsImp = isImp;
149  IsKill = isKill;
150  IsDead = isDead;
151  IsUndef = isUndef;
152  IsInternalRead = false;
153  IsEarlyClobber = false;
154  IsDebug = isDebug;
155  // Ensure isOnRegUseList() returns false.
156  Contents.Reg.Prev = 0;
157  // Preserve the tie when the operand was already a register.
158  if (!WasReg)
159    TiedTo = 0;
160
161  // If this operand is embedded in a function, add the operand to the
162  // register's use/def list.
163  if (RegInfo)
164    RegInfo->addRegOperandToUseList(this);
165}
166
167/// isIdenticalTo - Return true if this operand is identical to the specified
168/// operand. Note that this should stay in sync with the hash_value overload
169/// below.
170bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
171  if (getType() != Other.getType() ||
172      getTargetFlags() != Other.getTargetFlags())
173    return false;
174
175  switch (getType()) {
176  case MachineOperand::MO_Register:
177    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
178           getSubReg() == Other.getSubReg();
179  case MachineOperand::MO_Immediate:
180    return getImm() == Other.getImm();
181  case MachineOperand::MO_CImmediate:
182    return getCImm() == Other.getCImm();
183  case MachineOperand::MO_FPImmediate:
184    return getFPImm() == Other.getFPImm();
185  case MachineOperand::MO_MachineBasicBlock:
186    return getMBB() == Other.getMBB();
187  case MachineOperand::MO_FrameIndex:
188    return getIndex() == Other.getIndex();
189  case MachineOperand::MO_ConstantPoolIndex:
190  case MachineOperand::MO_TargetIndex:
191    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
192  case MachineOperand::MO_JumpTableIndex:
193    return getIndex() == Other.getIndex();
194  case MachineOperand::MO_GlobalAddress:
195    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
196  case MachineOperand::MO_ExternalSymbol:
197    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
198           getOffset() == Other.getOffset();
199  case MachineOperand::MO_BlockAddress:
200    return getBlockAddress() == Other.getBlockAddress() &&
201           getOffset() == Other.getOffset();
202  case MO_RegisterMask:
203    return getRegMask() == Other.getRegMask();
204  case MachineOperand::MO_MCSymbol:
205    return getMCSymbol() == Other.getMCSymbol();
206  case MachineOperand::MO_Metadata:
207    return getMetadata() == Other.getMetadata();
208  }
209  llvm_unreachable("Invalid machine operand type");
210}
211
212// Note: this must stay exactly in sync with isIdenticalTo above.
213hash_code llvm::hash_value(const MachineOperand &MO) {
214  switch (MO.getType()) {
215  case MachineOperand::MO_Register:
216    // Register operands don't have target flags.
217    return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
218  case MachineOperand::MO_Immediate:
219    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
220  case MachineOperand::MO_CImmediate:
221    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
222  case MachineOperand::MO_FPImmediate:
223    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
224  case MachineOperand::MO_MachineBasicBlock:
225    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
226  case MachineOperand::MO_FrameIndex:
227    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
228  case MachineOperand::MO_ConstantPoolIndex:
229  case MachineOperand::MO_TargetIndex:
230    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
231                        MO.getOffset());
232  case MachineOperand::MO_JumpTableIndex:
233    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
234  case MachineOperand::MO_ExternalSymbol:
235    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
236                        MO.getSymbolName());
237  case MachineOperand::MO_GlobalAddress:
238    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
239                        MO.getOffset());
240  case MachineOperand::MO_BlockAddress:
241    return hash_combine(MO.getType(), MO.getTargetFlags(),
242                        MO.getBlockAddress(), MO.getOffset());
243  case MachineOperand::MO_RegisterMask:
244    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
245  case MachineOperand::MO_Metadata:
246    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247  case MachineOperand::MO_MCSymbol:
248    return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
249  }
250  llvm_unreachable("Invalid machine operand type");
251}
252
253/// print - Print the specified machine operand.
254///
255void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
256  // If the instruction is embedded into a basic block, we can find the
257  // target info for the instruction.
258  if (!TM)
259    if (const MachineInstr *MI = getParent())
260      if (const MachineBasicBlock *MBB = MI->getParent())
261        if (const MachineFunction *MF = MBB->getParent())
262          TM = &MF->getTarget();
263  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
264
265  switch (getType()) {
266  case MachineOperand::MO_Register:
267    OS << PrintReg(getReg(), TRI, getSubReg());
268
269    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
270        isInternalRead() || isEarlyClobber() || isTied()) {
271      OS << '<';
272      bool NeedComma = false;
273      if (isDef()) {
274        if (NeedComma) OS << ',';
275        if (isEarlyClobber())
276          OS << "earlyclobber,";
277        if (isImplicit())
278          OS << "imp-";
279        OS << "def";
280        NeedComma = true;
281        // <def,read-undef> only makes sense when getSubReg() is set.
282        // Don't clutter the output otherwise.
283        if (isUndef() && getSubReg())
284          OS << ",read-undef";
285      } else if (isImplicit()) {
286          OS << "imp-use";
287          NeedComma = true;
288      }
289
290      if (isKill()) {
291        if (NeedComma) OS << ',';
292        OS << "kill";
293        NeedComma = true;
294      }
295      if (isDead()) {
296        if (NeedComma) OS << ',';
297        OS << "dead";
298        NeedComma = true;
299      }
300      if (isUndef() && isUse()) {
301        if (NeedComma) OS << ',';
302        OS << "undef";
303        NeedComma = true;
304      }
305      if (isInternalRead()) {
306        if (NeedComma) OS << ',';
307        OS << "internal";
308        NeedComma = true;
309      }
310      if (isTied()) {
311        if (NeedComma) OS << ',';
312        OS << "tied";
313        if (TiedTo != 15)
314          OS << unsigned(TiedTo - 1);
315        NeedComma = true;
316      }
317      OS << '>';
318    }
319    break;
320  case MachineOperand::MO_Immediate:
321    OS << getImm();
322    break;
323  case MachineOperand::MO_CImmediate:
324    getCImm()->getValue().print(OS, false);
325    break;
326  case MachineOperand::MO_FPImmediate:
327    if (getFPImm()->getType()->isFloatTy())
328      OS << getFPImm()->getValueAPF().convertToFloat();
329    else
330      OS << getFPImm()->getValueAPF().convertToDouble();
331    break;
332  case MachineOperand::MO_MachineBasicBlock:
333    OS << "<BB#" << getMBB()->getNumber() << ">";
334    break;
335  case MachineOperand::MO_FrameIndex:
336    OS << "<fi#" << getIndex() << '>';
337    break;
338  case MachineOperand::MO_ConstantPoolIndex:
339    OS << "<cp#" << getIndex();
340    if (getOffset()) OS << "+" << getOffset();
341    OS << '>';
342    break;
343  case MachineOperand::MO_TargetIndex:
344    OS << "<ti#" << getIndex();
345    if (getOffset()) OS << "+" << getOffset();
346    OS << '>';
347    break;
348  case MachineOperand::MO_JumpTableIndex:
349    OS << "<jt#" << getIndex() << '>';
350    break;
351  case MachineOperand::MO_GlobalAddress:
352    OS << "<ga:";
353    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
354    if (getOffset()) OS << "+" << getOffset();
355    OS << '>';
356    break;
357  case MachineOperand::MO_ExternalSymbol:
358    OS << "<es:" << getSymbolName();
359    if (getOffset()) OS << "+" << getOffset();
360    OS << '>';
361    break;
362  case MachineOperand::MO_BlockAddress:
363    OS << '<';
364    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
365    if (getOffset()) OS << "+" << getOffset();
366    OS << '>';
367    break;
368  case MachineOperand::MO_RegisterMask:
369    OS << "<regmask>";
370    break;
371  case MachineOperand::MO_Metadata:
372    OS << '<';
373    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
374    OS << '>';
375    break;
376  case MachineOperand::MO_MCSymbol:
377    OS << "<MCSym=" << *getMCSymbol() << '>';
378    break;
379  }
380
381  if (unsigned TF = getTargetFlags())
382    OS << "[TF=" << TF << ']';
383}
384
385//===----------------------------------------------------------------------===//
386// MachineMemOperand Implementation
387//===----------------------------------------------------------------------===//
388
389/// getAddrSpace - Return the LLVM IR address space number that this pointer
390/// points into.
391unsigned MachinePointerInfo::getAddrSpace() const {
392  if (V == 0) return 0;
393  return cast<PointerType>(V->getType())->getAddressSpace();
394}
395
396/// getConstantPool - Return a MachinePointerInfo record that refers to the
397/// constant pool.
398MachinePointerInfo MachinePointerInfo::getConstantPool() {
399  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
400}
401
402/// getFixedStack - Return a MachinePointerInfo record that refers to the
403/// the specified FrameIndex.
404MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
405  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
406}
407
408MachinePointerInfo MachinePointerInfo::getJumpTable() {
409  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
410}
411
412MachinePointerInfo MachinePointerInfo::getGOT() {
413  return MachinePointerInfo(PseudoSourceValue::getGOT());
414}
415
416MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
417  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
418}
419
420MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
421                                     uint64_t s, unsigned int a,
422                                     const MDNode *TBAAInfo,
423                                     const MDNode *Ranges)
424  : PtrInfo(ptrinfo), Size(s),
425    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
426    TBAAInfo(TBAAInfo), Ranges(Ranges) {
427  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
428         "invalid pointer value");
429  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
430  assert((isLoad() || isStore()) && "Not a load/store!");
431}
432
433/// Profile - Gather unique data for the object.
434///
435void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
436  ID.AddInteger(getOffset());
437  ID.AddInteger(Size);
438  ID.AddPointer(getValue());
439  ID.AddInteger(Flags);
440}
441
442void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
443  // The Value and Offset may differ due to CSE. But the flags and size
444  // should be the same.
445  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
446  assert(MMO->getSize() == getSize() && "Size mismatch!");
447
448  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
449    // Update the alignment value.
450    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
451      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
452    // Also update the base and offset, because the new alignment may
453    // not be applicable with the old ones.
454    PtrInfo = MMO->PtrInfo;
455  }
456}
457
458/// getAlignment - Return the minimum known alignment in bytes of the
459/// actual memory reference.
460uint64_t MachineMemOperand::getAlignment() const {
461  return MinAlign(getBaseAlignment(), getOffset());
462}
463
464raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
465  assert((MMO.isLoad() || MMO.isStore()) &&
466         "SV has to be a load, store or both.");
467
468  if (MMO.isVolatile())
469    OS << "Volatile ";
470
471  if (MMO.isLoad())
472    OS << "LD";
473  if (MMO.isStore())
474    OS << "ST";
475  OS << MMO.getSize();
476
477  // Print the address information.
478  OS << "[";
479  if (!MMO.getValue())
480    OS << "<unknown>";
481  else
482    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
483
484  // If the alignment of the memory reference itself differs from the alignment
485  // of the base pointer, print the base alignment explicitly, next to the base
486  // pointer.
487  if (MMO.getBaseAlignment() != MMO.getAlignment())
488    OS << "(align=" << MMO.getBaseAlignment() << ")";
489
490  if (MMO.getOffset() != 0)
491    OS << "+" << MMO.getOffset();
492  OS << "]";
493
494  // Print the alignment of the reference.
495  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
496      MMO.getBaseAlignment() != MMO.getSize())
497    OS << "(align=" << MMO.getAlignment() << ")";
498
499  // Print TBAA info.
500  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
501    OS << "(tbaa=";
502    if (TBAAInfo->getNumOperands() > 0)
503      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
504    else
505      OS << "<unknown>";
506    OS << ")";
507  }
508
509  // Print nontemporal info.
510  if (MMO.isNonTemporal())
511    OS << "(nontemporal)";
512
513  return OS;
514}
515
516//===----------------------------------------------------------------------===//
517// MachineInstr Implementation
518//===----------------------------------------------------------------------===//
519
520void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
521  if (MCID->ImplicitDefs)
522    for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
523      addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
524  if (MCID->ImplicitUses)
525    for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
526      addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
527}
528
529/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
530/// implicit operands. It reserves space for the number of operands specified by
531/// the MCInstrDesc.
532MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
533                           const DebugLoc dl, bool NoImp)
534  : MCID(&tid), Parent(0), Operands(0), NumOperands(0),
535    Flags(0), AsmPrinterFlags(0),
536    NumMemRefs(0), MemRefs(0), debugLoc(dl) {
537  // Reserve space for the expected number of operands.
538  if (unsigned NumOps = MCID->getNumOperands() +
539    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
540    CapOperands = OperandCapacity::get(NumOps);
541    Operands = MF.allocateOperandArray(CapOperands);
542  }
543
544  if (!NoImp)
545    addImplicitDefUseOperands(MF);
546}
547
548/// MachineInstr ctor - Copies MachineInstr arg exactly
549///
550MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
551  : MCID(&MI.getDesc()), Parent(0), Operands(0), NumOperands(0),
552    Flags(0), AsmPrinterFlags(0),
553    NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
554    debugLoc(MI.getDebugLoc()) {
555  CapOperands = OperandCapacity::get(MI.getNumOperands());
556  Operands = MF.allocateOperandArray(CapOperands);
557
558  // Copy operands.
559  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
560    addOperand(MF, MI.getOperand(i));
561
562  // Copy all the sensible flags.
563  setFlags(MI.Flags);
564}
565
566/// getRegInfo - If this instruction is embedded into a MachineFunction,
567/// return the MachineRegisterInfo object for the current function, otherwise
568/// return null.
569MachineRegisterInfo *MachineInstr::getRegInfo() {
570  if (MachineBasicBlock *MBB = getParent())
571    return &MBB->getParent()->getRegInfo();
572  return 0;
573}
574
575/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
576/// this instruction from their respective use lists.  This requires that the
577/// operands already be on their use lists.
578void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
579  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
580    if (Operands[i].isReg())
581      MRI.removeRegOperandFromUseList(&Operands[i]);
582}
583
584/// AddRegOperandsToUseLists - Add all of the register operands in
585/// this instruction from their respective use lists.  This requires that the
586/// operands not be on their use lists yet.
587void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
588  for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
589    if (Operands[i].isReg())
590      MRI.addRegOperandToUseList(&Operands[i]);
591}
592
593void MachineInstr::addOperand(const MachineOperand &Op) {
594  MachineBasicBlock *MBB = getParent();
595  assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
596  MachineFunction *MF = MBB->getParent();
597  assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
598  addOperand(*MF, Op);
599}
600
601/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
602/// ranges. If MRI is non-null also update use-def chains.
603static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
604                         unsigned NumOps, MachineRegisterInfo *MRI) {
605  if (MRI)
606    return MRI->moveOperands(Dst, Src, NumOps);
607
608  // Here it would be convenient to call memmove, so that isn't allowed because
609  // MachineOperand has a constructor and so isn't a POD type.
610  if (Dst < Src)
611    for (unsigned i = 0; i != NumOps; ++i)
612      new (Dst + i) MachineOperand(Src[i]);
613  else
614    for (unsigned i = NumOps; i ; --i)
615      new (Dst + i - 1) MachineOperand(Src[i - 1]);
616}
617
618/// addOperand - Add the specified operand to the instruction.  If it is an
619/// implicit operand, it is added to the end of the operand list.  If it is
620/// an explicit operand it is added at the end of the explicit operand list
621/// (before the first implicit operand).
622void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
623  assert(MCID && "Cannot add operands before providing an instr descriptor");
624
625  // Check if we're adding one of our existing operands.
626  if (&Op >= Operands && &Op < Operands + NumOperands) {
627    // This is unusual: MI->addOperand(MI->getOperand(i)).
628    // If adding Op requires reallocating or moving existing operands around,
629    // the Op reference could go stale. Support it by copying Op.
630    MachineOperand CopyOp(Op);
631    return addOperand(MF, CopyOp);
632  }
633
634  // Find the insert location for the new operand.  Implicit registers go at
635  // the end, everything else goes before the implicit regs.
636  //
637  // FIXME: Allow mixed explicit and implicit operands on inline asm.
638  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
639  // implicit-defs, but they must not be moved around.  See the FIXME in
640  // InstrEmitter.cpp.
641  unsigned OpNo = getNumOperands();
642  bool isImpReg = Op.isReg() && Op.isImplicit();
643  if (!isImpReg && !isInlineAsm()) {
644    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
645      --OpNo;
646      assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
647    }
648  }
649
650  // OpNo now points as the desired insertion point.  Unless this is a variadic
651  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
652  // RegMask operands go between the explicit and implicit operands.
653  assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
654          OpNo < MCID->getNumOperands()) &&
655         "Trying to add an operand to a machine instr that is already done!");
656
657  MachineRegisterInfo *MRI = getRegInfo();
658
659  // Determine if the Operands array needs to be reallocated.
660  // Save the old capacity and operand array.
661  OperandCapacity OldCap = CapOperands;
662  MachineOperand *OldOperands = Operands;
663  if (!OldOperands || OldCap.getSize() == getNumOperands()) {
664    CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
665    Operands = MF.allocateOperandArray(CapOperands);
666    // Move the operands before the insertion point.
667    if (OpNo)
668      moveOperands(Operands, OldOperands, OpNo, MRI);
669  }
670
671  // Move the operands following the insertion point.
672  if (OpNo != NumOperands)
673    moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
674                 MRI);
675  ++NumOperands;
676
677  // Deallocate the old operand array.
678  if (OldOperands != Operands && OldOperands)
679    MF.deallocateOperandArray(OldCap, OldOperands);
680
681  // Copy Op into place. It still needs to be inserted into the MRI use lists.
682  MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
683  NewMO->ParentMI = this;
684
685  // When adding a register operand, tell MRI about it.
686  if (NewMO->isReg()) {
687    // Ensure isOnRegUseList() returns false, regardless of Op's status.
688    NewMO->Contents.Reg.Prev = 0;
689    // Ignore existing ties. This is not a property that can be copied.
690    NewMO->TiedTo = 0;
691    // Add the new operand to MRI, but only for instructions in an MBB.
692    if (MRI)
693      MRI->addRegOperandToUseList(NewMO);
694    // The MCID operand information isn't accurate until we start adding
695    // explicit operands. The implicit operands are added first, then the
696    // explicits are inserted before them.
697    if (!isImpReg) {
698      // Tie uses to defs as indicated in MCInstrDesc.
699      if (NewMO->isUse()) {
700        int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
701        if (DefIdx != -1)
702          tieOperands(DefIdx, OpNo);
703      }
704      // If the register operand is flagged as early, mark the operand as such.
705      if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
706        NewMO->setIsEarlyClobber(true);
707    }
708  }
709}
710
711/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
712/// fewer operand than it started with.
713///
714void MachineInstr::RemoveOperand(unsigned OpNo) {
715  assert(OpNo < getNumOperands() && "Invalid operand number");
716  untieRegOperand(OpNo);
717
718#ifndef NDEBUG
719  // Moving tied operands would break the ties.
720  for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
721    if (Operands[i].isReg())
722      assert(!Operands[i].isTied() && "Cannot move tied operands");
723#endif
724
725  MachineRegisterInfo *MRI = getRegInfo();
726  if (MRI && Operands[OpNo].isReg())
727    MRI->removeRegOperandFromUseList(Operands + OpNo);
728
729  // Don't call the MachineOperand destructor. A lot of this code depends on
730  // MachineOperand having a trivial destructor anyway, and adding a call here
731  // wouldn't make it 'destructor-correct'.
732
733  if (unsigned N = NumOperands - 1 - OpNo)
734    moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
735  --NumOperands;
736}
737
738/// addMemOperand - Add a MachineMemOperand to the machine instruction.
739/// This function should be used only occasionally. The setMemRefs function
740/// is the primary method for setting up a MachineInstr's MemRefs list.
741void MachineInstr::addMemOperand(MachineFunction &MF,
742                                 MachineMemOperand *MO) {
743  mmo_iterator OldMemRefs = MemRefs;
744  unsigned OldNumMemRefs = NumMemRefs;
745
746  unsigned NewNum = NumMemRefs + 1;
747  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
748
749  std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
750  NewMemRefs[NewNum - 1] = MO;
751  setMemRefs(NewMemRefs, NewMemRefs + NewNum);
752}
753
754bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
755  assert(!isBundledWithPred() && "Must be called on bundle header");
756  for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
757    if (MII->getDesc().getFlags() & Mask) {
758      if (Type == AnyInBundle)
759        return true;
760    } else {
761      if (Type == AllInBundle && !MII->isBundle())
762        return false;
763    }
764    // This was the last instruction in the bundle.
765    if (!MII->isBundledWithSucc())
766      return Type == AllInBundle;
767  }
768}
769
770bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
771                                 MICheckType Check) const {
772  // If opcodes or number of operands are not the same then the two
773  // instructions are obviously not identical.
774  if (Other->getOpcode() != getOpcode() ||
775      Other->getNumOperands() != getNumOperands())
776    return false;
777
778  if (isBundle()) {
779    // Both instructions are bundles, compare MIs inside the bundle.
780    MachineBasicBlock::const_instr_iterator I1 = *this;
781    MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
782    MachineBasicBlock::const_instr_iterator I2 = *Other;
783    MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
784    while (++I1 != E1 && I1->isInsideBundle()) {
785      ++I2;
786      if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
787        return false;
788    }
789  }
790
791  // Check operands to make sure they match.
792  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
793    const MachineOperand &MO = getOperand(i);
794    const MachineOperand &OMO = Other->getOperand(i);
795    if (!MO.isReg()) {
796      if (!MO.isIdenticalTo(OMO))
797        return false;
798      continue;
799    }
800
801    // Clients may or may not want to ignore defs when testing for equality.
802    // For example, machine CSE pass only cares about finding common
803    // subexpressions, so it's safe to ignore virtual register defs.
804    if (MO.isDef()) {
805      if (Check == IgnoreDefs)
806        continue;
807      else if (Check == IgnoreVRegDefs) {
808        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
809            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
810          if (MO.getReg() != OMO.getReg())
811            return false;
812      } else {
813        if (!MO.isIdenticalTo(OMO))
814          return false;
815        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
816          return false;
817      }
818    } else {
819      if (!MO.isIdenticalTo(OMO))
820        return false;
821      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
822        return false;
823    }
824  }
825  // If DebugLoc does not match then two dbg.values are not identical.
826  if (isDebugValue())
827    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
828        && getDebugLoc() != Other->getDebugLoc())
829      return false;
830  return true;
831}
832
833MachineInstr *MachineInstr::removeFromParent() {
834  assert(getParent() && "Not embedded in a basic block!");
835  return getParent()->remove(this);
836}
837
838MachineInstr *MachineInstr::removeFromBundle() {
839  assert(getParent() && "Not embedded in a basic block!");
840  return getParent()->remove_instr(this);
841}
842
843void MachineInstr::eraseFromParent() {
844  assert(getParent() && "Not embedded in a basic block!");
845  getParent()->erase(this);
846}
847
848void MachineInstr::eraseFromBundle() {
849  assert(getParent() && "Not embedded in a basic block!");
850  getParent()->erase_instr(this);
851}
852
853/// getNumExplicitOperands - Returns the number of non-implicit operands.
854///
855unsigned MachineInstr::getNumExplicitOperands() const {
856  unsigned NumOperands = MCID->getNumOperands();
857  if (!MCID->isVariadic())
858    return NumOperands;
859
860  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
861    const MachineOperand &MO = getOperand(i);
862    if (!MO.isReg() || !MO.isImplicit())
863      NumOperands++;
864  }
865  return NumOperands;
866}
867
868void MachineInstr::bundleWithPred() {
869  assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
870  setFlag(BundledPred);
871  MachineBasicBlock::instr_iterator Pred = this;
872  --Pred;
873  assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
874  Pred->setFlag(BundledSucc);
875}
876
877void MachineInstr::bundleWithSucc() {
878  assert(!isBundledWithSucc() && "MI is already bundled with its successor");
879  setFlag(BundledSucc);
880  MachineBasicBlock::instr_iterator Succ = this;
881  ++Succ;
882  assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
883  Succ->setFlag(BundledPred);
884}
885
886void MachineInstr::unbundleFromPred() {
887  assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
888  clearFlag(BundledPred);
889  MachineBasicBlock::instr_iterator Pred = this;
890  --Pred;
891  assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
892  Pred->clearFlag(BundledSucc);
893}
894
895void MachineInstr::unbundleFromSucc() {
896  assert(isBundledWithSucc() && "MI isn't bundled with its successor");
897  clearFlag(BundledSucc);
898  MachineBasicBlock::instr_iterator Succ = this;
899  ++Succ;
900  assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
901  Succ->clearFlag(BundledPred);
902}
903
904bool MachineInstr::isStackAligningInlineAsm() const {
905  if (isInlineAsm()) {
906    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
907    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
908      return true;
909  }
910  return false;
911}
912
913InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
914  assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
915  unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
916  return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
917}
918
919int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
920                                       unsigned *GroupNo) const {
921  assert(isInlineAsm() && "Expected an inline asm instruction");
922  assert(OpIdx < getNumOperands() && "OpIdx out of range");
923
924  // Ignore queries about the initial operands.
925  if (OpIdx < InlineAsm::MIOp_FirstOperand)
926    return -1;
927
928  unsigned Group = 0;
929  unsigned NumOps;
930  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
931       i += NumOps) {
932    const MachineOperand &FlagMO = getOperand(i);
933    // If we reach the implicit register operands, stop looking.
934    if (!FlagMO.isImm())
935      return -1;
936    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
937    if (i + NumOps > OpIdx) {
938      if (GroupNo)
939        *GroupNo = Group;
940      return i;
941    }
942    ++Group;
943  }
944  return -1;
945}
946
947const TargetRegisterClass*
948MachineInstr::getRegClassConstraint(unsigned OpIdx,
949                                    const TargetInstrInfo *TII,
950                                    const TargetRegisterInfo *TRI) const {
951  assert(getParent() && "Can't have an MBB reference here!");
952  assert(getParent()->getParent() && "Can't have an MF reference here!");
953  const MachineFunction &MF = *getParent()->getParent();
954
955  // Most opcodes have fixed constraints in their MCInstrDesc.
956  if (!isInlineAsm())
957    return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
958
959  if (!getOperand(OpIdx).isReg())
960    return NULL;
961
962  // For tied uses on inline asm, get the constraint from the def.
963  unsigned DefIdx;
964  if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
965    OpIdx = DefIdx;
966
967  // Inline asm stores register class constraints in the flag word.
968  int FlagIdx = findInlineAsmFlagIdx(OpIdx);
969  if (FlagIdx < 0)
970    return NULL;
971
972  unsigned Flag = getOperand(FlagIdx).getImm();
973  unsigned RCID;
974  if (InlineAsm::hasRegClassConstraint(Flag, RCID))
975    return TRI->getRegClass(RCID);
976
977  // Assume that all registers in a memory operand are pointers.
978  if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
979    return TRI->getPointerRegClass(MF);
980
981  return NULL;
982}
983
984/// Return the number of instructions inside the MI bundle, not counting the
985/// header instruction.
986unsigned MachineInstr::getBundleSize() const {
987  MachineBasicBlock::const_instr_iterator I = this;
988  unsigned Size = 0;
989  while (I->isBundledWithSucc())
990    ++Size, ++I;
991  return Size;
992}
993
994/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
995/// the specific register or -1 if it is not found. It further tightens
996/// the search criteria to a use that kills the register if isKill is true.
997int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
998                                          const TargetRegisterInfo *TRI) const {
999  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1000    const MachineOperand &MO = getOperand(i);
1001    if (!MO.isReg() || !MO.isUse())
1002      continue;
1003    unsigned MOReg = MO.getReg();
1004    if (!MOReg)
1005      continue;
1006    if (MOReg == Reg ||
1007        (TRI &&
1008         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1009         TargetRegisterInfo::isPhysicalRegister(Reg) &&
1010         TRI->isSubRegister(MOReg, Reg)))
1011      if (!isKill || MO.isKill())
1012        return i;
1013  }
1014  return -1;
1015}
1016
1017/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1018/// indicating if this instruction reads or writes Reg. This also considers
1019/// partial defines.
1020std::pair<bool,bool>
1021MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1022                                         SmallVectorImpl<unsigned> *Ops) const {
1023  bool PartDef = false; // Partial redefine.
1024  bool FullDef = false; // Full define.
1025  bool Use = false;
1026
1027  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1028    const MachineOperand &MO = getOperand(i);
1029    if (!MO.isReg() || MO.getReg() != Reg)
1030      continue;
1031    if (Ops)
1032      Ops->push_back(i);
1033    if (MO.isUse())
1034      Use |= !MO.isUndef();
1035    else if (MO.getSubReg() && !MO.isUndef())
1036      // A partial <def,undef> doesn't count as reading the register.
1037      PartDef = true;
1038    else
1039      FullDef = true;
1040  }
1041  // A partial redefine uses Reg unless there is also a full define.
1042  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1043}
1044
1045/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1046/// the specified register or -1 if it is not found. If isDead is true, defs
1047/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1048/// also checks if there is a def of a super-register.
1049int
1050MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1051                                        const TargetRegisterInfo *TRI) const {
1052  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1053  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1054    const MachineOperand &MO = getOperand(i);
1055    // Accept regmask operands when Overlap is set.
1056    // Ignore them when looking for a specific def operand (Overlap == false).
1057    if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1058      return i;
1059    if (!MO.isReg() || !MO.isDef())
1060      continue;
1061    unsigned MOReg = MO.getReg();
1062    bool Found = (MOReg == Reg);
1063    if (!Found && TRI && isPhys &&
1064        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1065      if (Overlap)
1066        Found = TRI->regsOverlap(MOReg, Reg);
1067      else
1068        Found = TRI->isSubRegister(MOReg, Reg);
1069    }
1070    if (Found && (!isDead || MO.isDead()))
1071      return i;
1072  }
1073  return -1;
1074}
1075
1076/// findFirstPredOperandIdx() - Find the index of the first operand in the
1077/// operand list that is used to represent the predicate. It returns -1 if
1078/// none is found.
1079int MachineInstr::findFirstPredOperandIdx() const {
1080  // Don't call MCID.findFirstPredOperandIdx() because this variant
1081  // is sometimes called on an instruction that's not yet complete, and
1082  // so the number of operands is less than the MCID indicates. In
1083  // particular, the PTX target does this.
1084  const MCInstrDesc &MCID = getDesc();
1085  if (MCID.isPredicable()) {
1086    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1087      if (MCID.OpInfo[i].isPredicate())
1088        return i;
1089  }
1090
1091  return -1;
1092}
1093
1094// MachineOperand::TiedTo is 4 bits wide.
1095const unsigned TiedMax = 15;
1096
1097/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1098///
1099/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1100/// field. TiedTo can have these values:
1101///
1102/// 0:              Operand is not tied to anything.
1103/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1104/// TiedMax:        Tied to an operand >= TiedMax-1.
1105///
1106/// The tied def must be one of the first TiedMax operands on a normal
1107/// instruction. INLINEASM instructions allow more tied defs.
1108///
1109void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1110  MachineOperand &DefMO = getOperand(DefIdx);
1111  MachineOperand &UseMO = getOperand(UseIdx);
1112  assert(DefMO.isDef() && "DefIdx must be a def operand");
1113  assert(UseMO.isUse() && "UseIdx must be a use operand");
1114  assert(!DefMO.isTied() && "Def is already tied to another use");
1115  assert(!UseMO.isTied() && "Use is already tied to another def");
1116
1117  if (DefIdx < TiedMax)
1118    UseMO.TiedTo = DefIdx + 1;
1119  else {
1120    // Inline asm can use the group descriptors to find tied operands, but on
1121    // normal instruction, the tied def must be within the first TiedMax
1122    // operands.
1123    assert(isInlineAsm() && "DefIdx out of range");
1124    UseMO.TiedTo = TiedMax;
1125  }
1126
1127  // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1128  DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1129}
1130
1131/// Given the index of a tied register operand, find the operand it is tied to.
1132/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1133/// which must exist.
1134unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1135  const MachineOperand &MO = getOperand(OpIdx);
1136  assert(MO.isTied() && "Operand isn't tied");
1137
1138  // Normally TiedTo is in range.
1139  if (MO.TiedTo < TiedMax)
1140    return MO.TiedTo - 1;
1141
1142  // Uses on normal instructions can be out of range.
1143  if (!isInlineAsm()) {
1144    // Normal tied defs must be in the 0..TiedMax-1 range.
1145    if (MO.isUse())
1146      return TiedMax - 1;
1147    // MO is a def. Search for the tied use.
1148    for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1149      const MachineOperand &UseMO = getOperand(i);
1150      if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1151        return i;
1152    }
1153    llvm_unreachable("Can't find tied use");
1154  }
1155
1156  // Now deal with inline asm by parsing the operand group descriptor flags.
1157  // Find the beginning of each operand group.
1158  SmallVector<unsigned, 8> GroupIdx;
1159  unsigned OpIdxGroup = ~0u;
1160  unsigned NumOps;
1161  for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1162       i += NumOps) {
1163    const MachineOperand &FlagMO = getOperand(i);
1164    assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1165    unsigned CurGroup = GroupIdx.size();
1166    GroupIdx.push_back(i);
1167    NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1168    // OpIdx belongs to this operand group.
1169    if (OpIdx > i && OpIdx < i + NumOps)
1170      OpIdxGroup = CurGroup;
1171    unsigned TiedGroup;
1172    if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1173      continue;
1174    // Operands in this group are tied to operands in TiedGroup which must be
1175    // earlier. Find the number of operands between the two groups.
1176    unsigned Delta = i - GroupIdx[TiedGroup];
1177
1178    // OpIdx is a use tied to TiedGroup.
1179    if (OpIdxGroup == CurGroup)
1180      return OpIdx - Delta;
1181
1182    // OpIdx is a def tied to this use group.
1183    if (OpIdxGroup == TiedGroup)
1184      return OpIdx + Delta;
1185  }
1186  llvm_unreachable("Invalid tied operand on inline asm");
1187}
1188
1189/// clearKillInfo - Clears kill flags on all operands.
1190///
1191void MachineInstr::clearKillInfo() {
1192  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1193    MachineOperand &MO = getOperand(i);
1194    if (MO.isReg() && MO.isUse())
1195      MO.setIsKill(false);
1196  }
1197}
1198
1199void MachineInstr::substituteRegister(unsigned FromReg,
1200                                      unsigned ToReg,
1201                                      unsigned SubIdx,
1202                                      const TargetRegisterInfo &RegInfo) {
1203  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1204    if (SubIdx)
1205      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1206    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1207      MachineOperand &MO = getOperand(i);
1208      if (!MO.isReg() || MO.getReg() != FromReg)
1209        continue;
1210      MO.substPhysReg(ToReg, RegInfo);
1211    }
1212  } else {
1213    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1214      MachineOperand &MO = getOperand(i);
1215      if (!MO.isReg() || MO.getReg() != FromReg)
1216        continue;
1217      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1218    }
1219  }
1220}
1221
1222/// isSafeToMove - Return true if it is safe to move this instruction. If
1223/// SawStore is set to true, it means that there is a store (or call) between
1224/// the instruction's location and its intended destination.
1225bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1226                                AliasAnalysis *AA,
1227                                bool &SawStore) const {
1228  // Ignore stuff that we obviously can't move.
1229  //
1230  // Treat volatile loads as stores. This is not strictly necessary for
1231  // volatiles, but it is required for atomic loads. It is not allowed to move
1232  // a load across an atomic load with Ordering > Monotonic.
1233  if (mayStore() || isCall() ||
1234      (mayLoad() && hasOrderedMemoryRef())) {
1235    SawStore = true;
1236    return false;
1237  }
1238
1239  if (isLabel() || isDebugValue() ||
1240      isTerminator() || hasUnmodeledSideEffects())
1241    return false;
1242
1243  // See if this instruction does a load.  If so, we have to guarantee that the
1244  // loaded value doesn't change between the load and the its intended
1245  // destination. The check for isInvariantLoad gives the targe the chance to
1246  // classify the load as always returning a constant, e.g. a constant pool
1247  // load.
1248  if (mayLoad() && !isInvariantLoad(AA))
1249    // Otherwise, this is a real load.  If there is a store between the load and
1250    // end of block, we can't move it.
1251    return !SawStore;
1252
1253  return true;
1254}
1255
1256/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1257/// instruction which defined the specified register instead of copying it.
1258bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1259                                 AliasAnalysis *AA,
1260                                 unsigned DstReg) const {
1261  bool SawStore = false;
1262  if (!TII->isTriviallyReMaterializable(this, AA) ||
1263      !isSafeToMove(TII, AA, SawStore))
1264    return false;
1265  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1266    const MachineOperand &MO = getOperand(i);
1267    if (!MO.isReg())
1268      continue;
1269    // FIXME: For now, do not remat any instruction with register operands.
1270    // Later on, we can loosen the restriction is the register operands have
1271    // not been modified between the def and use. Note, this is different from
1272    // MachineSink because the code is no longer in two-address form (at least
1273    // partially).
1274    if (MO.isUse())
1275      return false;
1276    else if (!MO.isDead() && MO.getReg() != DstReg)
1277      return false;
1278  }
1279  return true;
1280}
1281
1282/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1283/// or volatile memory reference, or if the information describing the memory
1284/// reference is not available. Return false if it is known to have no ordered
1285/// memory references.
1286bool MachineInstr::hasOrderedMemoryRef() const {
1287  // An instruction known never to access memory won't have a volatile access.
1288  if (!mayStore() &&
1289      !mayLoad() &&
1290      !isCall() &&
1291      !hasUnmodeledSideEffects())
1292    return false;
1293
1294  // Otherwise, if the instruction has no memory reference information,
1295  // conservatively assume it wasn't preserved.
1296  if (memoperands_empty())
1297    return true;
1298
1299  // Check the memory reference information for ordered references.
1300  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1301    if (!(*I)->isUnordered())
1302      return true;
1303
1304  return false;
1305}
1306
1307/// isInvariantLoad - Return true if this instruction is loading from a
1308/// location whose value is invariant across the function.  For example,
1309/// loading a value from the constant pool or from the argument area
1310/// of a function if it does not change.  This should only return true of
1311/// *all* loads the instruction does are invariant (if it does multiple loads).
1312bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1313  // If the instruction doesn't load at all, it isn't an invariant load.
1314  if (!mayLoad())
1315    return false;
1316
1317  // If the instruction has lost its memoperands, conservatively assume that
1318  // it may not be an invariant load.
1319  if (memoperands_empty())
1320    return false;
1321
1322  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1323
1324  for (mmo_iterator I = memoperands_begin(),
1325       E = memoperands_end(); I != E; ++I) {
1326    if ((*I)->isVolatile()) return false;
1327    if ((*I)->isStore()) return false;
1328    if ((*I)->isInvariant()) return true;
1329
1330    if (const Value *V = (*I)->getValue()) {
1331      // A load from a constant PseudoSourceValue is invariant.
1332      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1333        if (PSV->isConstant(MFI))
1334          continue;
1335      // If we have an AliasAnalysis, ask it whether the memory is constant.
1336      if (AA && AA->pointsToConstantMemory(
1337                      AliasAnalysis::Location(V, (*I)->getSize(),
1338                                              (*I)->getTBAAInfo())))
1339        continue;
1340    }
1341
1342    // Otherwise assume conservatively.
1343    return false;
1344  }
1345
1346  // Everything checks out.
1347  return true;
1348}
1349
1350/// isConstantValuePHI - If the specified instruction is a PHI that always
1351/// merges together the same virtual register, return the register, otherwise
1352/// return 0.
1353unsigned MachineInstr::isConstantValuePHI() const {
1354  if (!isPHI())
1355    return 0;
1356  assert(getNumOperands() >= 3 &&
1357         "It's illegal to have a PHI without source operands");
1358
1359  unsigned Reg = getOperand(1).getReg();
1360  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1361    if (getOperand(i).getReg() != Reg)
1362      return 0;
1363  return Reg;
1364}
1365
1366bool MachineInstr::hasUnmodeledSideEffects() const {
1367  if (hasProperty(MCID::UnmodeledSideEffects))
1368    return true;
1369  if (isInlineAsm()) {
1370    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1371    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1372      return true;
1373  }
1374
1375  return false;
1376}
1377
1378/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1379///
1380bool MachineInstr::allDefsAreDead() const {
1381  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1382    const MachineOperand &MO = getOperand(i);
1383    if (!MO.isReg() || MO.isUse())
1384      continue;
1385    if (!MO.isDead())
1386      return false;
1387  }
1388  return true;
1389}
1390
1391/// copyImplicitOps - Copy implicit register operands from specified
1392/// instruction to this instruction.
1393void MachineInstr::copyImplicitOps(MachineFunction &MF,
1394                                   const MachineInstr *MI) {
1395  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1396       i != e; ++i) {
1397    const MachineOperand &MO = MI->getOperand(i);
1398    if (MO.isReg() && MO.isImplicit())
1399      addOperand(MF, MO);
1400  }
1401}
1402
1403void MachineInstr::dump() const {
1404#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1405  dbgs() << "  " << *this;
1406#endif
1407}
1408
1409static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1410                         raw_ostream &CommentOS) {
1411  const LLVMContext &Ctx = MF->getFunction()->getContext();
1412  if (!DL.isUnknown()) {          // Print source line info.
1413    DIScope Scope(DL.getScope(Ctx));
1414    // Omit the directory, because it's likely to be long and uninteresting.
1415    if (Scope.Verify())
1416      CommentOS << Scope.getFilename();
1417    else
1418      CommentOS << "<unknown>";
1419    CommentOS << ':' << DL.getLine();
1420    if (DL.getCol() != 0)
1421      CommentOS << ':' << DL.getCol();
1422    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1423    if (!InlinedAtDL.isUnknown()) {
1424      CommentOS << " @[ ";
1425      printDebugLoc(InlinedAtDL, MF, CommentOS);
1426      CommentOS << " ]";
1427    }
1428  }
1429}
1430
1431void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM,
1432                         bool SkipOpers) const {
1433  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1434  const MachineFunction *MF = 0;
1435  const MachineRegisterInfo *MRI = 0;
1436  if (const MachineBasicBlock *MBB = getParent()) {
1437    MF = MBB->getParent();
1438    if (!TM && MF)
1439      TM = &MF->getTarget();
1440    if (MF)
1441      MRI = &MF->getRegInfo();
1442  }
1443
1444  // Save a list of virtual registers.
1445  SmallVector<unsigned, 8> VirtRegs;
1446
1447  // Print explicitly defined operands on the left of an assignment syntax.
1448  unsigned StartOp = 0, e = getNumOperands();
1449  for (; StartOp < e && getOperand(StartOp).isReg() &&
1450         getOperand(StartOp).isDef() &&
1451         !getOperand(StartOp).isImplicit();
1452       ++StartOp) {
1453    if (StartOp != 0) OS << ", ";
1454    getOperand(StartOp).print(OS, TM);
1455    unsigned Reg = getOperand(StartOp).getReg();
1456    if (TargetRegisterInfo::isVirtualRegister(Reg))
1457      VirtRegs.push_back(Reg);
1458  }
1459
1460  if (StartOp != 0)
1461    OS << " = ";
1462
1463  // Print the opcode name.
1464  if (TM && TM->getInstrInfo())
1465    OS << TM->getInstrInfo()->getName(getOpcode());
1466  else
1467    OS << "UNKNOWN";
1468
1469  if (SkipOpers)
1470    return;
1471
1472  // Print the rest of the operands.
1473  bool OmittedAnyCallClobbers = false;
1474  bool FirstOp = true;
1475  unsigned AsmDescOp = ~0u;
1476  unsigned AsmOpCount = 0;
1477
1478  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1479    // Print asm string.
1480    OS << " ";
1481    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1482
1483    // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1484    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1485    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1486      OS << " [sideeffect]";
1487    if (ExtraInfo & InlineAsm::Extra_MayLoad)
1488      OS << " [mayload]";
1489    if (ExtraInfo & InlineAsm::Extra_MayStore)
1490      OS << " [maystore]";
1491    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1492      OS << " [alignstack]";
1493    if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1494      OS << " [attdialect]";
1495    if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1496      OS << " [inteldialect]";
1497
1498    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1499    FirstOp = false;
1500  }
1501
1502
1503  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1504    const MachineOperand &MO = getOperand(i);
1505
1506    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1507      VirtRegs.push_back(MO.getReg());
1508
1509    // Omit call-clobbered registers which aren't used anywhere. This makes
1510    // call instructions much less noisy on targets where calls clobber lots
1511    // of registers. Don't rely on MO.isDead() because we may be called before
1512    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1513    if (MF && isCall() &&
1514        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1515      unsigned Reg = MO.getReg();
1516      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1517        const MachineRegisterInfo &MRI = MF->getRegInfo();
1518        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1519          bool HasAliasLive = false;
1520          for (MCRegAliasIterator AI(Reg, TM->getRegisterInfo(), true);
1521               AI.isValid(); ++AI) {
1522            unsigned AliasReg = *AI;
1523            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1524              HasAliasLive = true;
1525              break;
1526            }
1527          }
1528          if (!HasAliasLive) {
1529            OmittedAnyCallClobbers = true;
1530            continue;
1531          }
1532        }
1533      }
1534    }
1535
1536    if (FirstOp) FirstOp = false; else OS << ",";
1537    OS << " ";
1538    if (i < getDesc().NumOperands) {
1539      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1540      if (MCOI.isPredicate())
1541        OS << "pred:";
1542      if (MCOI.isOptionalDef())
1543        OS << "opt:";
1544    }
1545    if (isDebugValue() && MO.isMetadata()) {
1546      // Pretty print DBG_VALUE instructions.
1547      const MDNode *MD = MO.getMetadata();
1548      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1549        OS << "!\"" << MDS->getString() << '\"';
1550      else
1551        MO.print(OS, TM);
1552    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1553      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1554    } else if (i == AsmDescOp && MO.isImm()) {
1555      // Pretty print the inline asm operand descriptor.
1556      OS << '$' << AsmOpCount++;
1557      unsigned Flag = MO.getImm();
1558      switch (InlineAsm::getKind(Flag)) {
1559      case InlineAsm::Kind_RegUse:             OS << ":[reguse"; break;
1560      case InlineAsm::Kind_RegDef:             OS << ":[regdef"; break;
1561      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1562      case InlineAsm::Kind_Clobber:            OS << ":[clobber"; break;
1563      case InlineAsm::Kind_Imm:                OS << ":[imm"; break;
1564      case InlineAsm::Kind_Mem:                OS << ":[mem"; break;
1565      default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1566      }
1567
1568      unsigned RCID = 0;
1569      if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1570        if (TM)
1571          OS << ':' << TM->getRegisterInfo()->getRegClass(RCID)->getName();
1572        else
1573          OS << ":RC" << RCID;
1574      }
1575
1576      unsigned TiedTo = 0;
1577      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1578        OS << " tiedto:$" << TiedTo;
1579
1580      OS << ']';
1581
1582      // Compute the index of the next operand descriptor.
1583      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1584    } else
1585      MO.print(OS, TM);
1586  }
1587
1588  // Briefly indicate whether any call clobbers were omitted.
1589  if (OmittedAnyCallClobbers) {
1590    if (!FirstOp) OS << ",";
1591    OS << " ...";
1592  }
1593
1594  bool HaveSemi = false;
1595  const unsigned PrintableFlags = FrameSetup;
1596  if (Flags & PrintableFlags) {
1597    if (!HaveSemi) OS << ";"; HaveSemi = true;
1598    OS << " flags: ";
1599
1600    if (Flags & FrameSetup)
1601      OS << "FrameSetup";
1602  }
1603
1604  if (!memoperands_empty()) {
1605    if (!HaveSemi) OS << ";"; HaveSemi = true;
1606
1607    OS << " mem:";
1608    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1609         i != e; ++i) {
1610      OS << **i;
1611      if (llvm::next(i) != e)
1612        OS << " ";
1613    }
1614  }
1615
1616  // Print the regclass of any virtual registers encountered.
1617  if (MRI && !VirtRegs.empty()) {
1618    if (!HaveSemi) OS << ";"; HaveSemi = true;
1619    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1620      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1621      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1622      for (unsigned j = i+1; j != VirtRegs.size();) {
1623        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1624          ++j;
1625          continue;
1626        }
1627        if (VirtRegs[i] != VirtRegs[j])
1628          OS << "," << PrintReg(VirtRegs[j]);
1629        VirtRegs.erase(VirtRegs.begin()+j);
1630      }
1631    }
1632  }
1633
1634  // Print debug location information.
1635  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1636    if (!HaveSemi) OS << ";"; HaveSemi = true;
1637    DIVariable DV(getOperand(e - 1).getMetadata());
1638    OS << " line no:" <<  DV.getLineNumber();
1639    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1640      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1641      if (!InlinedAtDL.isUnknown()) {
1642        OS << " inlined @[ ";
1643        printDebugLoc(InlinedAtDL, MF, OS);
1644        OS << " ]";
1645      }
1646    }
1647  } else if (!debugLoc.isUnknown() && MF) {
1648    if (!HaveSemi) OS << ";"; HaveSemi = true;
1649    OS << " dbg:";
1650    printDebugLoc(debugLoc, MF, OS);
1651  }
1652
1653  OS << '\n';
1654}
1655
1656bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1657                                     const TargetRegisterInfo *RegInfo,
1658                                     bool AddIfNotFound) {
1659  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1660  bool hasAliases = isPhysReg &&
1661    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1662  bool Found = false;
1663  SmallVector<unsigned,4> DeadOps;
1664  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1665    MachineOperand &MO = getOperand(i);
1666    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1667      continue;
1668    unsigned Reg = MO.getReg();
1669    if (!Reg)
1670      continue;
1671
1672    if (Reg == IncomingReg) {
1673      if (!Found) {
1674        if (MO.isKill())
1675          // The register is already marked kill.
1676          return true;
1677        if (isPhysReg && isRegTiedToDefOperand(i))
1678          // Two-address uses of physregs must not be marked kill.
1679          return true;
1680        MO.setIsKill();
1681        Found = true;
1682      }
1683    } else if (hasAliases && MO.isKill() &&
1684               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1685      // A super-register kill already exists.
1686      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1687        return true;
1688      if (RegInfo->isSubRegister(IncomingReg, Reg))
1689        DeadOps.push_back(i);
1690    }
1691  }
1692
1693  // Trim unneeded kill operands.
1694  while (!DeadOps.empty()) {
1695    unsigned OpIdx = DeadOps.back();
1696    if (getOperand(OpIdx).isImplicit())
1697      RemoveOperand(OpIdx);
1698    else
1699      getOperand(OpIdx).setIsKill(false);
1700    DeadOps.pop_back();
1701  }
1702
1703  // If not found, this means an alias of one of the operands is killed. Add a
1704  // new implicit operand if required.
1705  if (!Found && AddIfNotFound) {
1706    addOperand(MachineOperand::CreateReg(IncomingReg,
1707                                         false /*IsDef*/,
1708                                         true  /*IsImp*/,
1709                                         true  /*IsKill*/));
1710    return true;
1711  }
1712  return Found;
1713}
1714
1715void MachineInstr::clearRegisterKills(unsigned Reg,
1716                                      const TargetRegisterInfo *RegInfo) {
1717  if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1718    RegInfo = 0;
1719  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1720    MachineOperand &MO = getOperand(i);
1721    if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1722      continue;
1723    unsigned OpReg = MO.getReg();
1724    if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1725      MO.setIsKill(false);
1726  }
1727}
1728
1729bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1730                                   const TargetRegisterInfo *RegInfo,
1731                                   bool AddIfNotFound) {
1732  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1733  bool hasAliases = isPhysReg &&
1734    MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1735  bool Found = false;
1736  SmallVector<unsigned,4> DeadOps;
1737  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1738    MachineOperand &MO = getOperand(i);
1739    if (!MO.isReg() || !MO.isDef())
1740      continue;
1741    unsigned Reg = MO.getReg();
1742    if (!Reg)
1743      continue;
1744
1745    if (Reg == IncomingReg) {
1746      MO.setIsDead();
1747      Found = true;
1748    } else if (hasAliases && MO.isDead() &&
1749               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1750      // There exists a super-register that's marked dead.
1751      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1752        return true;
1753      if (RegInfo->isSubRegister(IncomingReg, Reg))
1754        DeadOps.push_back(i);
1755    }
1756  }
1757
1758  // Trim unneeded dead operands.
1759  while (!DeadOps.empty()) {
1760    unsigned OpIdx = DeadOps.back();
1761    if (getOperand(OpIdx).isImplicit())
1762      RemoveOperand(OpIdx);
1763    else
1764      getOperand(OpIdx).setIsDead(false);
1765    DeadOps.pop_back();
1766  }
1767
1768  // If not found, this means an alias of one of the operands is dead. Add a
1769  // new implicit operand if required.
1770  if (Found || !AddIfNotFound)
1771    return Found;
1772
1773  addOperand(MachineOperand::CreateReg(IncomingReg,
1774                                       true  /*IsDef*/,
1775                                       true  /*IsImp*/,
1776                                       false /*IsKill*/,
1777                                       true  /*IsDead*/));
1778  return true;
1779}
1780
1781void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1782                                      const TargetRegisterInfo *RegInfo) {
1783  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1784    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1785    if (MO)
1786      return;
1787  } else {
1788    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1789      const MachineOperand &MO = getOperand(i);
1790      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1791          MO.getSubReg() == 0)
1792        return;
1793    }
1794  }
1795  addOperand(MachineOperand::CreateReg(IncomingReg,
1796                                       true  /*IsDef*/,
1797                                       true  /*IsImp*/));
1798}
1799
1800void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1801                                         const TargetRegisterInfo &TRI) {
1802  bool HasRegMask = false;
1803  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1804    MachineOperand &MO = getOperand(i);
1805    if (MO.isRegMask()) {
1806      HasRegMask = true;
1807      continue;
1808    }
1809    if (!MO.isReg() || !MO.isDef()) continue;
1810    unsigned Reg = MO.getReg();
1811    if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1812    bool Dead = true;
1813    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1814         I != E; ++I)
1815      if (TRI.regsOverlap(*I, Reg)) {
1816        Dead = false;
1817        break;
1818      }
1819    // If there are no uses, including partial uses, the def is dead.
1820    if (Dead) MO.setIsDead();
1821  }
1822
1823  // This is a call with a register mask operand.
1824  // Mask clobbers are always dead, so add defs for the non-dead defines.
1825  if (HasRegMask)
1826    for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1827         I != E; ++I)
1828      addRegisterDefined(*I, &TRI);
1829}
1830
1831unsigned
1832MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1833  // Build up a buffer of hash code components.
1834  SmallVector<size_t, 8> HashComponents;
1835  HashComponents.reserve(MI->getNumOperands() + 1);
1836  HashComponents.push_back(MI->getOpcode());
1837  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1838    const MachineOperand &MO = MI->getOperand(i);
1839    if (MO.isReg() && MO.isDef() &&
1840        TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1841      continue;  // Skip virtual register defs.
1842
1843    HashComponents.push_back(hash_value(MO));
1844  }
1845  return hash_combine_range(HashComponents.begin(), HashComponents.end());
1846}
1847
1848void MachineInstr::emitError(StringRef Msg) const {
1849  // Find the source location cookie.
1850  unsigned LocCookie = 0;
1851  const MDNode *LocMD = 0;
1852  for (unsigned i = getNumOperands(); i != 0; --i) {
1853    if (getOperand(i-1).isMetadata() &&
1854        (LocMD = getOperand(i-1).getMetadata()) &&
1855        LocMD->getNumOperands() != 0) {
1856      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1857        LocCookie = CI->getZExtValue();
1858        break;
1859      }
1860    }
1861  }
1862
1863  if (const MachineBasicBlock *MBB = getParent())
1864    if (const MachineFunction *MF = MBB->getParent())
1865      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1866  report_fatal_error(Msg);
1867}
1868