MachineInstr.cpp revision cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Constants.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/Value.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
19#include "llvm/CodeGen/PseudoSourceValue.h"
20#include "llvm/Target/TargetMachine.h"
21#include "llvm/Target/TargetInstrInfo.h"
22#include "llvm/Target/TargetInstrDesc.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Support/LeakDetector.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/Streams.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/ADT/FoldingSet.h"
29#include <ostream>
30using namespace llvm;
31
32//===----------------------------------------------------------------------===//
33// MachineOperand Implementation
34//===----------------------------------------------------------------------===//
35
36/// AddRegOperandToRegInfo - Add this register operand to the specified
37/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
38/// explicitly nulled out.
39void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
40  assert(isReg() && "Can only add reg operand to use lists");
41
42  // If the reginfo pointer is null, just explicitly null out or next/prev
43  // pointers, to ensure they are not garbage.
44  if (RegInfo == 0) {
45    Contents.Reg.Prev = 0;
46    Contents.Reg.Next = 0;
47    return;
48  }
49
50  // Otherwise, add this operand to the head of the registers use/def list.
51  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
52
53  // For SSA values, we prefer to keep the definition at the start of the list.
54  // we do this by skipping over the definition if it is at the head of the
55  // list.
56  if (*Head && (*Head)->isDef())
57    Head = &(*Head)->Contents.Reg.Next;
58
59  Contents.Reg.Next = *Head;
60  if (Contents.Reg.Next) {
61    assert(getReg() == Contents.Reg.Next->getReg() &&
62           "Different regs on the same list!");
63    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
64  }
65
66  Contents.Reg.Prev = Head;
67  *Head = this;
68}
69
70void MachineOperand::setReg(unsigned Reg) {
71  if (getReg() == Reg) return; // No change.
72
73  // Otherwise, we have to change the register.  If this operand is embedded
74  // into a machine function, we need to update the old and new register's
75  // use/def lists.
76  if (MachineInstr *MI = getParent())
77    if (MachineBasicBlock *MBB = MI->getParent())
78      if (MachineFunction *MF = MBB->getParent()) {
79        RemoveRegOperandFromRegInfo();
80        Contents.Reg.RegNo = Reg;
81        AddRegOperandToRegInfo(&MF->getRegInfo());
82        return;
83      }
84
85  // Otherwise, just change the register, no problem.  :)
86  Contents.Reg.RegNo = Reg;
87}
88
89/// ChangeToImmediate - Replace this operand with a new immediate operand of
90/// the specified value.  If an operand is known to be an immediate already,
91/// the setImm method should be used.
92void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
93  // If this operand is currently a register operand, and if this is in a
94  // function, deregister the operand from the register's use/def list.
95  if (isReg() && getParent() && getParent()->getParent() &&
96      getParent()->getParent()->getParent())
97    RemoveRegOperandFromRegInfo();
98
99  OpKind = MO_Immediate;
100  Contents.ImmVal = ImmVal;
101}
102
103/// ChangeToRegister - Replace this operand with a new register operand of
104/// the specified value.  If an operand is known to be an register already,
105/// the setReg method should be used.
106void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
107                                      bool isKill, bool isDead) {
108  // If this operand is already a register operand, use setReg to update the
109  // register's use/def lists.
110  if (isReg()) {
111    assert(!isEarlyClobber());
112    setReg(Reg);
113  } else {
114    // Otherwise, change this to a register and set the reg#.
115    OpKind = MO_Register;
116    Contents.Reg.RegNo = Reg;
117
118    // If this operand is embedded in a function, add the operand to the
119    // register's use/def list.
120    if (MachineInstr *MI = getParent())
121      if (MachineBasicBlock *MBB = MI->getParent())
122        if (MachineFunction *MF = MBB->getParent())
123          AddRegOperandToRegInfo(&MF->getRegInfo());
124  }
125
126  IsDef = isDef;
127  IsImp = isImp;
128  IsKill = isKill;
129  IsDead = isDead;
130  IsEarlyClobber = false;
131  SubReg = 0;
132}
133
134/// isIdenticalTo - Return true if this operand is identical to the specified
135/// operand.
136bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
137  if (getType() != Other.getType()) return false;
138
139  switch (getType()) {
140  default: assert(0 && "Unrecognized operand type");
141  case MachineOperand::MO_Register:
142    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
143           getSubReg() == Other.getSubReg();
144  case MachineOperand::MO_Immediate:
145    return getImm() == Other.getImm();
146  case MachineOperand::MO_FPImmediate:
147    return getFPImm() == Other.getFPImm();
148  case MachineOperand::MO_MachineBasicBlock:
149    return getMBB() == Other.getMBB();
150  case MachineOperand::MO_FrameIndex:
151    return getIndex() == Other.getIndex();
152  case MachineOperand::MO_ConstantPoolIndex:
153    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
154  case MachineOperand::MO_JumpTableIndex:
155    return getIndex() == Other.getIndex();
156  case MachineOperand::MO_GlobalAddress:
157    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
158  case MachineOperand::MO_ExternalSymbol:
159    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
160           getOffset() == Other.getOffset();
161  }
162}
163
164/// print - Print the specified machine operand.
165///
166void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
167  raw_os_ostream RawOS(OS);
168  print(RawOS, TM);
169}
170
171void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
172  switch (getType()) {
173  case MachineOperand::MO_Register:
174    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
175      OS << "%reg" << getReg();
176    } else {
177      // If the instruction is embedded into a basic block, we can find the
178      // target info for the instruction.
179      if (TM == 0)
180        if (const MachineInstr *MI = getParent())
181          if (const MachineBasicBlock *MBB = MI->getParent())
182            if (const MachineFunction *MF = MBB->getParent())
183              TM = &MF->getTarget();
184
185      if (TM)
186        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
187      else
188        OS << "%mreg" << getReg();
189    }
190
191    if (isDef() || isKill() || isDead() || isImplicit() || isEarlyClobber()) {
192      OS << "<";
193      bool NeedComma = false;
194      if (isImplicit()) {
195        if (NeedComma) OS << ",";
196        OS << (isDef() ? "imp-def" : "imp-use");
197        NeedComma = true;
198      } else if (isDef()) {
199        if (NeedComma) OS << ",";
200        if (isEarlyClobber())
201          OS << "earlyclobber,";
202        OS << "def";
203        NeedComma = true;
204      }
205      if (isKill() || isDead()) {
206        if (NeedComma) OS << ",";
207        if (isKill())  OS << "kill";
208        if (isDead())  OS << "dead";
209      }
210      OS << ">";
211    }
212    break;
213  case MachineOperand::MO_Immediate:
214    OS << getImm();
215    break;
216  case MachineOperand::MO_FPImmediate:
217    if (getFPImm()->getType() == Type::FloatTy) {
218      OS << getFPImm()->getValueAPF().convertToFloat();
219    } else {
220      OS << getFPImm()->getValueAPF().convertToDouble();
221    }
222    break;
223  case MachineOperand::MO_MachineBasicBlock:
224    OS << "mbb<"
225       << ((Value*)getMBB()->getBasicBlock())->getName()
226       << "," << (void*)getMBB() << ">";
227    break;
228  case MachineOperand::MO_FrameIndex:
229    OS << "<fi#" << getIndex() << ">";
230    break;
231  case MachineOperand::MO_ConstantPoolIndex:
232    OS << "<cp#" << getIndex();
233    if (getOffset()) OS << "+" << getOffset();
234    OS << ">";
235    break;
236  case MachineOperand::MO_JumpTableIndex:
237    OS << "<jt#" << getIndex() << ">";
238    break;
239  case MachineOperand::MO_GlobalAddress:
240    OS << "<ga:" << ((Value*)getGlobal())->getName();
241    if (getOffset()) OS << "+" << getOffset();
242    OS << ">";
243    break;
244  case MachineOperand::MO_ExternalSymbol:
245    OS << "<es:" << getSymbolName();
246    if (getOffset()) OS << "+" << getOffset();
247    OS << ">";
248    break;
249  default:
250    assert(0 && "Unrecognized operand type");
251  }
252}
253
254//===----------------------------------------------------------------------===//
255// MachineMemOperand Implementation
256//===----------------------------------------------------------------------===//
257
258MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
259                                     int64_t o, uint64_t s, unsigned int a)
260  : Offset(o), Size(s), V(v),
261    Flags((f & 7) | ((Log2_32(a) + 1) << 3)) {
262  assert(isPowerOf2_32(a) && "Alignment is not a power of 2!");
263  assert((isLoad() || isStore()) && "Not a load/store!");
264}
265
266/// Profile - Gather unique data for the object.
267///
268void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
269  ID.AddInteger(Offset);
270  ID.AddInteger(Size);
271  ID.AddPointer(V);
272  ID.AddInteger(Flags);
273}
274
275//===----------------------------------------------------------------------===//
276// MachineInstr Implementation
277//===----------------------------------------------------------------------===//
278
279/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
280/// TID NULL and no operands.
281MachineInstr::MachineInstr()
282  : TID(0), NumImplicitOps(0), Parent(0) {
283  // Make sure that we get added to a machine basicblock
284  LeakDetector::addGarbageObject(this);
285}
286
287void MachineInstr::addImplicitDefUseOperands() {
288  if (TID->ImplicitDefs)
289    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
290      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
291  if (TID->ImplicitUses)
292    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
293      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
294}
295
296/// MachineInstr ctor - This constructor create a MachineInstr and add the
297/// implicit operands. It reserves space for number of operands specified by
298/// TargetInstrDesc or the numOperands if it is not zero. (for
299/// instructions with variable number of operands).
300MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
301  : TID(&tid), NumImplicitOps(0), Parent(0) {
302  if (!NoImp && TID->getImplicitDefs())
303    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
304      NumImplicitOps++;
305  if (!NoImp && TID->getImplicitUses())
306    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
307      NumImplicitOps++;
308  Operands.reserve(NumImplicitOps + TID->getNumOperands());
309  if (!NoImp)
310    addImplicitDefUseOperands();
311  // Make sure that we get added to a machine basicblock
312  LeakDetector::addGarbageObject(this);
313}
314
315/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
316/// MachineInstr is created and added to the end of the specified basic block.
317///
318MachineInstr::MachineInstr(MachineBasicBlock *MBB,
319                           const TargetInstrDesc &tid)
320  : TID(&tid), NumImplicitOps(0), Parent(0) {
321  assert(MBB && "Cannot use inserting ctor with null basic block!");
322  if (TID->ImplicitDefs)
323    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
324      NumImplicitOps++;
325  if (TID->ImplicitUses)
326    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
327      NumImplicitOps++;
328  Operands.reserve(NumImplicitOps + TID->getNumOperands());
329  addImplicitDefUseOperands();
330  // Make sure that we get added to a machine basicblock
331  LeakDetector::addGarbageObject(this);
332  MBB->push_back(this);  // Add instruction to end of basic block!
333}
334
335/// MachineInstr ctor - Copies MachineInstr arg exactly
336///
337MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
338  : TID(&MI.getDesc()), NumImplicitOps(0), Parent(0) {
339  Operands.reserve(MI.getNumOperands());
340
341  // Add operands
342  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
343    addOperand(MI.getOperand(i));
344  NumImplicitOps = MI.NumImplicitOps;
345
346  // Add memory operands.
347  for (std::list<MachineMemOperand>::const_iterator i = MI.memoperands_begin(),
348       j = MI.memoperands_end(); i != j; ++i)
349    addMemOperand(MF, *i);
350
351  // Set parent to null.
352  Parent = 0;
353
354  LeakDetector::addGarbageObject(this);
355}
356
357MachineInstr::~MachineInstr() {
358  LeakDetector::removeGarbageObject(this);
359  assert(MemOperands.empty() &&
360         "MachineInstr being deleted with live memoperands!");
361#ifndef NDEBUG
362  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
363    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
364    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
365           "Reg operand def/use list corrupted");
366  }
367#endif
368}
369
370/// getRegInfo - If this instruction is embedded into a MachineFunction,
371/// return the MachineRegisterInfo object for the current function, otherwise
372/// return null.
373MachineRegisterInfo *MachineInstr::getRegInfo() {
374  if (MachineBasicBlock *MBB = getParent())
375    return &MBB->getParent()->getRegInfo();
376  return 0;
377}
378
379/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
380/// this instruction from their respective use lists.  This requires that the
381/// operands already be on their use lists.
382void MachineInstr::RemoveRegOperandsFromUseLists() {
383  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
384    if (Operands[i].isReg())
385      Operands[i].RemoveRegOperandFromRegInfo();
386  }
387}
388
389/// AddRegOperandsToUseLists - Add all of the register operands in
390/// this instruction from their respective use lists.  This requires that the
391/// operands not be on their use lists yet.
392void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
393  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
394    if (Operands[i].isReg())
395      Operands[i].AddRegOperandToRegInfo(&RegInfo);
396  }
397}
398
399
400/// addOperand - Add the specified operand to the instruction.  If it is an
401/// implicit operand, it is added to the end of the operand list.  If it is
402/// an explicit operand it is added at the end of the explicit operand list
403/// (before the first implicit operand).
404void MachineInstr::addOperand(const MachineOperand &Op) {
405  bool isImpReg = Op.isReg() && Op.isImplicit();
406  assert((isImpReg || !OperandsComplete()) &&
407         "Trying to add an operand to a machine instr that is already done!");
408
409  // If we are adding the operand to the end of the list, our job is simpler.
410  // This is true most of the time, so this is a reasonable optimization.
411  if (isImpReg || NumImplicitOps == 0) {
412    // We can only do this optimization if we know that the operand list won't
413    // reallocate.
414    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
415      Operands.push_back(Op);
416
417      // Set the parent of the operand.
418      Operands.back().ParentMI = this;
419
420      // If the operand is a register, update the operand's use list.
421      if (Op.isReg())
422        Operands.back().AddRegOperandToRegInfo(getRegInfo());
423      return;
424    }
425  }
426
427  // Otherwise, we have to insert a real operand before any implicit ones.
428  unsigned OpNo = Operands.size()-NumImplicitOps;
429
430  MachineRegisterInfo *RegInfo = getRegInfo();
431
432  // If this instruction isn't embedded into a function, then we don't need to
433  // update any operand lists.
434  if (RegInfo == 0) {
435    // Simple insertion, no reginfo update needed for other register operands.
436    Operands.insert(Operands.begin()+OpNo, Op);
437    Operands[OpNo].ParentMI = this;
438
439    // Do explicitly set the reginfo for this operand though, to ensure the
440    // next/prev fields are properly nulled out.
441    if (Operands[OpNo].isReg())
442      Operands[OpNo].AddRegOperandToRegInfo(0);
443
444  } else if (Operands.size()+1 <= Operands.capacity()) {
445    // Otherwise, we have to remove register operands from their register use
446    // list, add the operand, then add the register operands back to their use
447    // list.  This also must handle the case when the operand list reallocates
448    // to somewhere else.
449
450    // If insertion of this operand won't cause reallocation of the operand
451    // list, just remove the implicit operands, add the operand, then re-add all
452    // the rest of the operands.
453    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
454      assert(Operands[i].isReg() && "Should only be an implicit reg!");
455      Operands[i].RemoveRegOperandFromRegInfo();
456    }
457
458    // Add the operand.  If it is a register, add it to the reg list.
459    Operands.insert(Operands.begin()+OpNo, Op);
460    Operands[OpNo].ParentMI = this;
461
462    if (Operands[OpNo].isReg())
463      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
464
465    // Re-add all the implicit ops.
466    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
467      assert(Operands[i].isReg() && "Should only be an implicit reg!");
468      Operands[i].AddRegOperandToRegInfo(RegInfo);
469    }
470  } else {
471    // Otherwise, we will be reallocating the operand list.  Remove all reg
472    // operands from their list, then readd them after the operand list is
473    // reallocated.
474    RemoveRegOperandsFromUseLists();
475
476    Operands.insert(Operands.begin()+OpNo, Op);
477    Operands[OpNo].ParentMI = this;
478
479    // Re-add all the operands.
480    AddRegOperandsToUseLists(*RegInfo);
481  }
482}
483
484/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
485/// fewer operand than it started with.
486///
487void MachineInstr::RemoveOperand(unsigned OpNo) {
488  assert(OpNo < Operands.size() && "Invalid operand number");
489
490  // Special case removing the last one.
491  if (OpNo == Operands.size()-1) {
492    // If needed, remove from the reg def/use list.
493    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
494      Operands.back().RemoveRegOperandFromRegInfo();
495
496    Operands.pop_back();
497    return;
498  }
499
500  // Otherwise, we are removing an interior operand.  If we have reginfo to
501  // update, remove all operands that will be shifted down from their reg lists,
502  // move everything down, then re-add them.
503  MachineRegisterInfo *RegInfo = getRegInfo();
504  if (RegInfo) {
505    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
506      if (Operands[i].isReg())
507        Operands[i].RemoveRegOperandFromRegInfo();
508    }
509  }
510
511  Operands.erase(Operands.begin()+OpNo);
512
513  if (RegInfo) {
514    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
515      if (Operands[i].isReg())
516        Operands[i].AddRegOperandToRegInfo(RegInfo);
517    }
518  }
519}
520
521/// addMemOperand - Add a MachineMemOperand to the machine instruction,
522/// referencing arbitrary storage.
523void MachineInstr::addMemOperand(MachineFunction &MF,
524                                 const MachineMemOperand &MO) {
525  MemOperands.push_back(MO);
526}
527
528/// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
529void MachineInstr::clearMemOperands(MachineFunction &MF) {
530  MemOperands.clear();
531}
532
533
534/// removeFromParent - This method unlinks 'this' from the containing basic
535/// block, and returns it, but does not delete it.
536MachineInstr *MachineInstr::removeFromParent() {
537  assert(getParent() && "Not embedded in a basic block!");
538  getParent()->remove(this);
539  return this;
540}
541
542
543/// eraseFromParent - This method unlinks 'this' from the containing basic
544/// block, and deletes it.
545void MachineInstr::eraseFromParent() {
546  assert(getParent() && "Not embedded in a basic block!");
547  getParent()->erase(this);
548}
549
550
551/// OperandComplete - Return true if it's illegal to add a new operand
552///
553bool MachineInstr::OperandsComplete() const {
554  unsigned short NumOperands = TID->getNumOperands();
555  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
556    return true;  // Broken: we have all the operands of this instruction!
557  return false;
558}
559
560/// getNumExplicitOperands - Returns the number of non-implicit operands.
561///
562unsigned MachineInstr::getNumExplicitOperands() const {
563  unsigned NumOperands = TID->getNumOperands();
564  if (!TID->isVariadic())
565    return NumOperands;
566
567  for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
568    const MachineOperand &MO = getOperand(NumOperands);
569    if (!MO.isReg() || !MO.isImplicit())
570      NumOperands++;
571  }
572  return NumOperands;
573}
574
575
576/// isLabel - Returns true if the MachineInstr represents a label.
577///
578bool MachineInstr::isLabel() const {
579  return getOpcode() == TargetInstrInfo::DBG_LABEL ||
580         getOpcode() == TargetInstrInfo::EH_LABEL ||
581         getOpcode() == TargetInstrInfo::GC_LABEL;
582}
583
584/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
585///
586bool MachineInstr::isDebugLabel() const {
587  return getOpcode() == TargetInstrInfo::DBG_LABEL;
588}
589
590/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
591/// the specific register or -1 if it is not found. It further tightening
592/// the search criteria to a use that kills the register if isKill is true.
593int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
594                                          const TargetRegisterInfo *TRI) const {
595  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
596    const MachineOperand &MO = getOperand(i);
597    if (!MO.isReg() || !MO.isUse())
598      continue;
599    unsigned MOReg = MO.getReg();
600    if (!MOReg)
601      continue;
602    if (MOReg == Reg ||
603        (TRI &&
604         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
605         TargetRegisterInfo::isPhysicalRegister(Reg) &&
606         TRI->isSubRegister(MOReg, Reg)))
607      if (!isKill || MO.isKill())
608        return i;
609  }
610  return -1;
611}
612
613/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
614/// the specified register or -1 if it is not found. If isDead is true, defs
615/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
616/// also checks if there is a def of a super-register.
617int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
618                                          const TargetRegisterInfo *TRI) const {
619  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
620    const MachineOperand &MO = getOperand(i);
621    if (!MO.isReg() || !MO.isDef())
622      continue;
623    unsigned MOReg = MO.getReg();
624    if (MOReg == Reg ||
625        (TRI &&
626         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
627         TargetRegisterInfo::isPhysicalRegister(Reg) &&
628         TRI->isSubRegister(MOReg, Reg)))
629      if (!isDead || MO.isDead())
630        return i;
631  }
632  return -1;
633}
634
635/// findFirstPredOperandIdx() - Find the index of the first operand in the
636/// operand list that is used to represent the predicate. It returns -1 if
637/// none is found.
638int MachineInstr::findFirstPredOperandIdx() const {
639  const TargetInstrDesc &TID = getDesc();
640  if (TID.isPredicable()) {
641    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
642      if (TID.OpInfo[i].isPredicate())
643        return i;
644  }
645
646  return -1;
647}
648
649/// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
650/// check if the register def is a re-definition due to two addr elimination.
651bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const{
652  const TargetInstrDesc &TID = getDesc();
653  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
654    const MachineOperand &MO = getOperand(i);
655    if (MO.isReg() && MO.isUse() && MO.getReg() == Reg &&
656        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefIdx)
657      return true;
658  }
659  return false;
660}
661
662/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
663///
664void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
665  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
666    const MachineOperand &MO = MI->getOperand(i);
667    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
668      continue;
669    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
670      MachineOperand &MOp = getOperand(j);
671      if (!MOp.isIdenticalTo(MO))
672        continue;
673      if (MO.isKill())
674        MOp.setIsKill();
675      else
676        MOp.setIsDead();
677      break;
678    }
679  }
680}
681
682/// copyPredicates - Copies predicate operand(s) from MI.
683void MachineInstr::copyPredicates(const MachineInstr *MI) {
684  const TargetInstrDesc &TID = MI->getDesc();
685  if (!TID.isPredicable())
686    return;
687  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
688    if (TID.OpInfo[i].isPredicate()) {
689      // Predicated operands must be last operands.
690      addOperand(MI->getOperand(i));
691    }
692  }
693}
694
695/// isSafeToMove - Return true if it is safe to move this instruction. If
696/// SawStore is set to true, it means that there is a store (or call) between
697/// the instruction's location and its intended destination.
698bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
699                                bool &SawStore) const {
700  // Ignore stuff that we obviously can't move.
701  if (TID->mayStore() || TID->isCall()) {
702    SawStore = true;
703    return false;
704  }
705  if (TID->isReturn() || TID->isBranch() || TID->hasUnmodeledSideEffects())
706    return false;
707
708  // See if this instruction does a load.  If so, we have to guarantee that the
709  // loaded value doesn't change between the load and the its intended
710  // destination. The check for isInvariantLoad gives the targe the chance to
711  // classify the load as always returning a constant, e.g. a constant pool
712  // load.
713  if (TID->mayLoad() && !TII->isInvariantLoad(this))
714    // Otherwise, this is a real load.  If there is a store between the load and
715    // end of block, or if the laod is volatile, we can't move it.
716    return !SawStore && !hasVolatileMemoryRef();
717
718  return true;
719}
720
721/// isSafeToReMat - Return true if it's safe to rematerialize the specified
722/// instruction which defined the specified register instead of copying it.
723bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
724                                 unsigned DstReg) const {
725  bool SawStore = false;
726  if (!getDesc().isRematerializable() ||
727      !TII->isTriviallyReMaterializable(this) ||
728      !isSafeToMove(TII, SawStore))
729    return false;
730  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
731    const MachineOperand &MO = getOperand(i);
732    if (!MO.isReg())
733      continue;
734    // FIXME: For now, do not remat any instruction with register operands.
735    // Later on, we can loosen the restriction is the register operands have
736    // not been modified between the def and use. Note, this is different from
737    // MachineSink because the code is no longer in two-address form (at least
738    // partially).
739    if (MO.isUse())
740      return false;
741    else if (!MO.isDead() && MO.getReg() != DstReg)
742      return false;
743  }
744  return true;
745}
746
747/// hasVolatileMemoryRef - Return true if this instruction may have a
748/// volatile memory reference, or if the information describing the
749/// memory reference is not available. Return false if it is known to
750/// have no volatile memory references.
751bool MachineInstr::hasVolatileMemoryRef() const {
752  // An instruction known never to access memory won't have a volatile access.
753  if (!TID->mayStore() &&
754      !TID->mayLoad() &&
755      !TID->isCall() &&
756      !TID->hasUnmodeledSideEffects())
757    return false;
758
759  // Otherwise, if the instruction has no memory reference information,
760  // conservatively assume it wasn't preserved.
761  if (memoperands_empty())
762    return true;
763
764  // Check the memory reference information for volatile references.
765  for (std::list<MachineMemOperand>::const_iterator I = memoperands_begin(),
766       E = memoperands_end(); I != E; ++I)
767    if (I->isVolatile())
768      return true;
769
770  return false;
771}
772
773void MachineInstr::dump() const {
774  cerr << "  " << *this;
775}
776
777void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
778  raw_os_ostream RawOS(OS);
779  print(RawOS, TM);
780}
781
782void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
783  // Specialize printing if op#0 is definition
784  unsigned StartOp = 0;
785  if (getNumOperands() && getOperand(0).isReg() && getOperand(0).isDef()) {
786    getOperand(0).print(OS, TM);
787    OS << " = ";
788    ++StartOp;   // Don't print this operand again!
789  }
790
791  OS << getDesc().getName();
792
793  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
794    if (i != StartOp)
795      OS << ",";
796    OS << " ";
797    getOperand(i).print(OS, TM);
798  }
799
800  if (!memoperands_empty()) {
801    OS << ", Mem:";
802    for (std::list<MachineMemOperand>::const_iterator i = memoperands_begin(),
803         e = memoperands_end(); i != e; ++i) {
804      const MachineMemOperand &MRO = *i;
805      const Value *V = MRO.getValue();
806
807      assert((MRO.isLoad() || MRO.isStore()) &&
808             "SV has to be a load, store or both.");
809
810      if (MRO.isVolatile())
811        OS << "Volatile ";
812
813      if (MRO.isLoad())
814        OS << "LD";
815      if (MRO.isStore())
816        OS << "ST";
817
818      OS << "(" << MRO.getSize() << "," << MRO.getAlignment() << ") [";
819
820      if (!V)
821        OS << "<unknown>";
822      else if (!V->getName().empty())
823        OS << V->getName();
824      else if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
825        PSV->print(OS);
826      } else
827        OS << V;
828
829      OS << " + " << MRO.getOffset() << "]";
830    }
831  }
832
833  OS << "\n";
834}
835
836bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
837                                     const TargetRegisterInfo *RegInfo,
838                                     bool AddIfNotFound) {
839  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
840  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
841  bool Found = false;
842  SmallVector<unsigned,4> DeadOps;
843  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
844    MachineOperand &MO = getOperand(i);
845    if (!MO.isReg() || !MO.isUse())
846      continue;
847    unsigned Reg = MO.getReg();
848    if (!Reg)
849      continue;
850
851    if (Reg == IncomingReg) {
852      if (!Found) {
853        if (MO.isKill())
854          // The register is already marked kill.
855          return true;
856        MO.setIsKill();
857        Found = true;
858      }
859    } else if (hasAliases && MO.isKill() &&
860               TargetRegisterInfo::isPhysicalRegister(Reg)) {
861      // A super-register kill already exists.
862      if (RegInfo->isSuperRegister(IncomingReg, Reg))
863        return true;
864      if (RegInfo->isSubRegister(IncomingReg, Reg))
865        DeadOps.push_back(i);
866    }
867  }
868
869  // Trim unneeded kill operands.
870  while (!DeadOps.empty()) {
871    unsigned OpIdx = DeadOps.back();
872    if (getOperand(OpIdx).isImplicit())
873      RemoveOperand(OpIdx);
874    else
875      getOperand(OpIdx).setIsKill(false);
876    DeadOps.pop_back();
877  }
878
879  // If not found, this means an alias of one of the operands is killed. Add a
880  // new implicit operand if required.
881  if (!Found && AddIfNotFound) {
882    addOperand(MachineOperand::CreateReg(IncomingReg,
883                                         false /*IsDef*/,
884                                         true  /*IsImp*/,
885                                         true  /*IsKill*/));
886    return true;
887  }
888  return Found;
889}
890
891bool MachineInstr::addRegisterDead(unsigned IncomingReg,
892                                   const TargetRegisterInfo *RegInfo,
893                                   bool AddIfNotFound) {
894  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
895  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
896  bool Found = false;
897  SmallVector<unsigned,4> DeadOps;
898  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
899    MachineOperand &MO = getOperand(i);
900    if (!MO.isReg() || !MO.isDef())
901      continue;
902    unsigned Reg = MO.getReg();
903    if (!Reg)
904      continue;
905
906    if (Reg == IncomingReg) {
907      if (!Found) {
908        if (MO.isDead())
909          // The register is already marked dead.
910          return true;
911        MO.setIsDead();
912        Found = true;
913      }
914    } else if (hasAliases && MO.isDead() &&
915               TargetRegisterInfo::isPhysicalRegister(Reg)) {
916      // There exists a super-register that's marked dead.
917      if (RegInfo->isSuperRegister(IncomingReg, Reg))
918        return true;
919      if (RegInfo->getSubRegisters(IncomingReg) &&
920          RegInfo->getSuperRegisters(Reg) &&
921          RegInfo->isSubRegister(IncomingReg, Reg))
922        DeadOps.push_back(i);
923    }
924  }
925
926  // Trim unneeded dead operands.
927  while (!DeadOps.empty()) {
928    unsigned OpIdx = DeadOps.back();
929    if (getOperand(OpIdx).isImplicit())
930      RemoveOperand(OpIdx);
931    else
932      getOperand(OpIdx).setIsDead(false);
933    DeadOps.pop_back();
934  }
935
936  // If not found, this means an alias of one of the operands is dead. Add a
937  // new implicit operand if required.
938  if (!Found && AddIfNotFound) {
939    addOperand(MachineOperand::CreateReg(IncomingReg,
940                                         true  /*IsDef*/,
941                                         true  /*IsImp*/,
942                                         false /*IsKill*/,
943                                         true  /*IsDead*/));
944    return true;
945  }
946  return Found;
947}
948