MachineInstr.cpp revision cc84cda91997bf6fc93512a56c3a12eecaaa2d88 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/LLVMContext.h"
19#include "llvm/Metadata.h"
20#include "llvm/Module.h"
21#include "llvm/Type.h"
22#include "llvm/Value.h"
23#include "llvm/Assembly/Writer.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/MachineModuleInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Target/TargetMachine.h"
33#include "llvm/Target/TargetInstrInfo.h"
34#include "llvm/Target/TargetRegisterInfo.h"
35#include "llvm/Analysis/AliasAnalysis.h"
36#include "llvm/Analysis/DebugInfo.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/LeakDetector.h"
40#include "llvm/Support/MathExtras.h"
41#include "llvm/Support/raw_ostream.h"
42#include "llvm/ADT/FoldingSet.h"
43using namespace llvm;
44
45//===----------------------------------------------------------------------===//
46// MachineOperand Implementation
47//===----------------------------------------------------------------------===//
48
49/// AddRegOperandToRegInfo - Add this register operand to the specified
50/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
51/// explicitly nulled out.
52void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
53  assert(isReg() && "Can only add reg operand to use lists");
54
55  // If the reginfo pointer is null, just explicitly null out or next/prev
56  // pointers, to ensure they are not garbage.
57  if (RegInfo == 0) {
58    Contents.Reg.Prev = 0;
59    Contents.Reg.Next = 0;
60    return;
61  }
62
63  // Otherwise, add this operand to the head of the registers use/def list.
64  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
65
66  // For SSA values, we prefer to keep the definition at the start of the list.
67  // we do this by skipping over the definition if it is at the head of the
68  // list.
69  if (*Head && (*Head)->isDef())
70    Head = &(*Head)->Contents.Reg.Next;
71
72  Contents.Reg.Next = *Head;
73  if (Contents.Reg.Next) {
74    assert(getReg() == Contents.Reg.Next->getReg() &&
75           "Different regs on the same list!");
76    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
77  }
78
79  Contents.Reg.Prev = Head;
80  *Head = this;
81}
82
83/// RemoveRegOperandFromRegInfo - Remove this register operand from the
84/// MachineRegisterInfo it is linked with.
85void MachineOperand::RemoveRegOperandFromRegInfo() {
86  assert(isOnRegUseList() && "Reg operand is not on a use list");
87  // Unlink this from the doubly linked list of operands.
88  MachineOperand *NextOp = Contents.Reg.Next;
89  *Contents.Reg.Prev = NextOp;
90  if (NextOp) {
91    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
92    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
93  }
94  Contents.Reg.Prev = 0;
95  Contents.Reg.Next = 0;
96}
97
98void MachineOperand::setReg(unsigned Reg) {
99  if (getReg() == Reg) return; // No change.
100
101  // Otherwise, we have to change the register.  If this operand is embedded
102  // into a machine function, we need to update the old and new register's
103  // use/def lists.
104  if (MachineInstr *MI = getParent())
105    if (MachineBasicBlock *MBB = MI->getParent())
106      if (MachineFunction *MF = MBB->getParent()) {
107        RemoveRegOperandFromRegInfo();
108        SmallContents.RegNo = Reg;
109        AddRegOperandToRegInfo(&MF->getRegInfo());
110        return;
111      }
112
113  // Otherwise, just change the register, no problem.  :)
114  SmallContents.RegNo = Reg;
115}
116
117void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
118                                  const TargetRegisterInfo &TRI) {
119  assert(TargetRegisterInfo::isVirtualRegister(Reg));
120  if (SubIdx && getSubReg())
121    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
122  setReg(Reg);
123  if (SubIdx)
124    setSubReg(SubIdx);
125}
126
127void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
128  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
129  if (getSubReg()) {
130    Reg = TRI.getSubReg(Reg, getSubReg());
131    // Note that getSubReg() may return 0 if the sub-register doesn't exist.
132    // That won't happen in legal code.
133    setSubReg(0);
134  }
135  setReg(Reg);
136}
137
138/// ChangeToImmediate - Replace this operand with a new immediate operand of
139/// the specified value.  If an operand is known to be an immediate already,
140/// the setImm method should be used.
141void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
142  // If this operand is currently a register operand, and if this is in a
143  // function, deregister the operand from the register's use/def list.
144  if (isReg() && getParent() && getParent()->getParent() &&
145      getParent()->getParent()->getParent())
146    RemoveRegOperandFromRegInfo();
147
148  OpKind = MO_Immediate;
149  Contents.ImmVal = ImmVal;
150}
151
152/// ChangeToRegister - Replace this operand with a new register operand of
153/// the specified value.  If an operand is known to be an register already,
154/// the setReg method should be used.
155void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
156                                      bool isKill, bool isDead, bool isUndef,
157                                      bool isDebug) {
158  // If this operand is already a register operand, use setReg to update the
159  // register's use/def lists.
160  if (isReg()) {
161    assert(!isEarlyClobber());
162    setReg(Reg);
163  } else {
164    // Otherwise, change this to a register and set the reg#.
165    OpKind = MO_Register;
166    SmallContents.RegNo = Reg;
167
168    // If this operand is embedded in a function, add the operand to the
169    // register's use/def list.
170    if (MachineInstr *MI = getParent())
171      if (MachineBasicBlock *MBB = MI->getParent())
172        if (MachineFunction *MF = MBB->getParent())
173          AddRegOperandToRegInfo(&MF->getRegInfo());
174  }
175
176  IsDef = isDef;
177  IsImp = isImp;
178  IsKill = isKill;
179  IsDead = isDead;
180  IsUndef = isUndef;
181  IsEarlyClobber = false;
182  IsDebug = isDebug;
183  SubReg = 0;
184}
185
186/// isIdenticalTo - Return true if this operand is identical to the specified
187/// operand.
188bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
189  if (getType() != Other.getType() ||
190      getTargetFlags() != Other.getTargetFlags())
191    return false;
192
193  switch (getType()) {
194  default: llvm_unreachable("Unrecognized operand type");
195  case MachineOperand::MO_Register:
196    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
197           getSubReg() == Other.getSubReg();
198  case MachineOperand::MO_Immediate:
199    return getImm() == Other.getImm();
200  case MachineOperand::MO_CImmediate:
201    return getCImm() == Other.getCImm();
202  case MachineOperand::MO_FPImmediate:
203    return getFPImm() == Other.getFPImm();
204  case MachineOperand::MO_MachineBasicBlock:
205    return getMBB() == Other.getMBB();
206  case MachineOperand::MO_FrameIndex:
207    return getIndex() == Other.getIndex();
208  case MachineOperand::MO_ConstantPoolIndex:
209    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
210  case MachineOperand::MO_JumpTableIndex:
211    return getIndex() == Other.getIndex();
212  case MachineOperand::MO_GlobalAddress:
213    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
214  case MachineOperand::MO_ExternalSymbol:
215    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
216           getOffset() == Other.getOffset();
217  case MachineOperand::MO_BlockAddress:
218    return getBlockAddress() == Other.getBlockAddress();
219  case MachineOperand::MO_MCSymbol:
220    return getMCSymbol() == Other.getMCSymbol();
221  case MachineOperand::MO_Metadata:
222    return getMetadata() == Other.getMetadata();
223  }
224}
225
226/// print - Print the specified machine operand.
227///
228void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
229  // If the instruction is embedded into a basic block, we can find the
230  // target info for the instruction.
231  if (!TM)
232    if (const MachineInstr *MI = getParent())
233      if (const MachineBasicBlock *MBB = MI->getParent())
234        if (const MachineFunction *MF = MBB->getParent())
235          TM = &MF->getTarget();
236  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
237
238  switch (getType()) {
239  case MachineOperand::MO_Register:
240    OS << PrintReg(getReg(), TRI, getSubReg());
241
242    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
243        isEarlyClobber()) {
244      OS << '<';
245      bool NeedComma = false;
246      if (isDef()) {
247        if (NeedComma) OS << ',';
248        if (isEarlyClobber())
249          OS << "earlyclobber,";
250        if (isImplicit())
251          OS << "imp-";
252        OS << "def";
253        NeedComma = true;
254      } else if (isImplicit()) {
255          OS << "imp-use";
256          NeedComma = true;
257      }
258
259      if (isKill() || isDead() || isUndef()) {
260        if (NeedComma) OS << ',';
261        if (isKill())  OS << "kill";
262        if (isDead())  OS << "dead";
263        if (isUndef()) {
264          if (isKill() || isDead())
265            OS << ',';
266          OS << "undef";
267        }
268      }
269      OS << '>';
270    }
271    break;
272  case MachineOperand::MO_Immediate:
273    OS << getImm();
274    break;
275  case MachineOperand::MO_CImmediate:
276    getCImm()->getValue().print(OS, false);
277    break;
278  case MachineOperand::MO_FPImmediate:
279    if (getFPImm()->getType()->isFloatTy())
280      OS << getFPImm()->getValueAPF().convertToFloat();
281    else
282      OS << getFPImm()->getValueAPF().convertToDouble();
283    break;
284  case MachineOperand::MO_MachineBasicBlock:
285    OS << "<BB#" << getMBB()->getNumber() << ">";
286    break;
287  case MachineOperand::MO_FrameIndex:
288    OS << "<fi#" << getIndex() << '>';
289    break;
290  case MachineOperand::MO_ConstantPoolIndex:
291    OS << "<cp#" << getIndex();
292    if (getOffset()) OS << "+" << getOffset();
293    OS << '>';
294    break;
295  case MachineOperand::MO_JumpTableIndex:
296    OS << "<jt#" << getIndex() << '>';
297    break;
298  case MachineOperand::MO_GlobalAddress:
299    OS << "<ga:";
300    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
301    if (getOffset()) OS << "+" << getOffset();
302    OS << '>';
303    break;
304  case MachineOperand::MO_ExternalSymbol:
305    OS << "<es:" << getSymbolName();
306    if (getOffset()) OS << "+" << getOffset();
307    OS << '>';
308    break;
309  case MachineOperand::MO_BlockAddress:
310    OS << '<';
311    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
312    OS << '>';
313    break;
314  case MachineOperand::MO_Metadata:
315    OS << '<';
316    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
317    OS << '>';
318    break;
319  case MachineOperand::MO_MCSymbol:
320    OS << "<MCSym=" << *getMCSymbol() << '>';
321    break;
322  default:
323    llvm_unreachable("Unrecognized operand type");
324  }
325
326  if (unsigned TF = getTargetFlags())
327    OS << "[TF=" << TF << ']';
328}
329
330//===----------------------------------------------------------------------===//
331// MachineMemOperand Implementation
332//===----------------------------------------------------------------------===//
333
334/// getAddrSpace - Return the LLVM IR address space number that this pointer
335/// points into.
336unsigned MachinePointerInfo::getAddrSpace() const {
337  if (V == 0) return 0;
338  return cast<PointerType>(V->getType())->getAddressSpace();
339}
340
341/// getConstantPool - Return a MachinePointerInfo record that refers to the
342/// constant pool.
343MachinePointerInfo MachinePointerInfo::getConstantPool() {
344  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
345}
346
347/// getFixedStack - Return a MachinePointerInfo record that refers to the
348/// the specified FrameIndex.
349MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
350  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
351}
352
353MachinePointerInfo MachinePointerInfo::getJumpTable() {
354  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
355}
356
357MachinePointerInfo MachinePointerInfo::getGOT() {
358  return MachinePointerInfo(PseudoSourceValue::getGOT());
359}
360
361MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
362  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
363}
364
365MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
366                                     uint64_t s, unsigned int a,
367                                     const MDNode *TBAAInfo)
368  : PtrInfo(ptrinfo), Size(s),
369    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
370    TBAAInfo(TBAAInfo) {
371  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
372         "invalid pointer value");
373  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
374  assert((isLoad() || isStore()) && "Not a load/store!");
375}
376
377/// Profile - Gather unique data for the object.
378///
379void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
380  ID.AddInteger(getOffset());
381  ID.AddInteger(Size);
382  ID.AddPointer(getValue());
383  ID.AddInteger(Flags);
384}
385
386void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
387  // The Value and Offset may differ due to CSE. But the flags and size
388  // should be the same.
389  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
390  assert(MMO->getSize() == getSize() && "Size mismatch!");
391
392  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
393    // Update the alignment value.
394    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
395      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
396    // Also update the base and offset, because the new alignment may
397    // not be applicable with the old ones.
398    PtrInfo = MMO->PtrInfo;
399  }
400}
401
402/// getAlignment - Return the minimum known alignment in bytes of the
403/// actual memory reference.
404uint64_t MachineMemOperand::getAlignment() const {
405  return MinAlign(getBaseAlignment(), getOffset());
406}
407
408raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
409  assert((MMO.isLoad() || MMO.isStore()) &&
410         "SV has to be a load, store or both.");
411
412  if (MMO.isVolatile())
413    OS << "Volatile ";
414
415  if (MMO.isLoad())
416    OS << "LD";
417  if (MMO.isStore())
418    OS << "ST";
419  OS << MMO.getSize();
420
421  // Print the address information.
422  OS << "[";
423  if (!MMO.getValue())
424    OS << "<unknown>";
425  else
426    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
427
428  // If the alignment of the memory reference itself differs from the alignment
429  // of the base pointer, print the base alignment explicitly, next to the base
430  // pointer.
431  if (MMO.getBaseAlignment() != MMO.getAlignment())
432    OS << "(align=" << MMO.getBaseAlignment() << ")";
433
434  if (MMO.getOffset() != 0)
435    OS << "+" << MMO.getOffset();
436  OS << "]";
437
438  // Print the alignment of the reference.
439  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
440      MMO.getBaseAlignment() != MMO.getSize())
441    OS << "(align=" << MMO.getAlignment() << ")";
442
443  // Print TBAA info.
444  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
445    OS << "(tbaa=";
446    if (TBAAInfo->getNumOperands() > 0)
447      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
448    else
449      OS << "<unknown>";
450    OS << ")";
451  }
452
453  // Print nontemporal info.
454  if (MMO.isNonTemporal())
455    OS << "(nontemporal)";
456
457  return OS;
458}
459
460//===----------------------------------------------------------------------===//
461// MachineInstr Implementation
462//===----------------------------------------------------------------------===//
463
464/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
465/// MCID NULL and no operands.
466MachineInstr::MachineInstr()
467  : MCID(0), Flags(0), AsmPrinterFlags(0),
468    MemRefs(0), MemRefsEnd(0),
469    Parent(0) {
470  // Make sure that we get added to a machine basicblock
471  LeakDetector::addGarbageObject(this);
472}
473
474void MachineInstr::addImplicitDefUseOperands() {
475  if (MCID->ImplicitDefs)
476    for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs)
477      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
478  if (MCID->ImplicitUses)
479    for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses)
480      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
481}
482
483/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
484/// implicit operands. It reserves space for the number of operands specified by
485/// the MCInstrDesc.
486MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp)
487  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
488    MemRefs(0), MemRefsEnd(0), Parent(0) {
489  unsigned NumImplicitOps = 0;
490  if (!NoImp)
491    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
492  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
493  if (!NoImp)
494    addImplicitDefUseOperands();
495  // Make sure that we get added to a machine basicblock
496  LeakDetector::addGarbageObject(this);
497}
498
499/// MachineInstr ctor - As above, but with a DebugLoc.
500MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl,
501                           bool NoImp)
502  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
503    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
504  unsigned NumImplicitOps = 0;
505  if (!NoImp)
506    NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
507  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
508  if (!NoImp)
509    addImplicitDefUseOperands();
510  // Make sure that we get added to a machine basicblock
511  LeakDetector::addGarbageObject(this);
512}
513
514/// MachineInstr ctor - Work exactly the same as the ctor two above, except
515/// that the MachineInstr is created and added to the end of the specified
516/// basic block.
517MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid)
518  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
519    MemRefs(0), MemRefsEnd(0), Parent(0) {
520  assert(MBB && "Cannot use inserting ctor with null basic block!");
521  unsigned NumImplicitOps =
522    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
523  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
524  addImplicitDefUseOperands();
525  // Make sure that we get added to a machine basicblock
526  LeakDetector::addGarbageObject(this);
527  MBB->push_back(this);  // Add instruction to end of basic block!
528}
529
530/// MachineInstr ctor - As above, but with a DebugLoc.
531///
532MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
533                           const MCInstrDesc &tid)
534  : MCID(&tid), Flags(0), AsmPrinterFlags(0),
535    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
536  assert(MBB && "Cannot use inserting ctor with null basic block!");
537  unsigned NumImplicitOps =
538    MCID->getNumImplicitDefs() + MCID->getNumImplicitUses();
539  Operands.reserve(NumImplicitOps + MCID->getNumOperands());
540  addImplicitDefUseOperands();
541  // Make sure that we get added to a machine basicblock
542  LeakDetector::addGarbageObject(this);
543  MBB->push_back(this);  // Add instruction to end of basic block!
544}
545
546/// MachineInstr ctor - Copies MachineInstr arg exactly
547///
548MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
549  : MCID(&MI.getDesc()), Flags(0), AsmPrinterFlags(0),
550    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
551    Parent(0), debugLoc(MI.getDebugLoc()) {
552  Operands.reserve(MI.getNumOperands());
553
554  // Add operands
555  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
556    addOperand(MI.getOperand(i));
557
558  // Copy all the flags.
559  Flags = MI.Flags;
560
561  // Set parent to null.
562  Parent = 0;
563
564  LeakDetector::addGarbageObject(this);
565}
566
567MachineInstr::~MachineInstr() {
568  LeakDetector::removeGarbageObject(this);
569#ifndef NDEBUG
570  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
571    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
572    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
573           "Reg operand def/use list corrupted");
574  }
575#endif
576}
577
578/// getRegInfo - If this instruction is embedded into a MachineFunction,
579/// return the MachineRegisterInfo object for the current function, otherwise
580/// return null.
581MachineRegisterInfo *MachineInstr::getRegInfo() {
582  if (MachineBasicBlock *MBB = getParent())
583    return &MBB->getParent()->getRegInfo();
584  return 0;
585}
586
587/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
588/// this instruction from their respective use lists.  This requires that the
589/// operands already be on their use lists.
590void MachineInstr::RemoveRegOperandsFromUseLists() {
591  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
592    if (Operands[i].isReg())
593      Operands[i].RemoveRegOperandFromRegInfo();
594  }
595}
596
597/// AddRegOperandsToUseLists - Add all of the register operands in
598/// this instruction from their respective use lists.  This requires that the
599/// operands not be on their use lists yet.
600void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
601  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
602    if (Operands[i].isReg())
603      Operands[i].AddRegOperandToRegInfo(&RegInfo);
604  }
605}
606
607
608/// addOperand - Add the specified operand to the instruction.  If it is an
609/// implicit operand, it is added to the end of the operand list.  If it is
610/// an explicit operand it is added at the end of the explicit operand list
611/// (before the first implicit operand).
612void MachineInstr::addOperand(const MachineOperand &Op) {
613  assert(MCID && "Cannot add operands before providing an instr descriptor");
614  bool isImpReg = Op.isReg() && Op.isImplicit();
615  MachineRegisterInfo *RegInfo = getRegInfo();
616
617  // If the Operands backing store is reallocated, all register operands must
618  // be removed and re-added to RegInfo.  It is storing pointers to operands.
619  bool Reallocate = RegInfo &&
620    !Operands.empty() && Operands.size() == Operands.capacity();
621
622  // Find the insert location for the new operand.  Implicit registers go at
623  // the end, everything goes before the implicit regs.
624  unsigned OpNo = Operands.size();
625
626  // Remove all the implicit operands from RegInfo if they need to be shifted.
627  // FIXME: Allow mixed explicit and implicit operands on inline asm.
628  // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
629  // implicit-defs, but they must not be moved around.  See the FIXME in
630  // InstrEmitter.cpp.
631  if (!isImpReg && !isInlineAsm()) {
632    while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
633      --OpNo;
634      if (RegInfo)
635        Operands[OpNo].RemoveRegOperandFromRegInfo();
636    }
637  }
638
639  // OpNo now points as the desired insertion point.  Unless this is a variadic
640  // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
641  assert((isImpReg || MCID->isVariadic() || OpNo < MCID->getNumOperands()) &&
642         "Trying to add an operand to a machine instr that is already done!");
643
644  // All operands from OpNo have been removed from RegInfo.  If the Operands
645  // backing store needs to be reallocated, we also need to remove any other
646  // register operands.
647  if (Reallocate)
648    for (unsigned i = 0; i != OpNo; ++i)
649      if (Operands[i].isReg())
650        Operands[i].RemoveRegOperandFromRegInfo();
651
652  // Insert the new operand at OpNo.
653  Operands.insert(Operands.begin() + OpNo, Op);
654  Operands[OpNo].ParentMI = this;
655
656  // The Operands backing store has now been reallocated, so we can re-add the
657  // operands before OpNo.
658  if (Reallocate)
659    for (unsigned i = 0; i != OpNo; ++i)
660      if (Operands[i].isReg())
661        Operands[i].AddRegOperandToRegInfo(RegInfo);
662
663  // When adding a register operand, tell RegInfo about it.
664  if (Operands[OpNo].isReg()) {
665    // Add the new operand to RegInfo, even when RegInfo is NULL.
666    // This will initialize the linked list pointers.
667    Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
668    // If the register operand is flagged as early, mark the operand as such.
669    if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
670      Operands[OpNo].setIsEarlyClobber(true);
671  }
672
673  // Re-add all the implicit ops.
674  if (RegInfo) {
675    for (unsigned i = OpNo + 1, e = Operands.size(); i != e; ++i) {
676      assert(Operands[i].isReg() && "Should only be an implicit reg!");
677      Operands[i].AddRegOperandToRegInfo(RegInfo);
678    }
679  }
680}
681
682/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
683/// fewer operand than it started with.
684///
685void MachineInstr::RemoveOperand(unsigned OpNo) {
686  assert(OpNo < Operands.size() && "Invalid operand number");
687
688  // Special case removing the last one.
689  if (OpNo == Operands.size()-1) {
690    // If needed, remove from the reg def/use list.
691    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
692      Operands.back().RemoveRegOperandFromRegInfo();
693
694    Operands.pop_back();
695    return;
696  }
697
698  // Otherwise, we are removing an interior operand.  If we have reginfo to
699  // update, remove all operands that will be shifted down from their reg lists,
700  // move everything down, then re-add them.
701  MachineRegisterInfo *RegInfo = getRegInfo();
702  if (RegInfo) {
703    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
704      if (Operands[i].isReg())
705        Operands[i].RemoveRegOperandFromRegInfo();
706    }
707  }
708
709  Operands.erase(Operands.begin()+OpNo);
710
711  if (RegInfo) {
712    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
713      if (Operands[i].isReg())
714        Operands[i].AddRegOperandToRegInfo(RegInfo);
715    }
716  }
717}
718
719/// addMemOperand - Add a MachineMemOperand to the machine instruction.
720/// This function should be used only occasionally. The setMemRefs function
721/// is the primary method for setting up a MachineInstr's MemRefs list.
722void MachineInstr::addMemOperand(MachineFunction &MF,
723                                 MachineMemOperand *MO) {
724  mmo_iterator OldMemRefs = MemRefs;
725  mmo_iterator OldMemRefsEnd = MemRefsEnd;
726
727  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
728  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
729  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
730
731  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
732  NewMemRefs[NewNum - 1] = MO;
733
734  MemRefs = NewMemRefs;
735  MemRefsEnd = NewMemRefsEnd;
736}
737
738bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
739                                 MICheckType Check) const {
740  // If opcodes or number of operands are not the same then the two
741  // instructions are obviously not identical.
742  if (Other->getOpcode() != getOpcode() ||
743      Other->getNumOperands() != getNumOperands())
744    return false;
745
746  // Check operands to make sure they match.
747  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
748    const MachineOperand &MO = getOperand(i);
749    const MachineOperand &OMO = Other->getOperand(i);
750    if (!MO.isReg()) {
751      if (!MO.isIdenticalTo(OMO))
752        return false;
753      continue;
754    }
755
756    // Clients may or may not want to ignore defs when testing for equality.
757    // For example, machine CSE pass only cares about finding common
758    // subexpressions, so it's safe to ignore virtual register defs.
759    if (MO.isDef()) {
760      if (Check == IgnoreDefs)
761        continue;
762      else if (Check == IgnoreVRegDefs) {
763        if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
764            TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
765          if (MO.getReg() != OMO.getReg())
766            return false;
767      } else {
768        if (!MO.isIdenticalTo(OMO))
769          return false;
770        if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
771          return false;
772      }
773    } else {
774      if (!MO.isIdenticalTo(OMO))
775        return false;
776      if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
777        return false;
778    }
779  }
780  // If DebugLoc does not match then two dbg.values are not identical.
781  if (isDebugValue())
782    if (!getDebugLoc().isUnknown() && !Other->getDebugLoc().isUnknown()
783        && getDebugLoc() != Other->getDebugLoc())
784      return false;
785  return true;
786}
787
788/// removeFromParent - This method unlinks 'this' from the containing basic
789/// block, and returns it, but does not delete it.
790MachineInstr *MachineInstr::removeFromParent() {
791  assert(getParent() && "Not embedded in a basic block!");
792  getParent()->remove(this);
793  return this;
794}
795
796
797/// eraseFromParent - This method unlinks 'this' from the containing basic
798/// block, and deletes it.
799void MachineInstr::eraseFromParent() {
800  assert(getParent() && "Not embedded in a basic block!");
801  getParent()->erase(this);
802}
803
804
805/// getNumExplicitOperands - Returns the number of non-implicit operands.
806///
807unsigned MachineInstr::getNumExplicitOperands() const {
808  unsigned NumOperands = MCID->getNumOperands();
809  if (!MCID->isVariadic())
810    return NumOperands;
811
812  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
813    const MachineOperand &MO = getOperand(i);
814    if (!MO.isReg() || !MO.isImplicit())
815      NumOperands++;
816  }
817  return NumOperands;
818}
819
820bool MachineInstr::isStackAligningInlineAsm() const {
821  if (isInlineAsm()) {
822    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
823    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
824      return true;
825  }
826  return false;
827}
828
829/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
830/// the specific register or -1 if it is not found. It further tightens
831/// the search criteria to a use that kills the register if isKill is true.
832int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
833                                          const TargetRegisterInfo *TRI) const {
834  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
835    const MachineOperand &MO = getOperand(i);
836    if (!MO.isReg() || !MO.isUse())
837      continue;
838    unsigned MOReg = MO.getReg();
839    if (!MOReg)
840      continue;
841    if (MOReg == Reg ||
842        (TRI &&
843         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
844         TargetRegisterInfo::isPhysicalRegister(Reg) &&
845         TRI->isSubRegister(MOReg, Reg)))
846      if (!isKill || MO.isKill())
847        return i;
848  }
849  return -1;
850}
851
852/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
853/// indicating if this instruction reads or writes Reg. This also considers
854/// partial defines.
855std::pair<bool,bool>
856MachineInstr::readsWritesVirtualRegister(unsigned Reg,
857                                         SmallVectorImpl<unsigned> *Ops) const {
858  bool PartDef = false; // Partial redefine.
859  bool FullDef = false; // Full define.
860  bool Use = false;
861
862  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
863    const MachineOperand &MO = getOperand(i);
864    if (!MO.isReg() || MO.getReg() != Reg)
865      continue;
866    if (Ops)
867      Ops->push_back(i);
868    if (MO.isUse())
869      Use |= !MO.isUndef();
870    else if (MO.getSubReg() && !MO.isUndef())
871      // A partial <def,undef> doesn't count as reading the register.
872      PartDef = true;
873    else
874      FullDef = true;
875  }
876  // A partial redefine uses Reg unless there is also a full define.
877  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
878}
879
880/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
881/// the specified register or -1 if it is not found. If isDead is true, defs
882/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
883/// also checks if there is a def of a super-register.
884int
885MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
886                                        const TargetRegisterInfo *TRI) const {
887  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
888  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
889    const MachineOperand &MO = getOperand(i);
890    if (!MO.isReg() || !MO.isDef())
891      continue;
892    unsigned MOReg = MO.getReg();
893    bool Found = (MOReg == Reg);
894    if (!Found && TRI && isPhys &&
895        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
896      if (Overlap)
897        Found = TRI->regsOverlap(MOReg, Reg);
898      else
899        Found = TRI->isSubRegister(MOReg, Reg);
900    }
901    if (Found && (!isDead || MO.isDead()))
902      return i;
903  }
904  return -1;
905}
906
907/// findFirstPredOperandIdx() - Find the index of the first operand in the
908/// operand list that is used to represent the predicate. It returns -1 if
909/// none is found.
910int MachineInstr::findFirstPredOperandIdx() const {
911  // Don't call MCID.findFirstPredOperandIdx() because this variant
912  // is sometimes called on an instruction that's not yet complete, and
913  // so the number of operands is less than the MCID indicates. In
914  // particular, the PTX target does this.
915  const MCInstrDesc &MCID = getDesc();
916  if (MCID.isPredicable()) {
917    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
918      if (MCID.OpInfo[i].isPredicate())
919        return i;
920  }
921
922  return -1;
923}
924
925/// isRegTiedToUseOperand - Given the index of a register def operand,
926/// check if the register def is tied to a source operand, due to either
927/// two-address elimination or inline assembly constraints. Returns the
928/// first tied use operand index by reference is UseOpIdx is not null.
929bool MachineInstr::
930isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
931  if (isInlineAsm()) {
932    assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
933    const MachineOperand &MO = getOperand(DefOpIdx);
934    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
935      return false;
936    // Determine the actual operand index that corresponds to this index.
937    unsigned DefNo = 0;
938    unsigned DefPart = 0;
939    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
940         i < e; ) {
941      const MachineOperand &FMO = getOperand(i);
942      // After the normal asm operands there may be additional imp-def regs.
943      if (!FMO.isImm())
944        return false;
945      // Skip over this def.
946      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
947      unsigned PrevDef = i + 1;
948      i = PrevDef + NumOps;
949      if (i > DefOpIdx) {
950        DefPart = DefOpIdx - PrevDef;
951        break;
952      }
953      ++DefNo;
954    }
955    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
956         i != e; ++i) {
957      const MachineOperand &FMO = getOperand(i);
958      if (!FMO.isImm())
959        continue;
960      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
961        continue;
962      unsigned Idx;
963      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
964          Idx == DefNo) {
965        if (UseOpIdx)
966          *UseOpIdx = (unsigned)i + 1 + DefPart;
967        return true;
968      }
969    }
970    return false;
971  }
972
973  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
974  const MCInstrDesc &MCID = getDesc();
975  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
976    const MachineOperand &MO = getOperand(i);
977    if (MO.isReg() && MO.isUse() &&
978        MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) {
979      if (UseOpIdx)
980        *UseOpIdx = (unsigned)i;
981      return true;
982    }
983  }
984  return false;
985}
986
987/// isRegTiedToDefOperand - Return true if the operand of the specified index
988/// is a register use and it is tied to an def operand. It also returns the def
989/// operand index by reference.
990bool MachineInstr::
991isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
992  if (isInlineAsm()) {
993    const MachineOperand &MO = getOperand(UseOpIdx);
994    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
995      return false;
996
997    // Find the flag operand corresponding to UseOpIdx
998    unsigned FlagIdx, NumOps=0;
999    for (FlagIdx = InlineAsm::MIOp_FirstOperand;
1000         FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
1001      const MachineOperand &UFMO = getOperand(FlagIdx);
1002      // After the normal asm operands there may be additional imp-def regs.
1003      if (!UFMO.isImm())
1004        return false;
1005      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1006      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1007      if (UseOpIdx < FlagIdx+NumOps+1)
1008        break;
1009    }
1010    if (FlagIdx >= UseOpIdx)
1011      return false;
1012    const MachineOperand &UFMO = getOperand(FlagIdx);
1013    unsigned DefNo;
1014    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1015      if (!DefOpIdx)
1016        return true;
1017
1018      unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1019      // Remember to adjust the index. First operand is asm string, second is
1020      // the HasSideEffects and AlignStack bits, then there is a flag for each.
1021      while (DefNo) {
1022        const MachineOperand &FMO = getOperand(DefIdx);
1023        assert(FMO.isImm());
1024        // Skip over this def.
1025        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1026        --DefNo;
1027      }
1028      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1029      return true;
1030    }
1031    return false;
1032  }
1033
1034  const MCInstrDesc &MCID = getDesc();
1035  if (UseOpIdx >= MCID.getNumOperands())
1036    return false;
1037  const MachineOperand &MO = getOperand(UseOpIdx);
1038  if (!MO.isReg() || !MO.isUse())
1039    return false;
1040  int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO);
1041  if (DefIdx == -1)
1042    return false;
1043  if (DefOpIdx)
1044    *DefOpIdx = (unsigned)DefIdx;
1045  return true;
1046}
1047
1048/// clearKillInfo - Clears kill flags on all operands.
1049///
1050void MachineInstr::clearKillInfo() {
1051  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1052    MachineOperand &MO = getOperand(i);
1053    if (MO.isReg() && MO.isUse())
1054      MO.setIsKill(false);
1055  }
1056}
1057
1058/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1059///
1060void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1061  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1062    const MachineOperand &MO = MI->getOperand(i);
1063    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1064      continue;
1065    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1066      MachineOperand &MOp = getOperand(j);
1067      if (!MOp.isIdenticalTo(MO))
1068        continue;
1069      if (MO.isKill())
1070        MOp.setIsKill();
1071      else
1072        MOp.setIsDead();
1073      break;
1074    }
1075  }
1076}
1077
1078/// copyPredicates - Copies predicate operand(s) from MI.
1079void MachineInstr::copyPredicates(const MachineInstr *MI) {
1080  const MCInstrDesc &MCID = MI->getDesc();
1081  if (!MCID.isPredicable())
1082    return;
1083  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1084    if (MCID.OpInfo[i].isPredicate()) {
1085      // Predicated operands must be last operands.
1086      addOperand(MI->getOperand(i));
1087    }
1088  }
1089}
1090
1091void MachineInstr::substituteRegister(unsigned FromReg,
1092                                      unsigned ToReg,
1093                                      unsigned SubIdx,
1094                                      const TargetRegisterInfo &RegInfo) {
1095  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1096    if (SubIdx)
1097      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1098    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1099      MachineOperand &MO = getOperand(i);
1100      if (!MO.isReg() || MO.getReg() != FromReg)
1101        continue;
1102      MO.substPhysReg(ToReg, RegInfo);
1103    }
1104  } else {
1105    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1106      MachineOperand &MO = getOperand(i);
1107      if (!MO.isReg() || MO.getReg() != FromReg)
1108        continue;
1109      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1110    }
1111  }
1112}
1113
1114/// isSafeToMove - Return true if it is safe to move this instruction. If
1115/// SawStore is set to true, it means that there is a store (or call) between
1116/// the instruction's location and its intended destination.
1117bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1118                                AliasAnalysis *AA,
1119                                bool &SawStore) const {
1120  // Ignore stuff that we obviously can't move.
1121  if (MCID->mayStore() || MCID->isCall()) {
1122    SawStore = true;
1123    return false;
1124  }
1125
1126  if (isLabel() || isDebugValue() ||
1127      MCID->isTerminator() || hasUnmodeledSideEffects())
1128    return false;
1129
1130  // See if this instruction does a load.  If so, we have to guarantee that the
1131  // loaded value doesn't change between the load and the its intended
1132  // destination. The check for isInvariantLoad gives the targe the chance to
1133  // classify the load as always returning a constant, e.g. a constant pool
1134  // load.
1135  if (MCID->mayLoad() && !isInvariantLoad(AA))
1136    // Otherwise, this is a real load.  If there is a store between the load and
1137    // end of block, or if the load is volatile, we can't move it.
1138    return !SawStore && !hasVolatileMemoryRef();
1139
1140  return true;
1141}
1142
1143/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1144/// instruction which defined the specified register instead of copying it.
1145bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1146                                 AliasAnalysis *AA,
1147                                 unsigned DstReg) const {
1148  bool SawStore = false;
1149  if (!TII->isTriviallyReMaterializable(this, AA) ||
1150      !isSafeToMove(TII, AA, SawStore))
1151    return false;
1152  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1153    const MachineOperand &MO = getOperand(i);
1154    if (!MO.isReg())
1155      continue;
1156    // FIXME: For now, do not remat any instruction with register operands.
1157    // Later on, we can loosen the restriction is the register operands have
1158    // not been modified between the def and use. Note, this is different from
1159    // MachineSink because the code is no longer in two-address form (at least
1160    // partially).
1161    if (MO.isUse())
1162      return false;
1163    else if (!MO.isDead() && MO.getReg() != DstReg)
1164      return false;
1165  }
1166  return true;
1167}
1168
1169/// hasVolatileMemoryRef - Return true if this instruction may have a
1170/// volatile memory reference, or if the information describing the
1171/// memory reference is not available. Return false if it is known to
1172/// have no volatile memory references.
1173bool MachineInstr::hasVolatileMemoryRef() const {
1174  // An instruction known never to access memory won't have a volatile access.
1175  if (!MCID->mayStore() &&
1176      !MCID->mayLoad() &&
1177      !MCID->isCall() &&
1178      !hasUnmodeledSideEffects())
1179    return false;
1180
1181  // Otherwise, if the instruction has no memory reference information,
1182  // conservatively assume it wasn't preserved.
1183  if (memoperands_empty())
1184    return true;
1185
1186  // Check the memory reference information for volatile references.
1187  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1188    if ((*I)->isVolatile())
1189      return true;
1190
1191  return false;
1192}
1193
1194/// isInvariantLoad - Return true if this instruction is loading from a
1195/// location whose value is invariant across the function.  For example,
1196/// loading a value from the constant pool or from the argument area
1197/// of a function if it does not change.  This should only return true of
1198/// *all* loads the instruction does are invariant (if it does multiple loads).
1199bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1200  // If the instruction doesn't load at all, it isn't an invariant load.
1201  if (!MCID->mayLoad())
1202    return false;
1203
1204  // If the instruction has lost its memoperands, conservatively assume that
1205  // it may not be an invariant load.
1206  if (memoperands_empty())
1207    return false;
1208
1209  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1210
1211  for (mmo_iterator I = memoperands_begin(),
1212       E = memoperands_end(); I != E; ++I) {
1213    if ((*I)->isVolatile()) return false;
1214    if ((*I)->isStore()) return false;
1215
1216    if (const Value *V = (*I)->getValue()) {
1217      // A load from a constant PseudoSourceValue is invariant.
1218      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1219        if (PSV->isConstant(MFI))
1220          continue;
1221      // If we have an AliasAnalysis, ask it whether the memory is constant.
1222      if (AA && AA->pointsToConstantMemory(
1223                      AliasAnalysis::Location(V, (*I)->getSize(),
1224                                              (*I)->getTBAAInfo())))
1225        continue;
1226    }
1227
1228    // Otherwise assume conservatively.
1229    return false;
1230  }
1231
1232  // Everything checks out.
1233  return true;
1234}
1235
1236/// isConstantValuePHI - If the specified instruction is a PHI that always
1237/// merges together the same virtual register, return the register, otherwise
1238/// return 0.
1239unsigned MachineInstr::isConstantValuePHI() const {
1240  if (!isPHI())
1241    return 0;
1242  assert(getNumOperands() >= 3 &&
1243         "It's illegal to have a PHI without source operands");
1244
1245  unsigned Reg = getOperand(1).getReg();
1246  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1247    if (getOperand(i).getReg() != Reg)
1248      return 0;
1249  return Reg;
1250}
1251
1252bool MachineInstr::hasUnmodeledSideEffects() const {
1253  if (getDesc().hasUnmodeledSideEffects())
1254    return true;
1255  if (isInlineAsm()) {
1256    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1257    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1258      return true;
1259  }
1260
1261  return false;
1262}
1263
1264/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1265///
1266bool MachineInstr::allDefsAreDead() const {
1267  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1268    const MachineOperand &MO = getOperand(i);
1269    if (!MO.isReg() || MO.isUse())
1270      continue;
1271    if (!MO.isDead())
1272      return false;
1273  }
1274  return true;
1275}
1276
1277/// copyImplicitOps - Copy implicit register operands from specified
1278/// instruction to this instruction.
1279void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1280  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1281       i != e; ++i) {
1282    const MachineOperand &MO = MI->getOperand(i);
1283    if (MO.isReg() && MO.isImplicit())
1284      addOperand(MO);
1285  }
1286}
1287
1288void MachineInstr::dump() const {
1289  dbgs() << "  " << *this;
1290}
1291
1292static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1293                         raw_ostream &CommentOS) {
1294  const LLVMContext &Ctx = MF->getFunction()->getContext();
1295  if (!DL.isUnknown()) {          // Print source line info.
1296    DIScope Scope(DL.getScope(Ctx));
1297    // Omit the directory, because it's likely to be long and uninteresting.
1298    if (Scope.Verify())
1299      CommentOS << Scope.getFilename();
1300    else
1301      CommentOS << "<unknown>";
1302    CommentOS << ':' << DL.getLine();
1303    if (DL.getCol() != 0)
1304      CommentOS << ':' << DL.getCol();
1305    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1306    if (!InlinedAtDL.isUnknown()) {
1307      CommentOS << " @[ ";
1308      printDebugLoc(InlinedAtDL, MF, CommentOS);
1309      CommentOS << " ]";
1310    }
1311  }
1312}
1313
1314void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1315  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1316  const MachineFunction *MF = 0;
1317  const MachineRegisterInfo *MRI = 0;
1318  if (const MachineBasicBlock *MBB = getParent()) {
1319    MF = MBB->getParent();
1320    if (!TM && MF)
1321      TM = &MF->getTarget();
1322    if (MF)
1323      MRI = &MF->getRegInfo();
1324  }
1325
1326  // Save a list of virtual registers.
1327  SmallVector<unsigned, 8> VirtRegs;
1328
1329  // Print explicitly defined operands on the left of an assignment syntax.
1330  unsigned StartOp = 0, e = getNumOperands();
1331  for (; StartOp < e && getOperand(StartOp).isReg() &&
1332         getOperand(StartOp).isDef() &&
1333         !getOperand(StartOp).isImplicit();
1334       ++StartOp) {
1335    if (StartOp != 0) OS << ", ";
1336    getOperand(StartOp).print(OS, TM);
1337    unsigned Reg = getOperand(StartOp).getReg();
1338    if (TargetRegisterInfo::isVirtualRegister(Reg))
1339      VirtRegs.push_back(Reg);
1340  }
1341
1342  if (StartOp != 0)
1343    OS << " = ";
1344
1345  // Print the opcode name.
1346  OS << getDesc().getName();
1347
1348  // Print the rest of the operands.
1349  bool OmittedAnyCallClobbers = false;
1350  bool FirstOp = true;
1351  unsigned AsmDescOp = ~0u;
1352  unsigned AsmOpCount = 0;
1353
1354  if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1355    // Print asm string.
1356    OS << " ";
1357    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1358
1359    // Print HasSideEffects, IsAlignStack
1360    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1361    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1362      OS << " [sideeffect]";
1363    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1364      OS << " [alignstack]";
1365
1366    StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1367    FirstOp = false;
1368  }
1369
1370
1371  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1372    const MachineOperand &MO = getOperand(i);
1373
1374    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1375      VirtRegs.push_back(MO.getReg());
1376
1377    // Omit call-clobbered registers which aren't used anywhere. This makes
1378    // call instructions much less noisy on targets where calls clobber lots
1379    // of registers. Don't rely on MO.isDead() because we may be called before
1380    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1381    if (MF && getDesc().isCall() &&
1382        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1383      unsigned Reg = MO.getReg();
1384      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1385        const MachineRegisterInfo &MRI = MF->getRegInfo();
1386        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1387          bool HasAliasLive = false;
1388          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1389               unsigned AliasReg = *Alias; ++Alias)
1390            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1391              HasAliasLive = true;
1392              break;
1393            }
1394          if (!HasAliasLive) {
1395            OmittedAnyCallClobbers = true;
1396            continue;
1397          }
1398        }
1399      }
1400    }
1401
1402    if (FirstOp) FirstOp = false; else OS << ",";
1403    OS << " ";
1404    if (i < getDesc().NumOperands) {
1405      const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1406      if (MCOI.isPredicate())
1407        OS << "pred:";
1408      if (MCOI.isOptionalDef())
1409        OS << "opt:";
1410    }
1411    if (isDebugValue() && MO.isMetadata()) {
1412      // Pretty print DBG_VALUE instructions.
1413      const MDNode *MD = MO.getMetadata();
1414      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1415        OS << "!\"" << MDS->getString() << '\"';
1416      else
1417        MO.print(OS, TM);
1418    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1419      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1420    } else if (i == AsmDescOp && MO.isImm()) {
1421      // Pretty print the inline asm operand descriptor.
1422      OS << '$' << AsmOpCount++;
1423      unsigned Flag = MO.getImm();
1424      switch (InlineAsm::getKind(Flag)) {
1425      case InlineAsm::Kind_RegUse:             OS << ":[reguse]"; break;
1426      case InlineAsm::Kind_RegDef:             OS << ":[regdef]"; break;
1427      case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec]"; break;
1428      case InlineAsm::Kind_Clobber:            OS << ":[clobber]"; break;
1429      case InlineAsm::Kind_Imm:                OS << ":[imm]"; break;
1430      case InlineAsm::Kind_Mem:                OS << ":[mem]"; break;
1431      default: OS << ":[??" << InlineAsm::getKind(Flag) << ']'; break;
1432      }
1433
1434      unsigned TiedTo = 0;
1435      if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1436        OS << " [tiedto:$" << TiedTo << ']';
1437
1438      // Compute the index of the next operand descriptor.
1439      AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1440    } else
1441      MO.print(OS, TM);
1442  }
1443
1444  // Briefly indicate whether any call clobbers were omitted.
1445  if (OmittedAnyCallClobbers) {
1446    if (!FirstOp) OS << ",";
1447    OS << " ...";
1448  }
1449
1450  bool HaveSemi = false;
1451  if (Flags) {
1452    if (!HaveSemi) OS << ";"; HaveSemi = true;
1453    OS << " flags: ";
1454
1455    if (Flags & FrameSetup)
1456      OS << "FrameSetup";
1457  }
1458
1459  if (!memoperands_empty()) {
1460    if (!HaveSemi) OS << ";"; HaveSemi = true;
1461
1462    OS << " mem:";
1463    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1464         i != e; ++i) {
1465      OS << **i;
1466      if (llvm::next(i) != e)
1467        OS << " ";
1468    }
1469  }
1470
1471  // Print the regclass of any virtual registers encountered.
1472  if (MRI && !VirtRegs.empty()) {
1473    if (!HaveSemi) OS << ";"; HaveSemi = true;
1474    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1475      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1476      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1477      for (unsigned j = i+1; j != VirtRegs.size();) {
1478        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1479          ++j;
1480          continue;
1481        }
1482        if (VirtRegs[i] != VirtRegs[j])
1483          OS << "," << PrintReg(VirtRegs[j]);
1484        VirtRegs.erase(VirtRegs.begin()+j);
1485      }
1486    }
1487  }
1488
1489  // Print debug location information.
1490  if (isDebugValue() && getOperand(e - 1).isMetadata()) {
1491    if (!HaveSemi) OS << ";"; HaveSemi = true;
1492    DIVariable DV(getOperand(e - 1).getMetadata());
1493    OS << " line no:" <<  DV.getLineNumber();
1494    if (MDNode *InlinedAt = DV.getInlinedAt()) {
1495      DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(InlinedAt);
1496      if (!InlinedAtDL.isUnknown()) {
1497        OS << " inlined @[ ";
1498        printDebugLoc(InlinedAtDL, MF, OS);
1499        OS << " ]";
1500      }
1501    }
1502  } else if (!debugLoc.isUnknown() && MF) {
1503    if (!HaveSemi) OS << ";"; HaveSemi = true;
1504    OS << " dbg:";
1505    printDebugLoc(debugLoc, MF, OS);
1506  }
1507
1508  OS << '\n';
1509}
1510
1511bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1512                                     const TargetRegisterInfo *RegInfo,
1513                                     bool AddIfNotFound) {
1514  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1515  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1516  bool Found = false;
1517  SmallVector<unsigned,4> DeadOps;
1518  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1519    MachineOperand &MO = getOperand(i);
1520    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1521      continue;
1522    unsigned Reg = MO.getReg();
1523    if (!Reg)
1524      continue;
1525
1526    if (Reg == IncomingReg) {
1527      if (!Found) {
1528        if (MO.isKill())
1529          // The register is already marked kill.
1530          return true;
1531        if (isPhysReg && isRegTiedToDefOperand(i))
1532          // Two-address uses of physregs must not be marked kill.
1533          return true;
1534        MO.setIsKill();
1535        Found = true;
1536      }
1537    } else if (hasAliases && MO.isKill() &&
1538               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1539      // A super-register kill already exists.
1540      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1541        return true;
1542      if (RegInfo->isSubRegister(IncomingReg, Reg))
1543        DeadOps.push_back(i);
1544    }
1545  }
1546
1547  // Trim unneeded kill operands.
1548  while (!DeadOps.empty()) {
1549    unsigned OpIdx = DeadOps.back();
1550    if (getOperand(OpIdx).isImplicit())
1551      RemoveOperand(OpIdx);
1552    else
1553      getOperand(OpIdx).setIsKill(false);
1554    DeadOps.pop_back();
1555  }
1556
1557  // If not found, this means an alias of one of the operands is killed. Add a
1558  // new implicit operand if required.
1559  if (!Found && AddIfNotFound) {
1560    addOperand(MachineOperand::CreateReg(IncomingReg,
1561                                         false /*IsDef*/,
1562                                         true  /*IsImp*/,
1563                                         true  /*IsKill*/));
1564    return true;
1565  }
1566  return Found;
1567}
1568
1569bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1570                                   const TargetRegisterInfo *RegInfo,
1571                                   bool AddIfNotFound) {
1572  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1573  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1574  bool Found = false;
1575  SmallVector<unsigned,4> DeadOps;
1576  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1577    MachineOperand &MO = getOperand(i);
1578    if (!MO.isReg() || !MO.isDef())
1579      continue;
1580    unsigned Reg = MO.getReg();
1581    if (!Reg)
1582      continue;
1583
1584    if (Reg == IncomingReg) {
1585      MO.setIsDead();
1586      Found = true;
1587    } else if (hasAliases && MO.isDead() &&
1588               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1589      // There exists a super-register that's marked dead.
1590      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1591        return true;
1592      if (RegInfo->getSubRegisters(IncomingReg) &&
1593          RegInfo->getSuperRegisters(Reg) &&
1594          RegInfo->isSubRegister(IncomingReg, Reg))
1595        DeadOps.push_back(i);
1596    }
1597  }
1598
1599  // Trim unneeded dead operands.
1600  while (!DeadOps.empty()) {
1601    unsigned OpIdx = DeadOps.back();
1602    if (getOperand(OpIdx).isImplicit())
1603      RemoveOperand(OpIdx);
1604    else
1605      getOperand(OpIdx).setIsDead(false);
1606    DeadOps.pop_back();
1607  }
1608
1609  // If not found, this means an alias of one of the operands is dead. Add a
1610  // new implicit operand if required.
1611  if (Found || !AddIfNotFound)
1612    return Found;
1613
1614  addOperand(MachineOperand::CreateReg(IncomingReg,
1615                                       true  /*IsDef*/,
1616                                       true  /*IsImp*/,
1617                                       false /*IsKill*/,
1618                                       true  /*IsDead*/));
1619  return true;
1620}
1621
1622void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1623                                      const TargetRegisterInfo *RegInfo) {
1624  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1625    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1626    if (MO)
1627      return;
1628  } else {
1629    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1630      const MachineOperand &MO = getOperand(i);
1631      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1632          MO.getSubReg() == 0)
1633        return;
1634    }
1635  }
1636  addOperand(MachineOperand::CreateReg(IncomingReg,
1637                                       true  /*IsDef*/,
1638                                       true  /*IsImp*/));
1639}
1640
1641void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1642                                         const TargetRegisterInfo &TRI) {
1643  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1644    MachineOperand &MO = getOperand(i);
1645    if (!MO.isReg() || !MO.isDef()) continue;
1646    unsigned Reg = MO.getReg();
1647    if (Reg == 0) continue;
1648    bool Dead = true;
1649    for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1650         E = UsedRegs.end(); I != E; ++I)
1651      if (TRI.regsOverlap(*I, Reg)) {
1652        Dead = false;
1653        break;
1654      }
1655    // If there are no uses, including partial uses, the def is dead.
1656    if (Dead) MO.setIsDead();
1657  }
1658}
1659
1660unsigned
1661MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1662  unsigned Hash = MI->getOpcode() * 37;
1663  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1664    const MachineOperand &MO = MI->getOperand(i);
1665    uint64_t Key = (uint64_t)MO.getType() << 32;
1666    switch (MO.getType()) {
1667    default: break;
1668    case MachineOperand::MO_Register:
1669      if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1670        continue;  // Skip virtual register defs.
1671      Key |= MO.getReg();
1672      break;
1673    case MachineOperand::MO_Immediate:
1674      Key |= MO.getImm();
1675      break;
1676    case MachineOperand::MO_FrameIndex:
1677    case MachineOperand::MO_ConstantPoolIndex:
1678    case MachineOperand::MO_JumpTableIndex:
1679      Key |= MO.getIndex();
1680      break;
1681    case MachineOperand::MO_MachineBasicBlock:
1682      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1683      break;
1684    case MachineOperand::MO_GlobalAddress:
1685      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1686      break;
1687    case MachineOperand::MO_BlockAddress:
1688      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1689      break;
1690    case MachineOperand::MO_MCSymbol:
1691      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1692      break;
1693    }
1694    Key += ~(Key << 32);
1695    Key ^= (Key >> 22);
1696    Key += ~(Key << 13);
1697    Key ^= (Key >> 8);
1698    Key += (Key << 3);
1699    Key ^= (Key >> 15);
1700    Key += ~(Key << 27);
1701    Key ^= (Key >> 31);
1702    Hash = (unsigned)Key + Hash * 37;
1703  }
1704  return Hash;
1705}
1706
1707void MachineInstr::emitError(StringRef Msg) const {
1708  // Find the source location cookie.
1709  unsigned LocCookie = 0;
1710  const MDNode *LocMD = 0;
1711  for (unsigned i = getNumOperands(); i != 0; --i) {
1712    if (getOperand(i-1).isMetadata() &&
1713        (LocMD = getOperand(i-1).getMetadata()) &&
1714        LocMD->getNumOperands() != 0) {
1715      if (const ConstantInt *CI = dyn_cast<ConstantInt>(LocMD->getOperand(0))) {
1716        LocCookie = CI->getZExtValue();
1717        break;
1718      }
1719    }
1720  }
1721
1722  if (const MachineBasicBlock *MBB = getParent())
1723    if (const MachineFunction *MF = MBB->getParent())
1724      return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1725  report_fatal_error(Msg);
1726}
1727