MachineInstr.cpp revision d65ba721cccb0d0998750908bf2533e08b106f38 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/Metadata.h"
19#include "llvm/Type.h"
20#include "llvm/Value.h"
21#include "llvm/Assembly/Writer.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetInstrDesc.h"
31#include "llvm/Target/TargetRegisterInfo.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/DebugInfo.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/FoldingSet.h"
40using namespace llvm;
41
42//===----------------------------------------------------------------------===//
43// MachineOperand Implementation
44//===----------------------------------------------------------------------===//
45
46/// AddRegOperandToRegInfo - Add this register operand to the specified
47/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
48/// explicitly nulled out.
49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50  assert(isReg() && "Can only add reg operand to use lists");
51
52  // If the reginfo pointer is null, just explicitly null out or next/prev
53  // pointers, to ensure they are not garbage.
54  if (RegInfo == 0) {
55    Contents.Reg.Prev = 0;
56    Contents.Reg.Next = 0;
57    return;
58  }
59
60  // Otherwise, add this operand to the head of the registers use/def list.
61  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
62
63  // For SSA values, we prefer to keep the definition at the start of the list.
64  // we do this by skipping over the definition if it is at the head of the
65  // list.
66  if (*Head && (*Head)->isDef())
67    Head = &(*Head)->Contents.Reg.Next;
68
69  Contents.Reg.Next = *Head;
70  if (Contents.Reg.Next) {
71    assert(getReg() == Contents.Reg.Next->getReg() &&
72           "Different regs on the same list!");
73    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
74  }
75
76  Contents.Reg.Prev = Head;
77  *Head = this;
78}
79
80/// RemoveRegOperandFromRegInfo - Remove this register operand from the
81/// MachineRegisterInfo it is linked with.
82void MachineOperand::RemoveRegOperandFromRegInfo() {
83  assert(isOnRegUseList() && "Reg operand is not on a use list");
84  // Unlink this from the doubly linked list of operands.
85  MachineOperand *NextOp = Contents.Reg.Next;
86  *Contents.Reg.Prev = NextOp;
87  if (NextOp) {
88    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90  }
91  Contents.Reg.Prev = 0;
92  Contents.Reg.Next = 0;
93}
94
95void MachineOperand::setReg(unsigned Reg) {
96  if (getReg() == Reg) return; // No change.
97
98  // Otherwise, we have to change the register.  If this operand is embedded
99  // into a machine function, we need to update the old and new register's
100  // use/def lists.
101  if (MachineInstr *MI = getParent())
102    if (MachineBasicBlock *MBB = MI->getParent())
103      if (MachineFunction *MF = MBB->getParent()) {
104        RemoveRegOperandFromRegInfo();
105        SmallContents.RegNo = Reg;
106        AddRegOperandToRegInfo(&MF->getRegInfo());
107        return;
108      }
109
110  // Otherwise, just change the register, no problem.  :)
111  SmallContents.RegNo = Reg;
112}
113
114void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
115                                  const TargetRegisterInfo &TRI) {
116  assert(TargetRegisterInfo::isVirtualRegister(Reg));
117  if (SubIdx && getSubReg())
118    SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
119  setReg(Reg);
120  if (SubIdx)
121    setSubReg(SubIdx);
122}
123
124void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
125  assert(TargetRegisterInfo::isPhysicalRegister(Reg));
126  if (getSubReg()) {
127    Reg = TRI.getSubReg(Reg, getSubReg());
128    assert(Reg && "Invalid SubReg for physical register");
129    setSubReg(0);
130  }
131  setReg(Reg);
132}
133
134/// ChangeToImmediate - Replace this operand with a new immediate operand of
135/// the specified value.  If an operand is known to be an immediate already,
136/// the setImm method should be used.
137void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
138  // If this operand is currently a register operand, and if this is in a
139  // function, deregister the operand from the register's use/def list.
140  if (isReg() && getParent() && getParent()->getParent() &&
141      getParent()->getParent()->getParent())
142    RemoveRegOperandFromRegInfo();
143
144  OpKind = MO_Immediate;
145  Contents.ImmVal = ImmVal;
146}
147
148/// ChangeToRegister - Replace this operand with a new register operand of
149/// the specified value.  If an operand is known to be an register already,
150/// the setReg method should be used.
151void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
152                                      bool isKill, bool isDead, bool isUndef,
153                                      bool isDebug) {
154  // If this operand is already a register operand, use setReg to update the
155  // register's use/def lists.
156  if (isReg()) {
157    assert(!isEarlyClobber());
158    setReg(Reg);
159  } else {
160    // Otherwise, change this to a register and set the reg#.
161    OpKind = MO_Register;
162    SmallContents.RegNo = Reg;
163
164    // If this operand is embedded in a function, add the operand to the
165    // register's use/def list.
166    if (MachineInstr *MI = getParent())
167      if (MachineBasicBlock *MBB = MI->getParent())
168        if (MachineFunction *MF = MBB->getParent())
169          AddRegOperandToRegInfo(&MF->getRegInfo());
170  }
171
172  IsDef = isDef;
173  IsImp = isImp;
174  IsKill = isKill;
175  IsDead = isDead;
176  IsUndef = isUndef;
177  IsEarlyClobber = false;
178  IsDebug = isDebug;
179  SubReg = 0;
180}
181
182/// isIdenticalTo - Return true if this operand is identical to the specified
183/// operand.
184bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
185  if (getType() != Other.getType() ||
186      getTargetFlags() != Other.getTargetFlags())
187    return false;
188
189  switch (getType()) {
190  default: llvm_unreachable("Unrecognized operand type");
191  case MachineOperand::MO_Register:
192    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
193           getSubReg() == Other.getSubReg();
194  case MachineOperand::MO_Immediate:
195    return getImm() == Other.getImm();
196  case MachineOperand::MO_FPImmediate:
197    return getFPImm() == Other.getFPImm();
198  case MachineOperand::MO_MachineBasicBlock:
199    return getMBB() == Other.getMBB();
200  case MachineOperand::MO_FrameIndex:
201    return getIndex() == Other.getIndex();
202  case MachineOperand::MO_ConstantPoolIndex:
203    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
204  case MachineOperand::MO_JumpTableIndex:
205    return getIndex() == Other.getIndex();
206  case MachineOperand::MO_GlobalAddress:
207    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
208  case MachineOperand::MO_ExternalSymbol:
209    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
210           getOffset() == Other.getOffset();
211  case MachineOperand::MO_BlockAddress:
212    return getBlockAddress() == Other.getBlockAddress();
213  case MachineOperand::MO_MCSymbol:
214    return getMCSymbol() == Other.getMCSymbol();
215  case MachineOperand::MO_Metadata:
216    return getMetadata() == Other.getMetadata();
217  }
218}
219
220/// print - Print the specified machine operand.
221///
222void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
223  // If the instruction is embedded into a basic block, we can find the
224  // target info for the instruction.
225  if (!TM)
226    if (const MachineInstr *MI = getParent())
227      if (const MachineBasicBlock *MBB = MI->getParent())
228        if (const MachineFunction *MF = MBB->getParent())
229          TM = &MF->getTarget();
230  const TargetRegisterInfo *TRI = TM ? TM->getRegisterInfo() : 0;
231
232  switch (getType()) {
233  case MachineOperand::MO_Register:
234    OS << PrintReg(getReg(), TRI, getSubReg());
235
236    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
237        isEarlyClobber()) {
238      OS << '<';
239      bool NeedComma = false;
240      if (isDef()) {
241        if (NeedComma) OS << ',';
242        if (isEarlyClobber())
243          OS << "earlyclobber,";
244        if (isImplicit())
245          OS << "imp-";
246        OS << "def";
247        NeedComma = true;
248      } else if (isImplicit()) {
249          OS << "imp-use";
250          NeedComma = true;
251      }
252
253      if (isKill() || isDead() || isUndef()) {
254        if (NeedComma) OS << ',';
255        if (isKill())  OS << "kill";
256        if (isDead())  OS << "dead";
257        if (isUndef()) {
258          if (isKill() || isDead())
259            OS << ',';
260          OS << "undef";
261        }
262      }
263      OS << '>';
264    }
265    break;
266  case MachineOperand::MO_Immediate:
267    OS << getImm();
268    break;
269  case MachineOperand::MO_FPImmediate:
270    if (getFPImm()->getType()->isFloatTy())
271      OS << getFPImm()->getValueAPF().convertToFloat();
272    else
273      OS << getFPImm()->getValueAPF().convertToDouble();
274    break;
275  case MachineOperand::MO_MachineBasicBlock:
276    OS << "<BB#" << getMBB()->getNumber() << ">";
277    break;
278  case MachineOperand::MO_FrameIndex:
279    OS << "<fi#" << getIndex() << '>';
280    break;
281  case MachineOperand::MO_ConstantPoolIndex:
282    OS << "<cp#" << getIndex();
283    if (getOffset()) OS << "+" << getOffset();
284    OS << '>';
285    break;
286  case MachineOperand::MO_JumpTableIndex:
287    OS << "<jt#" << getIndex() << '>';
288    break;
289  case MachineOperand::MO_GlobalAddress:
290    OS << "<ga:";
291    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
292    if (getOffset()) OS << "+" << getOffset();
293    OS << '>';
294    break;
295  case MachineOperand::MO_ExternalSymbol:
296    OS << "<es:" << getSymbolName();
297    if (getOffset()) OS << "+" << getOffset();
298    OS << '>';
299    break;
300  case MachineOperand::MO_BlockAddress:
301    OS << '<';
302    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
303    OS << '>';
304    break;
305  case MachineOperand::MO_Metadata:
306    OS << '<';
307    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
308    OS << '>';
309    break;
310  case MachineOperand::MO_MCSymbol:
311    OS << "<MCSym=" << *getMCSymbol() << '>';
312    break;
313  default:
314    llvm_unreachable("Unrecognized operand type");
315  }
316
317  if (unsigned TF = getTargetFlags())
318    OS << "[TF=" << TF << ']';
319}
320
321//===----------------------------------------------------------------------===//
322// MachineMemOperand Implementation
323//===----------------------------------------------------------------------===//
324
325/// getAddrSpace - Return the LLVM IR address space number that this pointer
326/// points into.
327unsigned MachinePointerInfo::getAddrSpace() const {
328  if (V == 0) return 0;
329  return cast<PointerType>(V->getType())->getAddressSpace();
330}
331
332/// getConstantPool - Return a MachinePointerInfo record that refers to the
333/// constant pool.
334MachinePointerInfo MachinePointerInfo::getConstantPool() {
335  return MachinePointerInfo(PseudoSourceValue::getConstantPool());
336}
337
338/// getFixedStack - Return a MachinePointerInfo record that refers to the
339/// the specified FrameIndex.
340MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
341  return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
342}
343
344MachinePointerInfo MachinePointerInfo::getJumpTable() {
345  return MachinePointerInfo(PseudoSourceValue::getJumpTable());
346}
347
348MachinePointerInfo MachinePointerInfo::getGOT() {
349  return MachinePointerInfo(PseudoSourceValue::getGOT());
350}
351
352MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
353  return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
354}
355
356MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
357                                     uint64_t s, unsigned int a,
358                                     const MDNode *TBAAInfo)
359  : PtrInfo(ptrinfo), Size(s),
360    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
361    TBAAInfo(TBAAInfo) {
362  assert((PtrInfo.V == 0 || isa<PointerType>(PtrInfo.V->getType())) &&
363         "invalid pointer value");
364  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
365  assert((isLoad() || isStore()) && "Not a load/store!");
366}
367
368/// Profile - Gather unique data for the object.
369///
370void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
371  ID.AddInteger(getOffset());
372  ID.AddInteger(Size);
373  ID.AddPointer(getValue());
374  ID.AddInteger(Flags);
375}
376
377void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
378  // The Value and Offset may differ due to CSE. But the flags and size
379  // should be the same.
380  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
381  assert(MMO->getSize() == getSize() && "Size mismatch!");
382
383  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
384    // Update the alignment value.
385    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
386      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
387    // Also update the base and offset, because the new alignment may
388    // not be applicable with the old ones.
389    PtrInfo = MMO->PtrInfo;
390  }
391}
392
393/// getAlignment - Return the minimum known alignment in bytes of the
394/// actual memory reference.
395uint64_t MachineMemOperand::getAlignment() const {
396  return MinAlign(getBaseAlignment(), getOffset());
397}
398
399raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
400  assert((MMO.isLoad() || MMO.isStore()) &&
401         "SV has to be a load, store or both.");
402
403  if (MMO.isVolatile())
404    OS << "Volatile ";
405
406  if (MMO.isLoad())
407    OS << "LD";
408  if (MMO.isStore())
409    OS << "ST";
410  OS << MMO.getSize();
411
412  // Print the address information.
413  OS << "[";
414  if (!MMO.getValue())
415    OS << "<unknown>";
416  else
417    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
418
419  // If the alignment of the memory reference itself differs from the alignment
420  // of the base pointer, print the base alignment explicitly, next to the base
421  // pointer.
422  if (MMO.getBaseAlignment() != MMO.getAlignment())
423    OS << "(align=" << MMO.getBaseAlignment() << ")";
424
425  if (MMO.getOffset() != 0)
426    OS << "+" << MMO.getOffset();
427  OS << "]";
428
429  // Print the alignment of the reference.
430  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
431      MMO.getBaseAlignment() != MMO.getSize())
432    OS << "(align=" << MMO.getAlignment() << ")";
433
434  // Print TBAA info.
435  if (const MDNode *TBAAInfo = MMO.getTBAAInfo()) {
436    OS << "(tbaa=";
437    if (TBAAInfo->getNumOperands() > 0)
438      WriteAsOperand(OS, TBAAInfo->getOperand(0), /*PrintType=*/false);
439    else
440      OS << "<unknown>";
441    OS << ")";
442  }
443
444  // Print nontemporal info.
445  if (MMO.isNonTemporal())
446    OS << "(nontemporal)";
447
448  return OS;
449}
450
451//===----------------------------------------------------------------------===//
452// MachineInstr Implementation
453//===----------------------------------------------------------------------===//
454
455/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
456/// TID NULL and no operands.
457MachineInstr::MachineInstr()
458  : TID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
459    MemRefs(0), MemRefsEnd(0),
460    Parent(0) {
461  // Make sure that we get added to a machine basicblock
462  LeakDetector::addGarbageObject(this);
463}
464
465void MachineInstr::addImplicitDefUseOperands() {
466  if (TID->ImplicitDefs)
467    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
468      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
469  if (TID->ImplicitUses)
470    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
471      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
472}
473
474/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
475/// implicit operands. It reserves space for the number of operands specified by
476/// the TargetInstrDesc.
477MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
478  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
479    MemRefs(0), MemRefsEnd(0), Parent(0) {
480  if (!NoImp)
481    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
482  Operands.reserve(NumImplicitOps + TID->getNumOperands());
483  if (!NoImp)
484    addImplicitDefUseOperands();
485  // Make sure that we get added to a machine basicblock
486  LeakDetector::addGarbageObject(this);
487}
488
489/// MachineInstr ctor - As above, but with a DebugLoc.
490MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
491                           bool NoImp)
492  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
493    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
494  if (!NoImp)
495    NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
496  Operands.reserve(NumImplicitOps + TID->getNumOperands());
497  if (!NoImp)
498    addImplicitDefUseOperands();
499  // Make sure that we get added to a machine basicblock
500  LeakDetector::addGarbageObject(this);
501}
502
503/// MachineInstr ctor - Work exactly the same as the ctor two above, except
504/// that the MachineInstr is created and added to the end of the specified
505/// basic block.
506MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
507  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
508    MemRefs(0), MemRefsEnd(0), Parent(0) {
509  assert(MBB && "Cannot use inserting ctor with null basic block!");
510  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
511  Operands.reserve(NumImplicitOps + TID->getNumOperands());
512  addImplicitDefUseOperands();
513  // Make sure that we get added to a machine basicblock
514  LeakDetector::addGarbageObject(this);
515  MBB->push_back(this);  // Add instruction to end of basic block!
516}
517
518/// MachineInstr ctor - As above, but with a DebugLoc.
519///
520MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
521                           const TargetInstrDesc &tid)
522  : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
523    MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) {
524  assert(MBB && "Cannot use inserting ctor with null basic block!");
525  NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses();
526  Operands.reserve(NumImplicitOps + TID->getNumOperands());
527  addImplicitDefUseOperands();
528  // Make sure that we get added to a machine basicblock
529  LeakDetector::addGarbageObject(this);
530  MBB->push_back(this);  // Add instruction to end of basic block!
531}
532
533/// MachineInstr ctor - Copies MachineInstr arg exactly
534///
535MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
536  : TID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0),
537    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
538    Parent(0), debugLoc(MI.getDebugLoc()) {
539  Operands.reserve(MI.getNumOperands());
540
541  // Add operands
542  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
543    addOperand(MI.getOperand(i));
544  NumImplicitOps = MI.NumImplicitOps;
545
546  // Copy all the flags.
547  Flags = MI.Flags;
548
549  // Set parent to null.
550  Parent = 0;
551
552  LeakDetector::addGarbageObject(this);
553}
554
555MachineInstr::~MachineInstr() {
556  LeakDetector::removeGarbageObject(this);
557#ifndef NDEBUG
558  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
559    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
560    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
561           "Reg operand def/use list corrupted");
562  }
563#endif
564}
565
566/// getRegInfo - If this instruction is embedded into a MachineFunction,
567/// return the MachineRegisterInfo object for the current function, otherwise
568/// return null.
569MachineRegisterInfo *MachineInstr::getRegInfo() {
570  if (MachineBasicBlock *MBB = getParent())
571    return &MBB->getParent()->getRegInfo();
572  return 0;
573}
574
575/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
576/// this instruction from their respective use lists.  This requires that the
577/// operands already be on their use lists.
578void MachineInstr::RemoveRegOperandsFromUseLists() {
579  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
580    if (Operands[i].isReg())
581      Operands[i].RemoveRegOperandFromRegInfo();
582  }
583}
584
585/// AddRegOperandsToUseLists - Add all of the register operands in
586/// this instruction from their respective use lists.  This requires that the
587/// operands not be on their use lists yet.
588void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
589  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
590    if (Operands[i].isReg())
591      Operands[i].AddRegOperandToRegInfo(&RegInfo);
592  }
593}
594
595
596/// addOperand - Add the specified operand to the instruction.  If it is an
597/// implicit operand, it is added to the end of the operand list.  If it is
598/// an explicit operand it is added at the end of the explicit operand list
599/// (before the first implicit operand).
600void MachineInstr::addOperand(const MachineOperand &Op) {
601  bool isImpReg = Op.isReg() && Op.isImplicit();
602  assert((isImpReg || !OperandsComplete()) &&
603         "Trying to add an operand to a machine instr that is already done!");
604
605  MachineRegisterInfo *RegInfo = getRegInfo();
606
607  // If we are adding the operand to the end of the list, our job is simpler.
608  // This is true most of the time, so this is a reasonable optimization.
609  if (isImpReg || NumImplicitOps == 0) {
610    // We can only do this optimization if we know that the operand list won't
611    // reallocate.
612    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
613      Operands.push_back(Op);
614
615      // Set the parent of the operand.
616      Operands.back().ParentMI = this;
617
618      // If the operand is a register, update the operand's use list.
619      if (Op.isReg()) {
620        Operands.back().AddRegOperandToRegInfo(RegInfo);
621        // If the register operand is flagged as early, mark the operand as such
622        unsigned OpNo = Operands.size() - 1;
623        if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
624          Operands[OpNo].setIsEarlyClobber(true);
625      }
626      return;
627    }
628  }
629
630  // Otherwise, we have to insert a real operand before any implicit ones.
631  unsigned OpNo = Operands.size()-NumImplicitOps;
632
633  // If this instruction isn't embedded into a function, then we don't need to
634  // update any operand lists.
635  if (RegInfo == 0) {
636    // Simple insertion, no reginfo update needed for other register operands.
637    Operands.insert(Operands.begin()+OpNo, Op);
638    Operands[OpNo].ParentMI = this;
639
640    // Do explicitly set the reginfo for this operand though, to ensure the
641    // next/prev fields are properly nulled out.
642    if (Operands[OpNo].isReg()) {
643      Operands[OpNo].AddRegOperandToRegInfo(0);
644      // If the register operand is flagged as early, mark the operand as such
645      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
646        Operands[OpNo].setIsEarlyClobber(true);
647    }
648
649  } else if (Operands.size()+1 <= Operands.capacity()) {
650    // Otherwise, we have to remove register operands from their register use
651    // list, add the operand, then add the register operands back to their use
652    // list.  This also must handle the case when the operand list reallocates
653    // to somewhere else.
654
655    // If insertion of this operand won't cause reallocation of the operand
656    // list, just remove the implicit operands, add the operand, then re-add all
657    // the rest of the operands.
658    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
659      assert(Operands[i].isReg() && "Should only be an implicit reg!");
660      Operands[i].RemoveRegOperandFromRegInfo();
661    }
662
663    // Add the operand.  If it is a register, add it to the reg list.
664    Operands.insert(Operands.begin()+OpNo, Op);
665    Operands[OpNo].ParentMI = this;
666
667    if (Operands[OpNo].isReg()) {
668      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
669      // If the register operand is flagged as early, mark the operand as such
670      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
671        Operands[OpNo].setIsEarlyClobber(true);
672    }
673
674    // Re-add all the implicit ops.
675    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
676      assert(Operands[i].isReg() && "Should only be an implicit reg!");
677      Operands[i].AddRegOperandToRegInfo(RegInfo);
678    }
679  } else {
680    // Otherwise, we will be reallocating the operand list.  Remove all reg
681    // operands from their list, then readd them after the operand list is
682    // reallocated.
683    RemoveRegOperandsFromUseLists();
684
685    Operands.insert(Operands.begin()+OpNo, Op);
686    Operands[OpNo].ParentMI = this;
687
688    // Re-add all the operands.
689    AddRegOperandsToUseLists(*RegInfo);
690
691      // If the register operand is flagged as early, mark the operand as such
692    if (Operands[OpNo].isReg()
693        && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
694      Operands[OpNo].setIsEarlyClobber(true);
695  }
696}
697
698/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
699/// fewer operand than it started with.
700///
701void MachineInstr::RemoveOperand(unsigned OpNo) {
702  assert(OpNo < Operands.size() && "Invalid operand number");
703
704  // Special case removing the last one.
705  if (OpNo == Operands.size()-1) {
706    // If needed, remove from the reg def/use list.
707    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
708      Operands.back().RemoveRegOperandFromRegInfo();
709
710    Operands.pop_back();
711    return;
712  }
713
714  // Otherwise, we are removing an interior operand.  If we have reginfo to
715  // update, remove all operands that will be shifted down from their reg lists,
716  // move everything down, then re-add them.
717  MachineRegisterInfo *RegInfo = getRegInfo();
718  if (RegInfo) {
719    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
720      if (Operands[i].isReg())
721        Operands[i].RemoveRegOperandFromRegInfo();
722    }
723  }
724
725  Operands.erase(Operands.begin()+OpNo);
726
727  if (RegInfo) {
728    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
729      if (Operands[i].isReg())
730        Operands[i].AddRegOperandToRegInfo(RegInfo);
731    }
732  }
733}
734
735/// addMemOperand - Add a MachineMemOperand to the machine instruction.
736/// This function should be used only occasionally. The setMemRefs function
737/// is the primary method for setting up a MachineInstr's MemRefs list.
738void MachineInstr::addMemOperand(MachineFunction &MF,
739                                 MachineMemOperand *MO) {
740  mmo_iterator OldMemRefs = MemRefs;
741  mmo_iterator OldMemRefsEnd = MemRefsEnd;
742
743  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
744  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
745  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
746
747  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
748  NewMemRefs[NewNum - 1] = MO;
749
750  MemRefs = NewMemRefs;
751  MemRefsEnd = NewMemRefsEnd;
752}
753
754bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
755                                 MICheckType Check) const {
756  // If opcodes or number of operands are not the same then the two
757  // instructions are obviously not identical.
758  if (Other->getOpcode() != getOpcode() ||
759      Other->getNumOperands() != getNumOperands())
760    return false;
761
762  // Check operands to make sure they match.
763  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
764    const MachineOperand &MO = getOperand(i);
765    const MachineOperand &OMO = Other->getOperand(i);
766    // Clients may or may not want to ignore defs when testing for equality.
767    // For example, machine CSE pass only cares about finding common
768    // subexpressions, so it's safe to ignore virtual register defs.
769    if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
770      if (Check == IgnoreDefs)
771        continue;
772      // Check == IgnoreVRegDefs
773      if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
774          TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
775        if (MO.getReg() != OMO.getReg())
776          return false;
777    } else if (!MO.isIdenticalTo(OMO))
778      return false;
779  }
780  return true;
781}
782
783/// removeFromParent - This method unlinks 'this' from the containing basic
784/// block, and returns it, but does not delete it.
785MachineInstr *MachineInstr::removeFromParent() {
786  assert(getParent() && "Not embedded in a basic block!");
787  getParent()->remove(this);
788  return this;
789}
790
791
792/// eraseFromParent - This method unlinks 'this' from the containing basic
793/// block, and deletes it.
794void MachineInstr::eraseFromParent() {
795  assert(getParent() && "Not embedded in a basic block!");
796  getParent()->erase(this);
797}
798
799
800/// OperandComplete - Return true if it's illegal to add a new operand
801///
802bool MachineInstr::OperandsComplete() const {
803  unsigned short NumOperands = TID->getNumOperands();
804  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
805    return true;  // Broken: we have all the operands of this instruction!
806  return false;
807}
808
809/// getNumExplicitOperands - Returns the number of non-implicit operands.
810///
811unsigned MachineInstr::getNumExplicitOperands() const {
812  unsigned NumOperands = TID->getNumOperands();
813  if (!TID->isVariadic())
814    return NumOperands;
815
816  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
817    const MachineOperand &MO = getOperand(i);
818    if (!MO.isReg() || !MO.isImplicit())
819      NumOperands++;
820  }
821  return NumOperands;
822}
823
824bool MachineInstr::isStackAligningInlineAsm() const {
825  if (isInlineAsm()) {
826    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
827    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
828      return true;
829  }
830  return false;
831}
832
833/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
834/// the specific register or -1 if it is not found. It further tightens
835/// the search criteria to a use that kills the register if isKill is true.
836int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
837                                          const TargetRegisterInfo *TRI) const {
838  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
839    const MachineOperand &MO = getOperand(i);
840    if (!MO.isReg() || !MO.isUse())
841      continue;
842    unsigned MOReg = MO.getReg();
843    if (!MOReg)
844      continue;
845    if (MOReg == Reg ||
846        (TRI &&
847         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
848         TargetRegisterInfo::isPhysicalRegister(Reg) &&
849         TRI->isSubRegister(MOReg, Reg)))
850      if (!isKill || MO.isKill())
851        return i;
852  }
853  return -1;
854}
855
856/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
857/// indicating if this instruction reads or writes Reg. This also considers
858/// partial defines.
859std::pair<bool,bool>
860MachineInstr::readsWritesVirtualRegister(unsigned Reg,
861                                         SmallVectorImpl<unsigned> *Ops) const {
862  bool PartDef = false; // Partial redefine.
863  bool FullDef = false; // Full define.
864  bool Use = false;
865
866  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
867    const MachineOperand &MO = getOperand(i);
868    if (!MO.isReg() || MO.getReg() != Reg)
869      continue;
870    if (Ops)
871      Ops->push_back(i);
872    if (MO.isUse())
873      Use |= !MO.isUndef();
874    else if (MO.getSubReg())
875      PartDef = true;
876    else
877      FullDef = true;
878  }
879  // A partial redefine uses Reg unless there is also a full define.
880  return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
881}
882
883/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
884/// the specified register or -1 if it is not found. If isDead is true, defs
885/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
886/// also checks if there is a def of a super-register.
887int
888MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
889                                        const TargetRegisterInfo *TRI) const {
890  bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
891  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
892    const MachineOperand &MO = getOperand(i);
893    if (!MO.isReg() || !MO.isDef())
894      continue;
895    unsigned MOReg = MO.getReg();
896    bool Found = (MOReg == Reg);
897    if (!Found && TRI && isPhys &&
898        TargetRegisterInfo::isPhysicalRegister(MOReg)) {
899      if (Overlap)
900        Found = TRI->regsOverlap(MOReg, Reg);
901      else
902        Found = TRI->isSubRegister(MOReg, Reg);
903    }
904    if (Found && (!isDead || MO.isDead()))
905      return i;
906  }
907  return -1;
908}
909
910/// findFirstPredOperandIdx() - Find the index of the first operand in the
911/// operand list that is used to represent the predicate. It returns -1 if
912/// none is found.
913int MachineInstr::findFirstPredOperandIdx() const {
914  const TargetInstrDesc &TID = getDesc();
915  if (TID.isPredicable()) {
916    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
917      if (TID.OpInfo[i].isPredicate())
918        return i;
919  }
920
921  return -1;
922}
923
924/// isRegTiedToUseOperand - Given the index of a register def operand,
925/// check if the register def is tied to a source operand, due to either
926/// two-address elimination or inline assembly constraints. Returns the
927/// first tied use operand index by reference is UseOpIdx is not null.
928bool MachineInstr::
929isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
930  if (isInlineAsm()) {
931    assert(DefOpIdx > InlineAsm::MIOp_FirstOperand);
932    const MachineOperand &MO = getOperand(DefOpIdx);
933    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
934      return false;
935    // Determine the actual operand index that corresponds to this index.
936    unsigned DefNo = 0;
937    unsigned DefPart = 0;
938    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
939         i < e; ) {
940      const MachineOperand &FMO = getOperand(i);
941      // After the normal asm operands there may be additional imp-def regs.
942      if (!FMO.isImm())
943        return false;
944      // Skip over this def.
945      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
946      unsigned PrevDef = i + 1;
947      i = PrevDef + NumOps;
948      if (i > DefOpIdx) {
949        DefPart = DefOpIdx - PrevDef;
950        break;
951      }
952      ++DefNo;
953    }
954    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands();
955         i != e; ++i) {
956      const MachineOperand &FMO = getOperand(i);
957      if (!FMO.isImm())
958        continue;
959      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
960        continue;
961      unsigned Idx;
962      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
963          Idx == DefNo) {
964        if (UseOpIdx)
965          *UseOpIdx = (unsigned)i + 1 + DefPart;
966        return true;
967      }
968    }
969    return false;
970  }
971
972  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
973  const TargetInstrDesc &TID = getDesc();
974  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
975    const MachineOperand &MO = getOperand(i);
976    if (MO.isReg() && MO.isUse() &&
977        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
978      if (UseOpIdx)
979        *UseOpIdx = (unsigned)i;
980      return true;
981    }
982  }
983  return false;
984}
985
986/// isRegTiedToDefOperand - Return true if the operand of the specified index
987/// is a register use and it is tied to an def operand. It also returns the def
988/// operand index by reference.
989bool MachineInstr::
990isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
991  if (isInlineAsm()) {
992    const MachineOperand &MO = getOperand(UseOpIdx);
993    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
994      return false;
995
996    // Find the flag operand corresponding to UseOpIdx
997    unsigned FlagIdx, NumOps=0;
998    for (FlagIdx = InlineAsm::MIOp_FirstOperand;
999         FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
1000      const MachineOperand &UFMO = getOperand(FlagIdx);
1001      // After the normal asm operands there may be additional imp-def regs.
1002      if (!UFMO.isImm())
1003        return false;
1004      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
1005      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
1006      if (UseOpIdx < FlagIdx+NumOps+1)
1007        break;
1008    }
1009    if (FlagIdx >= UseOpIdx)
1010      return false;
1011    const MachineOperand &UFMO = getOperand(FlagIdx);
1012    unsigned DefNo;
1013    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
1014      if (!DefOpIdx)
1015        return true;
1016
1017      unsigned DefIdx = InlineAsm::MIOp_FirstOperand;
1018      // Remember to adjust the index. First operand is asm string, second is
1019      // the HasSideEffects and AlignStack bits, then there is a flag for each.
1020      while (DefNo) {
1021        const MachineOperand &FMO = getOperand(DefIdx);
1022        assert(FMO.isImm());
1023        // Skip over this def.
1024        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
1025        --DefNo;
1026      }
1027      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
1028      return true;
1029    }
1030    return false;
1031  }
1032
1033  const TargetInstrDesc &TID = getDesc();
1034  if (UseOpIdx >= TID.getNumOperands())
1035    return false;
1036  const MachineOperand &MO = getOperand(UseOpIdx);
1037  if (!MO.isReg() || !MO.isUse())
1038    return false;
1039  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
1040  if (DefIdx == -1)
1041    return false;
1042  if (DefOpIdx)
1043    *DefOpIdx = (unsigned)DefIdx;
1044  return true;
1045}
1046
1047/// clearKillInfo - Clears kill flags on all operands.
1048///
1049void MachineInstr::clearKillInfo() {
1050  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1051    MachineOperand &MO = getOperand(i);
1052    if (MO.isReg() && MO.isUse())
1053      MO.setIsKill(false);
1054  }
1055}
1056
1057/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
1058///
1059void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
1060  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1061    const MachineOperand &MO = MI->getOperand(i);
1062    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
1063      continue;
1064    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
1065      MachineOperand &MOp = getOperand(j);
1066      if (!MOp.isIdenticalTo(MO))
1067        continue;
1068      if (MO.isKill())
1069        MOp.setIsKill();
1070      else
1071        MOp.setIsDead();
1072      break;
1073    }
1074  }
1075}
1076
1077/// copyPredicates - Copies predicate operand(s) from MI.
1078void MachineInstr::copyPredicates(const MachineInstr *MI) {
1079  const TargetInstrDesc &TID = MI->getDesc();
1080  if (!TID.isPredicable())
1081    return;
1082  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1083    if (TID.OpInfo[i].isPredicate()) {
1084      // Predicated operands must be last operands.
1085      addOperand(MI->getOperand(i));
1086    }
1087  }
1088}
1089
1090void MachineInstr::substituteRegister(unsigned FromReg,
1091                                      unsigned ToReg,
1092                                      unsigned SubIdx,
1093                                      const TargetRegisterInfo &RegInfo) {
1094  if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1095    if (SubIdx)
1096      ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1097    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1098      MachineOperand &MO = getOperand(i);
1099      if (!MO.isReg() || MO.getReg() != FromReg)
1100        continue;
1101      MO.substPhysReg(ToReg, RegInfo);
1102    }
1103  } else {
1104    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1105      MachineOperand &MO = getOperand(i);
1106      if (!MO.isReg() || MO.getReg() != FromReg)
1107        continue;
1108      MO.substVirtReg(ToReg, SubIdx, RegInfo);
1109    }
1110  }
1111}
1112
1113/// isSafeToMove - Return true if it is safe to move this instruction. If
1114/// SawStore is set to true, it means that there is a store (or call) between
1115/// the instruction's location and its intended destination.
1116bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
1117                                AliasAnalysis *AA,
1118                                bool &SawStore) const {
1119  // Ignore stuff that we obviously can't move.
1120  if (TID->mayStore() || TID->isCall()) {
1121    SawStore = true;
1122    return false;
1123  }
1124
1125  if (isLabel() || isDebugValue() ||
1126      TID->isTerminator() || hasUnmodeledSideEffects())
1127    return false;
1128
1129  // See if this instruction does a load.  If so, we have to guarantee that the
1130  // loaded value doesn't change between the load and the its intended
1131  // destination. The check for isInvariantLoad gives the targe the chance to
1132  // classify the load as always returning a constant, e.g. a constant pool
1133  // load.
1134  if (TID->mayLoad() && !isInvariantLoad(AA))
1135    // Otherwise, this is a real load.  If there is a store between the load and
1136    // end of block, or if the load is volatile, we can't move it.
1137    return !SawStore && !hasVolatileMemoryRef();
1138
1139  return true;
1140}
1141
1142/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1143/// instruction which defined the specified register instead of copying it.
1144bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1145                                 AliasAnalysis *AA,
1146                                 unsigned DstReg) const {
1147  bool SawStore = false;
1148  if (!TII->isTriviallyReMaterializable(this, AA) ||
1149      !isSafeToMove(TII, AA, SawStore))
1150    return false;
1151  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1152    const MachineOperand &MO = getOperand(i);
1153    if (!MO.isReg())
1154      continue;
1155    // FIXME: For now, do not remat any instruction with register operands.
1156    // Later on, we can loosen the restriction is the register operands have
1157    // not been modified between the def and use. Note, this is different from
1158    // MachineSink because the code is no longer in two-address form (at least
1159    // partially).
1160    if (MO.isUse())
1161      return false;
1162    else if (!MO.isDead() && MO.getReg() != DstReg)
1163      return false;
1164  }
1165  return true;
1166}
1167
1168/// hasVolatileMemoryRef - Return true if this instruction may have a
1169/// volatile memory reference, or if the information describing the
1170/// memory reference is not available. Return false if it is known to
1171/// have no volatile memory references.
1172bool MachineInstr::hasVolatileMemoryRef() const {
1173  // An instruction known never to access memory won't have a volatile access.
1174  if (!TID->mayStore() &&
1175      !TID->mayLoad() &&
1176      !TID->isCall() &&
1177      !hasUnmodeledSideEffects())
1178    return false;
1179
1180  // Otherwise, if the instruction has no memory reference information,
1181  // conservatively assume it wasn't preserved.
1182  if (memoperands_empty())
1183    return true;
1184
1185  // Check the memory reference information for volatile references.
1186  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1187    if ((*I)->isVolatile())
1188      return true;
1189
1190  return false;
1191}
1192
1193/// isInvariantLoad - Return true if this instruction is loading from a
1194/// location whose value is invariant across the function.  For example,
1195/// loading a value from the constant pool or from the argument area
1196/// of a function if it does not change.  This should only return true of
1197/// *all* loads the instruction does are invariant (if it does multiple loads).
1198bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1199  // If the instruction doesn't load at all, it isn't an invariant load.
1200  if (!TID->mayLoad())
1201    return false;
1202
1203  // If the instruction has lost its memoperands, conservatively assume that
1204  // it may not be an invariant load.
1205  if (memoperands_empty())
1206    return false;
1207
1208  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1209
1210  for (mmo_iterator I = memoperands_begin(),
1211       E = memoperands_end(); I != E; ++I) {
1212    if ((*I)->isVolatile()) return false;
1213    if ((*I)->isStore()) return false;
1214
1215    if (const Value *V = (*I)->getValue()) {
1216      // A load from a constant PseudoSourceValue is invariant.
1217      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1218        if (PSV->isConstant(MFI))
1219          continue;
1220      // If we have an AliasAnalysis, ask it whether the memory is constant.
1221      if (AA && AA->pointsToConstantMemory(
1222                      AliasAnalysis::Location(V, (*I)->getSize(),
1223                                              (*I)->getTBAAInfo())))
1224        continue;
1225    }
1226
1227    // Otherwise assume conservatively.
1228    return false;
1229  }
1230
1231  // Everything checks out.
1232  return true;
1233}
1234
1235/// isConstantValuePHI - If the specified instruction is a PHI that always
1236/// merges together the same virtual register, return the register, otherwise
1237/// return 0.
1238unsigned MachineInstr::isConstantValuePHI() const {
1239  if (!isPHI())
1240    return 0;
1241  assert(getNumOperands() >= 3 &&
1242         "It's illegal to have a PHI without source operands");
1243
1244  unsigned Reg = getOperand(1).getReg();
1245  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1246    if (getOperand(i).getReg() != Reg)
1247      return 0;
1248  return Reg;
1249}
1250
1251bool MachineInstr::hasUnmodeledSideEffects() const {
1252  if (getDesc().hasUnmodeledSideEffects())
1253    return true;
1254  if (isInlineAsm()) {
1255    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1256    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1257      return true;
1258  }
1259
1260  return false;
1261}
1262
1263/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1264///
1265bool MachineInstr::allDefsAreDead() const {
1266  for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
1267    const MachineOperand &MO = getOperand(i);
1268    if (!MO.isReg() || MO.isUse())
1269      continue;
1270    if (!MO.isDead())
1271      return false;
1272  }
1273  return true;
1274}
1275
1276/// copyImplicitOps - Copy implicit register operands from specified
1277/// instruction to this instruction.
1278void MachineInstr::copyImplicitOps(const MachineInstr *MI) {
1279  for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1280       i != e; ++i) {
1281    const MachineOperand &MO = MI->getOperand(i);
1282    if (MO.isReg() && MO.isImplicit())
1283      addOperand(MO);
1284  }
1285}
1286
1287void MachineInstr::dump() const {
1288  dbgs() << "  " << *this;
1289}
1290
1291static void printDebugLoc(DebugLoc DL, const MachineFunction *MF,
1292                         raw_ostream &CommentOS) {
1293  const LLVMContext &Ctx = MF->getFunction()->getContext();
1294  if (!DL.isUnknown()) {          // Print source line info.
1295    DIScope Scope(DL.getScope(Ctx));
1296    // Omit the directory, because it's likely to be long and uninteresting.
1297    if (Scope.Verify())
1298      CommentOS << Scope.getFilename();
1299    else
1300      CommentOS << "<unknown>";
1301    CommentOS << ':' << DL.getLine();
1302    if (DL.getCol() != 0)
1303      CommentOS << ':' << DL.getCol();
1304    DebugLoc InlinedAtDL = DebugLoc::getFromDILocation(DL.getInlinedAt(Ctx));
1305    if (!InlinedAtDL.isUnknown()) {
1306      CommentOS << " @[ ";
1307      printDebugLoc(InlinedAtDL, MF, CommentOS);
1308      CommentOS << " ]";
1309    }
1310  }
1311}
1312
1313void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1314  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1315  const MachineFunction *MF = 0;
1316  const MachineRegisterInfo *MRI = 0;
1317  if (const MachineBasicBlock *MBB = getParent()) {
1318    MF = MBB->getParent();
1319    if (!TM && MF)
1320      TM = &MF->getTarget();
1321    if (MF)
1322      MRI = &MF->getRegInfo();
1323  }
1324
1325  // Save a list of virtual registers.
1326  SmallVector<unsigned, 8> VirtRegs;
1327
1328  // Print explicitly defined operands on the left of an assignment syntax.
1329  unsigned StartOp = 0, e = getNumOperands();
1330  for (; StartOp < e && getOperand(StartOp).isReg() &&
1331         getOperand(StartOp).isDef() &&
1332         !getOperand(StartOp).isImplicit();
1333       ++StartOp) {
1334    if (StartOp != 0) OS << ", ";
1335    getOperand(StartOp).print(OS, TM);
1336    unsigned Reg = getOperand(StartOp).getReg();
1337    if (TargetRegisterInfo::isVirtualRegister(Reg))
1338      VirtRegs.push_back(Reg);
1339  }
1340
1341  if (StartOp != 0)
1342    OS << " = ";
1343
1344  // Print the opcode name.
1345  OS << getDesc().getName();
1346
1347  // Print the rest of the operands.
1348  bool OmittedAnyCallClobbers = false;
1349  bool FirstOp = true;
1350
1351  if (isInlineAsm()) {
1352    // Print asm string.
1353    OS << " ";
1354    getOperand(InlineAsm::MIOp_AsmString).print(OS, TM);
1355
1356    // Print HasSideEffects, IsAlignStack
1357    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1358    if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1359      OS << " [sideeffect]";
1360    if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1361      OS << " [alignstack]";
1362
1363    StartOp = InlineAsm::MIOp_FirstOperand;
1364    FirstOp = false;
1365  }
1366
1367
1368  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1369    const MachineOperand &MO = getOperand(i);
1370
1371    if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1372      VirtRegs.push_back(MO.getReg());
1373
1374    // Omit call-clobbered registers which aren't used anywhere. This makes
1375    // call instructions much less noisy on targets where calls clobber lots
1376    // of registers. Don't rely on MO.isDead() because we may be called before
1377    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1378    if (MF && getDesc().isCall() &&
1379        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1380      unsigned Reg = MO.getReg();
1381      if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1382        const MachineRegisterInfo &MRI = MF->getRegInfo();
1383        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1384          bool HasAliasLive = false;
1385          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1386               unsigned AliasReg = *Alias; ++Alias)
1387            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1388              HasAliasLive = true;
1389              break;
1390            }
1391          if (!HasAliasLive) {
1392            OmittedAnyCallClobbers = true;
1393            continue;
1394          }
1395        }
1396      }
1397    }
1398
1399    if (FirstOp) FirstOp = false; else OS << ",";
1400    OS << " ";
1401    if (i < getDesc().NumOperands) {
1402      const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1403      if (TOI.isPredicate())
1404        OS << "pred:";
1405      if (TOI.isOptionalDef())
1406        OS << "opt:";
1407    }
1408    if (isDebugValue() && MO.isMetadata()) {
1409      // Pretty print DBG_VALUE instructions.
1410      const MDNode *MD = MO.getMetadata();
1411      if (const MDString *MDS = dyn_cast<MDString>(MD->getOperand(2)))
1412        OS << "!\"" << MDS->getString() << '\"';
1413      else
1414        MO.print(OS, TM);
1415    } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1416      OS << TM->getRegisterInfo()->getSubRegIndexName(MO.getImm());
1417    } else
1418      MO.print(OS, TM);
1419  }
1420
1421  // Briefly indicate whether any call clobbers were omitted.
1422  if (OmittedAnyCallClobbers) {
1423    if (!FirstOp) OS << ",";
1424    OS << " ...";
1425  }
1426
1427  bool HaveSemi = false;
1428  if (Flags) {
1429    if (!HaveSemi) OS << ";"; HaveSemi = true;
1430    OS << " flags: ";
1431
1432    if (Flags & FrameSetup)
1433      OS << "FrameSetup";
1434  }
1435
1436  if (!memoperands_empty()) {
1437    if (!HaveSemi) OS << ";"; HaveSemi = true;
1438
1439    OS << " mem:";
1440    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1441         i != e; ++i) {
1442      OS << **i;
1443      if (llvm::next(i) != e)
1444        OS << " ";
1445    }
1446  }
1447
1448  // Print the regclass of any virtual registers encountered.
1449  if (MRI && !VirtRegs.empty()) {
1450    if (!HaveSemi) OS << ";"; HaveSemi = true;
1451    for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1452      const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1453      OS << " " << RC->getName() << ':' << PrintReg(VirtRegs[i]);
1454      for (unsigned j = i+1; j != VirtRegs.size();) {
1455        if (MRI->getRegClass(VirtRegs[j]) != RC) {
1456          ++j;
1457          continue;
1458        }
1459        if (VirtRegs[i] != VirtRegs[j])
1460          OS << "," << PrintReg(VirtRegs[j]);
1461        VirtRegs.erase(VirtRegs.begin()+j);
1462      }
1463    }
1464  }
1465
1466  // Print debug location information.
1467  if (!debugLoc.isUnknown() && MF) {
1468    if (!HaveSemi) OS << ";"; HaveSemi = true;
1469    OS << " dbg:";
1470    printDebugLoc(debugLoc, MF, OS);
1471  }
1472
1473  OS << '\n';
1474}
1475
1476bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1477                                     const TargetRegisterInfo *RegInfo,
1478                                     bool AddIfNotFound) {
1479  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1480  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1481  bool Found = false;
1482  SmallVector<unsigned,4> DeadOps;
1483  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1484    MachineOperand &MO = getOperand(i);
1485    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1486      continue;
1487    unsigned Reg = MO.getReg();
1488    if (!Reg)
1489      continue;
1490
1491    if (Reg == IncomingReg) {
1492      if (!Found) {
1493        if (MO.isKill())
1494          // The register is already marked kill.
1495          return true;
1496        if (isPhysReg && isRegTiedToDefOperand(i))
1497          // Two-address uses of physregs must not be marked kill.
1498          return true;
1499        MO.setIsKill();
1500        Found = true;
1501      }
1502    } else if (hasAliases && MO.isKill() &&
1503               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1504      // A super-register kill already exists.
1505      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1506        return true;
1507      if (RegInfo->isSubRegister(IncomingReg, Reg))
1508        DeadOps.push_back(i);
1509    }
1510  }
1511
1512  // Trim unneeded kill operands.
1513  while (!DeadOps.empty()) {
1514    unsigned OpIdx = DeadOps.back();
1515    if (getOperand(OpIdx).isImplicit())
1516      RemoveOperand(OpIdx);
1517    else
1518      getOperand(OpIdx).setIsKill(false);
1519    DeadOps.pop_back();
1520  }
1521
1522  // If not found, this means an alias of one of the operands is killed. Add a
1523  // new implicit operand if required.
1524  if (!Found && AddIfNotFound) {
1525    addOperand(MachineOperand::CreateReg(IncomingReg,
1526                                         false /*IsDef*/,
1527                                         true  /*IsImp*/,
1528                                         true  /*IsKill*/));
1529    return true;
1530  }
1531  return Found;
1532}
1533
1534bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1535                                   const TargetRegisterInfo *RegInfo,
1536                                   bool AddIfNotFound) {
1537  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1538  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1539  bool Found = false;
1540  SmallVector<unsigned,4> DeadOps;
1541  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1542    MachineOperand &MO = getOperand(i);
1543    if (!MO.isReg() || !MO.isDef())
1544      continue;
1545    unsigned Reg = MO.getReg();
1546    if (!Reg)
1547      continue;
1548
1549    if (Reg == IncomingReg) {
1550      MO.setIsDead();
1551      Found = true;
1552    } else if (hasAliases && MO.isDead() &&
1553               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1554      // There exists a super-register that's marked dead.
1555      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1556        return true;
1557      if (RegInfo->getSubRegisters(IncomingReg) &&
1558          RegInfo->getSuperRegisters(Reg) &&
1559          RegInfo->isSubRegister(IncomingReg, Reg))
1560        DeadOps.push_back(i);
1561    }
1562  }
1563
1564  // Trim unneeded dead operands.
1565  while (!DeadOps.empty()) {
1566    unsigned OpIdx = DeadOps.back();
1567    if (getOperand(OpIdx).isImplicit())
1568      RemoveOperand(OpIdx);
1569    else
1570      getOperand(OpIdx).setIsDead(false);
1571    DeadOps.pop_back();
1572  }
1573
1574  // If not found, this means an alias of one of the operands is dead. Add a
1575  // new implicit operand if required.
1576  if (Found || !AddIfNotFound)
1577    return Found;
1578
1579  addOperand(MachineOperand::CreateReg(IncomingReg,
1580                                       true  /*IsDef*/,
1581                                       true  /*IsImp*/,
1582                                       false /*IsKill*/,
1583                                       true  /*IsDead*/));
1584  return true;
1585}
1586
1587void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1588                                      const TargetRegisterInfo *RegInfo) {
1589  if (TargetRegisterInfo::isPhysicalRegister(IncomingReg)) {
1590    MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1591    if (MO)
1592      return;
1593  } else {
1594    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1595      const MachineOperand &MO = getOperand(i);
1596      if (MO.isReg() && MO.getReg() == IncomingReg && MO.isDef() &&
1597          MO.getSubReg() == 0)
1598        return;
1599    }
1600  }
1601  addOperand(MachineOperand::CreateReg(IncomingReg,
1602                                       true  /*IsDef*/,
1603                                       true  /*IsImp*/));
1604}
1605
1606void MachineInstr::setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
1607                                         const TargetRegisterInfo &TRI) {
1608  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1609    MachineOperand &MO = getOperand(i);
1610    if (!MO.isReg() || !MO.isDef()) continue;
1611    unsigned Reg = MO.getReg();
1612    if (Reg == 0) continue;
1613    bool Dead = true;
1614    for (SmallVectorImpl<unsigned>::const_iterator I = UsedRegs.begin(),
1615         E = UsedRegs.end(); I != E; ++I)
1616      if (TRI.regsOverlap(*I, Reg)) {
1617        Dead = false;
1618        break;
1619      }
1620    // If there are no uses, including partial uses, the def is dead.
1621    if (Dead) MO.setIsDead();
1622  }
1623}
1624
1625unsigned
1626MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1627  unsigned Hash = MI->getOpcode() * 37;
1628  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1629    const MachineOperand &MO = MI->getOperand(i);
1630    uint64_t Key = (uint64_t)MO.getType() << 32;
1631    switch (MO.getType()) {
1632    default: break;
1633    case MachineOperand::MO_Register:
1634      if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1635        continue;  // Skip virtual register defs.
1636      Key |= MO.getReg();
1637      break;
1638    case MachineOperand::MO_Immediate:
1639      Key |= MO.getImm();
1640      break;
1641    case MachineOperand::MO_FrameIndex:
1642    case MachineOperand::MO_ConstantPoolIndex:
1643    case MachineOperand::MO_JumpTableIndex:
1644      Key |= MO.getIndex();
1645      break;
1646    case MachineOperand::MO_MachineBasicBlock:
1647      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1648      break;
1649    case MachineOperand::MO_GlobalAddress:
1650      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1651      break;
1652    case MachineOperand::MO_BlockAddress:
1653      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1654      break;
1655    case MachineOperand::MO_MCSymbol:
1656      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1657      break;
1658    }
1659    Key += ~(Key << 32);
1660    Key ^= (Key >> 22);
1661    Key += ~(Key << 13);
1662    Key ^= (Key >> 8);
1663    Key += (Key << 3);
1664    Key ^= (Key >> 15);
1665    Key += ~(Key << 27);
1666    Key ^= (Key >> 31);
1667    Hash = (unsigned)Key + Hash * 37;
1668  }
1669  return Hash;
1670}
1671