MachineInstr.cpp revision de4845c163a5847c82d7ce10ed0c320098bce6e0 
1//===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/Constants.h"
16#include "llvm/Function.h"
17#include "llvm/InlineAsm.h"
18#include "llvm/Metadata.h"
19#include "llvm/Type.h"
20#include "llvm/Value.h"
21#include "llvm/Assembly/Writer.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/CodeGen/PseudoSourceValue.h"
27#include "llvm/MC/MCSymbol.h"
28#include "llvm/Target/TargetMachine.h"
29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetInstrDesc.h"
31#include "llvm/Target/TargetRegisterInfo.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/DebugInfo.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/LeakDetector.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/ADT/FoldingSet.h"
40using namespace llvm;
41
42//===----------------------------------------------------------------------===//
43// MachineOperand Implementation
44//===----------------------------------------------------------------------===//
45
46/// AddRegOperandToRegInfo - Add this register operand to the specified
47/// MachineRegisterInfo.  If it is null, then the next/prev fields should be
48/// explicitly nulled out.
49void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
50  assert(isReg() && "Can only add reg operand to use lists");
51
52  // If the reginfo pointer is null, just explicitly null out or next/prev
53  // pointers, to ensure they are not garbage.
54  if (RegInfo == 0) {
55    Contents.Reg.Prev = 0;
56    Contents.Reg.Next = 0;
57    return;
58  }
59
60  // Otherwise, add this operand to the head of the registers use/def list.
61  MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
62
63  // For SSA values, we prefer to keep the definition at the start of the list.
64  // we do this by skipping over the definition if it is at the head of the
65  // list.
66  if (*Head && (*Head)->isDef())
67    Head = &(*Head)->Contents.Reg.Next;
68
69  Contents.Reg.Next = *Head;
70  if (Contents.Reg.Next) {
71    assert(getReg() == Contents.Reg.Next->getReg() &&
72           "Different regs on the same list!");
73    Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next;
74  }
75
76  Contents.Reg.Prev = Head;
77  *Head = this;
78}
79
80/// RemoveRegOperandFromRegInfo - Remove this register operand from the
81/// MachineRegisterInfo it is linked with.
82void MachineOperand::RemoveRegOperandFromRegInfo() {
83  assert(isOnRegUseList() && "Reg operand is not on a use list");
84  // Unlink this from the doubly linked list of operands.
85  MachineOperand *NextOp = Contents.Reg.Next;
86  *Contents.Reg.Prev = NextOp;
87  if (NextOp) {
88    assert(NextOp->getReg() == getReg() && "Corrupt reg use/def chain!");
89    NextOp->Contents.Reg.Prev = Contents.Reg.Prev;
90  }
91  Contents.Reg.Prev = 0;
92  Contents.Reg.Next = 0;
93}
94
95void MachineOperand::setReg(unsigned Reg) {
96  if (getReg() == Reg) return; // No change.
97
98  // Otherwise, we have to change the register.  If this operand is embedded
99  // into a machine function, we need to update the old and new register's
100  // use/def lists.
101  if (MachineInstr *MI = getParent())
102    if (MachineBasicBlock *MBB = MI->getParent())
103      if (MachineFunction *MF = MBB->getParent()) {
104        RemoveRegOperandFromRegInfo();
105        Contents.Reg.RegNo = Reg;
106        AddRegOperandToRegInfo(&MF->getRegInfo());
107        return;
108      }
109
110  // Otherwise, just change the register, no problem.  :)
111  Contents.Reg.RegNo = Reg;
112}
113
114/// ChangeToImmediate - Replace this operand with a new immediate operand of
115/// the specified value.  If an operand is known to be an immediate already,
116/// the setImm method should be used.
117void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
118  // If this operand is currently a register operand, and if this is in a
119  // function, deregister the operand from the register's use/def list.
120  if (isReg() && getParent() && getParent()->getParent() &&
121      getParent()->getParent()->getParent())
122    RemoveRegOperandFromRegInfo();
123
124  OpKind = MO_Immediate;
125  Contents.ImmVal = ImmVal;
126}
127
128/// ChangeToRegister - Replace this operand with a new register operand of
129/// the specified value.  If an operand is known to be an register already,
130/// the setReg method should be used.
131void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
132                                      bool isKill, bool isDead, bool isUndef,
133                                      bool isDebug) {
134  // If this operand is already a register operand, use setReg to update the
135  // register's use/def lists.
136  if (isReg()) {
137    assert(!isEarlyClobber());
138    setReg(Reg);
139  } else {
140    // Otherwise, change this to a register and set the reg#.
141    OpKind = MO_Register;
142    Contents.Reg.RegNo = Reg;
143
144    // If this operand is embedded in a function, add the operand to the
145    // register's use/def list.
146    if (MachineInstr *MI = getParent())
147      if (MachineBasicBlock *MBB = MI->getParent())
148        if (MachineFunction *MF = MBB->getParent())
149          AddRegOperandToRegInfo(&MF->getRegInfo());
150  }
151
152  IsDef = isDef;
153  IsImp = isImp;
154  IsKill = isKill;
155  IsDead = isDead;
156  IsUndef = isUndef;
157  IsEarlyClobber = false;
158  IsDebug = isDebug;
159  SubReg = 0;
160}
161
162/// isIdenticalTo - Return true if this operand is identical to the specified
163/// operand.
164bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
165  if (getType() != Other.getType() ||
166      getTargetFlags() != Other.getTargetFlags())
167    return false;
168
169  switch (getType()) {
170  default: llvm_unreachable("Unrecognized operand type");
171  case MachineOperand::MO_Register:
172    return getReg() == Other.getReg() && isDef() == Other.isDef() &&
173           getSubReg() == Other.getSubReg();
174  case MachineOperand::MO_Immediate:
175    return getImm() == Other.getImm();
176  case MachineOperand::MO_FPImmediate:
177    return getFPImm() == Other.getFPImm();
178  case MachineOperand::MO_MachineBasicBlock:
179    return getMBB() == Other.getMBB();
180  case MachineOperand::MO_FrameIndex:
181    return getIndex() == Other.getIndex();
182  case MachineOperand::MO_ConstantPoolIndex:
183    return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
184  case MachineOperand::MO_JumpTableIndex:
185    return getIndex() == Other.getIndex();
186  case MachineOperand::MO_GlobalAddress:
187    return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
188  case MachineOperand::MO_ExternalSymbol:
189    return !strcmp(getSymbolName(), Other.getSymbolName()) &&
190           getOffset() == Other.getOffset();
191  case MachineOperand::MO_BlockAddress:
192    return getBlockAddress() == Other.getBlockAddress();
193  case MachineOperand::MO_MCSymbol:
194    return getMCSymbol() == Other.getMCSymbol();
195  }
196}
197
198/// print - Print the specified machine operand.
199///
200void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
201  // If the instruction is embedded into a basic block, we can find the
202  // target info for the instruction.
203  if (!TM)
204    if (const MachineInstr *MI = getParent())
205      if (const MachineBasicBlock *MBB = MI->getParent())
206        if (const MachineFunction *MF = MBB->getParent())
207          TM = &MF->getTarget();
208
209  switch (getType()) {
210  case MachineOperand::MO_Register:
211    if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) {
212      OS << "%reg" << getReg();
213    } else {
214      if (TM)
215        OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
216      else
217        OS << "%physreg" << getReg();
218    }
219
220    if (getSubReg() != 0)
221      OS << ':' << getSubReg();
222
223    if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
224        isEarlyClobber()) {
225      OS << '<';
226      bool NeedComma = false;
227      if (isDef()) {
228        if (NeedComma) OS << ',';
229        if (isEarlyClobber())
230          OS << "earlyclobber,";
231        if (isImplicit())
232          OS << "imp-";
233        OS << "def";
234        NeedComma = true;
235      } else if (isImplicit()) {
236          OS << "imp-use";
237          NeedComma = true;
238      }
239
240      if (isKill() || isDead() || isUndef()) {
241        if (NeedComma) OS << ',';
242        if (isKill())  OS << "kill";
243        if (isDead())  OS << "dead";
244        if (isUndef()) {
245          if (isKill() || isDead())
246            OS << ',';
247          OS << "undef";
248        }
249      }
250      OS << '>';
251    }
252    break;
253  case MachineOperand::MO_Immediate:
254    OS << getImm();
255    break;
256  case MachineOperand::MO_FPImmediate:
257    if (getFPImm()->getType()->isFloatTy())
258      OS << getFPImm()->getValueAPF().convertToFloat();
259    else
260      OS << getFPImm()->getValueAPF().convertToDouble();
261    break;
262  case MachineOperand::MO_MachineBasicBlock:
263    OS << "<BB#" << getMBB()->getNumber() << ">";
264    break;
265  case MachineOperand::MO_FrameIndex:
266    OS << "<fi#" << getIndex() << '>';
267    break;
268  case MachineOperand::MO_ConstantPoolIndex:
269    OS << "<cp#" << getIndex();
270    if (getOffset()) OS << "+" << getOffset();
271    OS << '>';
272    break;
273  case MachineOperand::MO_JumpTableIndex:
274    OS << "<jt#" << getIndex() << '>';
275    break;
276  case MachineOperand::MO_GlobalAddress:
277    OS << "<ga:";
278    WriteAsOperand(OS, getGlobal(), /*PrintType=*/false);
279    if (getOffset()) OS << "+" << getOffset();
280    OS << '>';
281    break;
282  case MachineOperand::MO_ExternalSymbol:
283    OS << "<es:" << getSymbolName();
284    if (getOffset()) OS << "+" << getOffset();
285    OS << '>';
286    break;
287  case MachineOperand::MO_BlockAddress:
288    OS << '<';
289    WriteAsOperand(OS, getBlockAddress(), /*PrintType=*/false);
290    OS << '>';
291    break;
292  case MachineOperand::MO_Metadata:
293    OS << '<';
294    WriteAsOperand(OS, getMetadata(), /*PrintType=*/false);
295    OS << '>';
296    break;
297  case MachineOperand::MO_MCSymbol:
298    OS << "<MCSym=" << *getMCSymbol() << '>';
299    break;
300  default:
301    llvm_unreachable("Unrecognized operand type");
302  }
303
304  if (unsigned TF = getTargetFlags())
305    OS << "[TF=" << TF << ']';
306}
307
308//===----------------------------------------------------------------------===//
309// MachineMemOperand Implementation
310//===----------------------------------------------------------------------===//
311
312MachineMemOperand::MachineMemOperand(const Value *v, unsigned int f,
313                                     int64_t o, uint64_t s, unsigned int a)
314  : Offset(o), Size(s), V(v),
315    Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)) {
316  assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
317  assert((isLoad() || isStore()) && "Not a load/store!");
318}
319
320/// Profile - Gather unique data for the object.
321///
322void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
323  ID.AddInteger(Offset);
324  ID.AddInteger(Size);
325  ID.AddPointer(V);
326  ID.AddInteger(Flags);
327}
328
329void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
330  // The Value and Offset may differ due to CSE. But the flags and size
331  // should be the same.
332  assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
333  assert(MMO->getSize() == getSize() && "Size mismatch!");
334
335  if (MMO->getBaseAlignment() >= getBaseAlignment()) {
336    // Update the alignment value.
337    Flags = (Flags & ((1 << MOMaxBits) - 1)) |
338      ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
339    // Also update the base and offset, because the new alignment may
340    // not be applicable with the old ones.
341    V = MMO->getValue();
342    Offset = MMO->getOffset();
343  }
344}
345
346/// getAlignment - Return the minimum known alignment in bytes of the
347/// actual memory reference.
348uint64_t MachineMemOperand::getAlignment() const {
349  return MinAlign(getBaseAlignment(), getOffset());
350}
351
352raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineMemOperand &MMO) {
353  assert((MMO.isLoad() || MMO.isStore()) &&
354         "SV has to be a load, store or both.");
355
356  if (MMO.isVolatile())
357    OS << "Volatile ";
358
359  if (MMO.isLoad())
360    OS << "LD";
361  if (MMO.isStore())
362    OS << "ST";
363  OS << MMO.getSize();
364
365  // Print the address information.
366  OS << "[";
367  if (!MMO.getValue())
368    OS << "<unknown>";
369  else
370    WriteAsOperand(OS, MMO.getValue(), /*PrintType=*/false);
371
372  // If the alignment of the memory reference itself differs from the alignment
373  // of the base pointer, print the base alignment explicitly, next to the base
374  // pointer.
375  if (MMO.getBaseAlignment() != MMO.getAlignment())
376    OS << "(align=" << MMO.getBaseAlignment() << ")";
377
378  if (MMO.getOffset() != 0)
379    OS << "+" << MMO.getOffset();
380  OS << "]";
381
382  // Print the alignment of the reference.
383  if (MMO.getBaseAlignment() != MMO.getAlignment() ||
384      MMO.getBaseAlignment() != MMO.getSize())
385    OS << "(align=" << MMO.getAlignment() << ")";
386
387  return OS;
388}
389
390//===----------------------------------------------------------------------===//
391// MachineInstr Implementation
392//===----------------------------------------------------------------------===//
393
394/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
395/// TID NULL and no operands.
396MachineInstr::MachineInstr()
397  : TID(0), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
398    Parent(0), debugLoc(DebugLoc::getUnknownLoc()) {
399  // Make sure that we get added to a machine basicblock
400  LeakDetector::addGarbageObject(this);
401}
402
403void MachineInstr::addImplicitDefUseOperands() {
404  if (TID->ImplicitDefs)
405    for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
406      addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
407  if (TID->ImplicitUses)
408    for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
409      addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
410}
411
412/// MachineInstr ctor - This constructor create a MachineInstr and add the
413/// implicit operands. It reserves space for number of operands specified by
414/// TargetInstrDesc or the numOperands if it is not zero. (for
415/// instructions with variable number of operands).
416MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
417  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
418    MemRefs(0), MemRefsEnd(0), Parent(0),
419    debugLoc(DebugLoc::getUnknownLoc()) {
420  if (!NoImp && TID->getImplicitDefs())
421    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
422      NumImplicitOps++;
423  if (!NoImp && TID->getImplicitUses())
424    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
425      NumImplicitOps++;
426  Operands.reserve(NumImplicitOps + TID->getNumOperands());
427  if (!NoImp)
428    addImplicitDefUseOperands();
429  // Make sure that we get added to a machine basicblock
430  LeakDetector::addGarbageObject(this);
431}
432
433/// MachineInstr ctor - As above, but with a DebugLoc.
434MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl,
435                           bool NoImp)
436  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
437    Parent(0), debugLoc(dl) {
438  if (!NoImp && TID->getImplicitDefs())
439    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
440      NumImplicitOps++;
441  if (!NoImp && TID->getImplicitUses())
442    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
443      NumImplicitOps++;
444  Operands.reserve(NumImplicitOps + TID->getNumOperands());
445  if (!NoImp)
446    addImplicitDefUseOperands();
447  // Make sure that we get added to a machine basicblock
448  LeakDetector::addGarbageObject(this);
449}
450
451/// MachineInstr ctor - Work exactly the same as the ctor two above, except
452/// that the MachineInstr is created and added to the end of the specified
453/// basic block.
454///
455MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid)
456  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0),
457    MemRefs(0), MemRefsEnd(0), Parent(0),
458    debugLoc(DebugLoc::getUnknownLoc()) {
459  assert(MBB && "Cannot use inserting ctor with null basic block!");
460  if (TID->ImplicitDefs)
461    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
462      NumImplicitOps++;
463  if (TID->ImplicitUses)
464    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
465      NumImplicitOps++;
466  Operands.reserve(NumImplicitOps + TID->getNumOperands());
467  addImplicitDefUseOperands();
468  // Make sure that we get added to a machine basicblock
469  LeakDetector::addGarbageObject(this);
470  MBB->push_back(this);  // Add instruction to end of basic block!
471}
472
473/// MachineInstr ctor - As above, but with a DebugLoc.
474///
475MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
476                           const TargetInstrDesc &tid)
477  : TID(&tid), NumImplicitOps(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0),
478    Parent(0), debugLoc(dl) {
479  assert(MBB && "Cannot use inserting ctor with null basic block!");
480  if (TID->ImplicitDefs)
481    for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
482      NumImplicitOps++;
483  if (TID->ImplicitUses)
484    for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
485      NumImplicitOps++;
486  Operands.reserve(NumImplicitOps + TID->getNumOperands());
487  addImplicitDefUseOperands();
488  // Make sure that we get added to a machine basicblock
489  LeakDetector::addGarbageObject(this);
490  MBB->push_back(this);  // Add instruction to end of basic block!
491}
492
493/// MachineInstr ctor - Copies MachineInstr arg exactly
494///
495MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
496  : TID(&MI.getDesc()), NumImplicitOps(0), AsmPrinterFlags(0),
497    MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd),
498    Parent(0), debugLoc(MI.getDebugLoc()) {
499  Operands.reserve(MI.getNumOperands());
500
501  // Add operands
502  for (unsigned i = 0; i != MI.getNumOperands(); ++i)
503    addOperand(MI.getOperand(i));
504  NumImplicitOps = MI.NumImplicitOps;
505
506  // Set parent to null.
507  Parent = 0;
508
509  LeakDetector::addGarbageObject(this);
510}
511
512MachineInstr::~MachineInstr() {
513  LeakDetector::removeGarbageObject(this);
514#ifndef NDEBUG
515  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
516    assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
517    assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) &&
518           "Reg operand def/use list corrupted");
519  }
520#endif
521}
522
523/// getRegInfo - If this instruction is embedded into a MachineFunction,
524/// return the MachineRegisterInfo object for the current function, otherwise
525/// return null.
526MachineRegisterInfo *MachineInstr::getRegInfo() {
527  if (MachineBasicBlock *MBB = getParent())
528    return &MBB->getParent()->getRegInfo();
529  return 0;
530}
531
532/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
533/// this instruction from their respective use lists.  This requires that the
534/// operands already be on their use lists.
535void MachineInstr::RemoveRegOperandsFromUseLists() {
536  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
537    if (Operands[i].isReg())
538      Operands[i].RemoveRegOperandFromRegInfo();
539  }
540}
541
542/// AddRegOperandsToUseLists - Add all of the register operands in
543/// this instruction from their respective use lists.  This requires that the
544/// operands not be on their use lists yet.
545void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
546  for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
547    if (Operands[i].isReg())
548      Operands[i].AddRegOperandToRegInfo(&RegInfo);
549  }
550}
551
552
553/// addOperand - Add the specified operand to the instruction.  If it is an
554/// implicit operand, it is added to the end of the operand list.  If it is
555/// an explicit operand it is added at the end of the explicit operand list
556/// (before the first implicit operand).
557void MachineInstr::addOperand(const MachineOperand &Op) {
558  bool isImpReg = Op.isReg() && Op.isImplicit();
559  assert((isImpReg || !OperandsComplete()) &&
560         "Trying to add an operand to a machine instr that is already done!");
561
562  MachineRegisterInfo *RegInfo = getRegInfo();
563
564  // If we are adding the operand to the end of the list, our job is simpler.
565  // This is true most of the time, so this is a reasonable optimization.
566  if (isImpReg || NumImplicitOps == 0) {
567    // We can only do this optimization if we know that the operand list won't
568    // reallocate.
569    if (Operands.empty() || Operands.size()+1 <= Operands.capacity()) {
570      Operands.push_back(Op);
571
572      // Set the parent of the operand.
573      Operands.back().ParentMI = this;
574
575      // If the operand is a register, update the operand's use list.
576      if (Op.isReg()) {
577        Operands.back().AddRegOperandToRegInfo(RegInfo);
578        // If the register operand is flagged as early, mark the operand as such
579        unsigned OpNo = Operands.size() - 1;
580        if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
581          Operands[OpNo].setIsEarlyClobber(true);
582      }
583      return;
584    }
585  }
586
587  // Otherwise, we have to insert a real operand before any implicit ones.
588  unsigned OpNo = Operands.size()-NumImplicitOps;
589
590  // If this instruction isn't embedded into a function, then we don't need to
591  // update any operand lists.
592  if (RegInfo == 0) {
593    // Simple insertion, no reginfo update needed for other register operands.
594    Operands.insert(Operands.begin()+OpNo, Op);
595    Operands[OpNo].ParentMI = this;
596
597    // Do explicitly set the reginfo for this operand though, to ensure the
598    // next/prev fields are properly nulled out.
599    if (Operands[OpNo].isReg()) {
600      Operands[OpNo].AddRegOperandToRegInfo(0);
601      // If the register operand is flagged as early, mark the operand as such
602      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
603        Operands[OpNo].setIsEarlyClobber(true);
604    }
605
606  } else if (Operands.size()+1 <= Operands.capacity()) {
607    // Otherwise, we have to remove register operands from their register use
608    // list, add the operand, then add the register operands back to their use
609    // list.  This also must handle the case when the operand list reallocates
610    // to somewhere else.
611
612    // If insertion of this operand won't cause reallocation of the operand
613    // list, just remove the implicit operands, add the operand, then re-add all
614    // the rest of the operands.
615    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
616      assert(Operands[i].isReg() && "Should only be an implicit reg!");
617      Operands[i].RemoveRegOperandFromRegInfo();
618    }
619
620    // Add the operand.  If it is a register, add it to the reg list.
621    Operands.insert(Operands.begin()+OpNo, Op);
622    Operands[OpNo].ParentMI = this;
623
624    if (Operands[OpNo].isReg()) {
625      Operands[OpNo].AddRegOperandToRegInfo(RegInfo);
626      // If the register operand is flagged as early, mark the operand as such
627      if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
628        Operands[OpNo].setIsEarlyClobber(true);
629    }
630
631    // Re-add all the implicit ops.
632    for (unsigned i = OpNo+1, e = Operands.size(); i != e; ++i) {
633      assert(Operands[i].isReg() && "Should only be an implicit reg!");
634      Operands[i].AddRegOperandToRegInfo(RegInfo);
635    }
636  } else {
637    // Otherwise, we will be reallocating the operand list.  Remove all reg
638    // operands from their list, then readd them after the operand list is
639    // reallocated.
640    RemoveRegOperandsFromUseLists();
641
642    Operands.insert(Operands.begin()+OpNo, Op);
643    Operands[OpNo].ParentMI = this;
644
645    // Re-add all the operands.
646    AddRegOperandsToUseLists(*RegInfo);
647
648      // If the register operand is flagged as early, mark the operand as such
649    if (Operands[OpNo].isReg()
650        && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1)
651      Operands[OpNo].setIsEarlyClobber(true);
652  }
653}
654
655/// RemoveOperand - Erase an operand  from an instruction, leaving it with one
656/// fewer operand than it started with.
657///
658void MachineInstr::RemoveOperand(unsigned OpNo) {
659  assert(OpNo < Operands.size() && "Invalid operand number");
660
661  // Special case removing the last one.
662  if (OpNo == Operands.size()-1) {
663    // If needed, remove from the reg def/use list.
664    if (Operands.back().isReg() && Operands.back().isOnRegUseList())
665      Operands.back().RemoveRegOperandFromRegInfo();
666
667    Operands.pop_back();
668    return;
669  }
670
671  // Otherwise, we are removing an interior operand.  If we have reginfo to
672  // update, remove all operands that will be shifted down from their reg lists,
673  // move everything down, then re-add them.
674  MachineRegisterInfo *RegInfo = getRegInfo();
675  if (RegInfo) {
676    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
677      if (Operands[i].isReg())
678        Operands[i].RemoveRegOperandFromRegInfo();
679    }
680  }
681
682  Operands.erase(Operands.begin()+OpNo);
683
684  if (RegInfo) {
685    for (unsigned i = OpNo, e = Operands.size(); i != e; ++i) {
686      if (Operands[i].isReg())
687        Operands[i].AddRegOperandToRegInfo(RegInfo);
688    }
689  }
690}
691
692/// addMemOperand - Add a MachineMemOperand to the machine instruction.
693/// This function should be used only occasionally. The setMemRefs function
694/// is the primary method for setting up a MachineInstr's MemRefs list.
695void MachineInstr::addMemOperand(MachineFunction &MF,
696                                 MachineMemOperand *MO) {
697  mmo_iterator OldMemRefs = MemRefs;
698  mmo_iterator OldMemRefsEnd = MemRefsEnd;
699
700  size_t NewNum = (MemRefsEnd - MemRefs) + 1;
701  mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
702  mmo_iterator NewMemRefsEnd = NewMemRefs + NewNum;
703
704  std::copy(OldMemRefs, OldMemRefsEnd, NewMemRefs);
705  NewMemRefs[NewNum - 1] = MO;
706
707  MemRefs = NewMemRefs;
708  MemRefsEnd = NewMemRefsEnd;
709}
710
711bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
712                                 MICheckType Check) const {
713  // If opcodes or number of operands are not the same then the two
714  // instructions are obviously not identical.
715  if (Other->getOpcode() != getOpcode() ||
716      Other->getNumOperands() != getNumOperands())
717    return false;
718
719  // Check operands to make sure they match.
720  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
721    const MachineOperand &MO = getOperand(i);
722    const MachineOperand &OMO = Other->getOperand(i);
723    // Clients may or may not want to ignore defs when testing for equality.
724    // For example, machine CSE pass only cares about finding common
725    // subexpressions, so it's safe to ignore virtual register defs.
726    if (Check != CheckDefs && MO.isReg() && MO.isDef()) {
727      if (Check == IgnoreDefs)
728        continue;
729      // Check == IgnoreVRegDefs
730      if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
731          TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
732        if (MO.getReg() != OMO.getReg())
733          return false;
734    } else if (!MO.isIdenticalTo(OMO))
735      return false;
736  }
737  return true;
738}
739
740/// removeFromParent - This method unlinks 'this' from the containing basic
741/// block, and returns it, but does not delete it.
742MachineInstr *MachineInstr::removeFromParent() {
743  assert(getParent() && "Not embedded in a basic block!");
744  getParent()->remove(this);
745  return this;
746}
747
748
749/// eraseFromParent - This method unlinks 'this' from the containing basic
750/// block, and deletes it.
751void MachineInstr::eraseFromParent() {
752  assert(getParent() && "Not embedded in a basic block!");
753  getParent()->erase(this);
754}
755
756
757/// OperandComplete - Return true if it's illegal to add a new operand
758///
759bool MachineInstr::OperandsComplete() const {
760  unsigned short NumOperands = TID->getNumOperands();
761  if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands)
762    return true;  // Broken: we have all the operands of this instruction!
763  return false;
764}
765
766/// getNumExplicitOperands - Returns the number of non-implicit operands.
767///
768unsigned MachineInstr::getNumExplicitOperands() const {
769  unsigned NumOperands = TID->getNumOperands();
770  if (!TID->isVariadic())
771    return NumOperands;
772
773  for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
774    const MachineOperand &MO = getOperand(i);
775    if (!MO.isReg() || !MO.isImplicit())
776      NumOperands++;
777  }
778  return NumOperands;
779}
780
781
782/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
783/// the specific register or -1 if it is not found. It further tightens
784/// the search criteria to a use that kills the register if isKill is true.
785int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
786                                          const TargetRegisterInfo *TRI) const {
787  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
788    const MachineOperand &MO = getOperand(i);
789    if (!MO.isReg() || !MO.isUse())
790      continue;
791    unsigned MOReg = MO.getReg();
792    if (!MOReg)
793      continue;
794    if (MOReg == Reg ||
795        (TRI &&
796         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
797         TargetRegisterInfo::isPhysicalRegister(Reg) &&
798         TRI->isSubRegister(MOReg, Reg)))
799      if (!isKill || MO.isKill())
800        return i;
801  }
802  return -1;
803}
804
805/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
806/// the specified register or -1 if it is not found. If isDead is true, defs
807/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
808/// also checks if there is a def of a super-register.
809int MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead,
810                                          const TargetRegisterInfo *TRI) const {
811  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
812    const MachineOperand &MO = getOperand(i);
813    if (!MO.isReg() || !MO.isDef())
814      continue;
815    unsigned MOReg = MO.getReg();
816    if (MOReg == Reg ||
817        (TRI &&
818         TargetRegisterInfo::isPhysicalRegister(MOReg) &&
819         TargetRegisterInfo::isPhysicalRegister(Reg) &&
820         TRI->isSubRegister(MOReg, Reg)))
821      if (!isDead || MO.isDead())
822        return i;
823  }
824  return -1;
825}
826
827/// findFirstPredOperandIdx() - Find the index of the first operand in the
828/// operand list that is used to represent the predicate. It returns -1 if
829/// none is found.
830int MachineInstr::findFirstPredOperandIdx() const {
831  const TargetInstrDesc &TID = getDesc();
832  if (TID.isPredicable()) {
833    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
834      if (TID.OpInfo[i].isPredicate())
835        return i;
836  }
837
838  return -1;
839}
840
841/// isRegTiedToUseOperand - Given the index of a register def operand,
842/// check if the register def is tied to a source operand, due to either
843/// two-address elimination or inline assembly constraints. Returns the
844/// first tied use operand index by reference is UseOpIdx is not null.
845bool MachineInstr::
846isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx) const {
847  if (isInlineAsm()) {
848    assert(DefOpIdx >= 2);
849    const MachineOperand &MO = getOperand(DefOpIdx);
850    if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
851      return false;
852    // Determine the actual operand index that corresponds to this index.
853    unsigned DefNo = 0;
854    unsigned DefPart = 0;
855    for (unsigned i = 1, e = getNumOperands(); i < e; ) {
856      const MachineOperand &FMO = getOperand(i);
857      // After the normal asm operands there may be additional imp-def regs.
858      if (!FMO.isImm())
859        return false;
860      // Skip over this def.
861      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
862      unsigned PrevDef = i + 1;
863      i = PrevDef + NumOps;
864      if (i > DefOpIdx) {
865        DefPart = DefOpIdx - PrevDef;
866        break;
867      }
868      ++DefNo;
869    }
870    for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
871      const MachineOperand &FMO = getOperand(i);
872      if (!FMO.isImm())
873        continue;
874      if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
875        continue;
876      unsigned Idx;
877      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
878          Idx == DefNo) {
879        if (UseOpIdx)
880          *UseOpIdx = (unsigned)i + 1 + DefPart;
881        return true;
882      }
883    }
884    return false;
885  }
886
887  assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
888  const TargetInstrDesc &TID = getDesc();
889  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
890    const MachineOperand &MO = getOperand(i);
891    if (MO.isReg() && MO.isUse() &&
892        TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) {
893      if (UseOpIdx)
894        *UseOpIdx = (unsigned)i;
895      return true;
896    }
897  }
898  return false;
899}
900
901/// isRegTiedToDefOperand - Return true if the operand of the specified index
902/// is a register use and it is tied to an def operand. It also returns the def
903/// operand index by reference.
904bool MachineInstr::
905isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx) const {
906  if (isInlineAsm()) {
907    const MachineOperand &MO = getOperand(UseOpIdx);
908    if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
909      return false;
910
911    // Find the flag operand corresponding to UseOpIdx
912    unsigned FlagIdx, NumOps=0;
913    for (FlagIdx = 1; FlagIdx < UseOpIdx; FlagIdx += NumOps+1) {
914      const MachineOperand &UFMO = getOperand(FlagIdx);
915      // After the normal asm operands there may be additional imp-def regs.
916      if (!UFMO.isImm())
917        return false;
918      NumOps = InlineAsm::getNumOperandRegisters(UFMO.getImm());
919      assert(NumOps < getNumOperands() && "Invalid inline asm flag");
920      if (UseOpIdx < FlagIdx+NumOps+1)
921        break;
922    }
923    if (FlagIdx >= UseOpIdx)
924      return false;
925    const MachineOperand &UFMO = getOperand(FlagIdx);
926    unsigned DefNo;
927    if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
928      if (!DefOpIdx)
929        return true;
930
931      unsigned DefIdx = 1;
932      // Remember to adjust the index. First operand is asm string, then there
933      // is a flag for each.
934      while (DefNo) {
935        const MachineOperand &FMO = getOperand(DefIdx);
936        assert(FMO.isImm());
937        // Skip over this def.
938        DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
939        --DefNo;
940      }
941      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
942      return true;
943    }
944    return false;
945  }
946
947  const TargetInstrDesc &TID = getDesc();
948  if (UseOpIdx >= TID.getNumOperands())
949    return false;
950  const MachineOperand &MO = getOperand(UseOpIdx);
951  if (!MO.isReg() || !MO.isUse())
952    return false;
953  int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO);
954  if (DefIdx == -1)
955    return false;
956  if (DefOpIdx)
957    *DefOpIdx = (unsigned)DefIdx;
958  return true;
959}
960
961/// copyKillDeadInfo - Copies kill / dead operand properties from MI.
962///
963void MachineInstr::copyKillDeadInfo(const MachineInstr *MI) {
964  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
965    const MachineOperand &MO = MI->getOperand(i);
966    if (!MO.isReg() || (!MO.isKill() && !MO.isDead()))
967      continue;
968    for (unsigned j = 0, ee = getNumOperands(); j != ee; ++j) {
969      MachineOperand &MOp = getOperand(j);
970      if (!MOp.isIdenticalTo(MO))
971        continue;
972      if (MO.isKill())
973        MOp.setIsKill();
974      else
975        MOp.setIsDead();
976      break;
977    }
978  }
979}
980
981/// copyPredicates - Copies predicate operand(s) from MI.
982void MachineInstr::copyPredicates(const MachineInstr *MI) {
983  const TargetInstrDesc &TID = MI->getDesc();
984  if (!TID.isPredicable())
985    return;
986  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
987    if (TID.OpInfo[i].isPredicate()) {
988      // Predicated operands must be last operands.
989      addOperand(MI->getOperand(i));
990    }
991  }
992}
993
994/// isSafeToMove - Return true if it is safe to move this instruction. If
995/// SawStore is set to true, it means that there is a store (or call) between
996/// the instruction's location and its intended destination.
997bool MachineInstr::isSafeToMove(const TargetInstrInfo *TII,
998                                AliasAnalysis *AA,
999                                bool &SawStore) const {
1000  // Ignore stuff that we obviously can't move.
1001  if (TID->mayStore() || TID->isCall()) {
1002    SawStore = true;
1003    return false;
1004  }
1005  if (TID->isTerminator() || TID->hasUnmodeledSideEffects())
1006    return false;
1007
1008  // See if this instruction does a load.  If so, we have to guarantee that the
1009  // loaded value doesn't change between the load and the its intended
1010  // destination. The check for isInvariantLoad gives the targe the chance to
1011  // classify the load as always returning a constant, e.g. a constant pool
1012  // load.
1013  if (TID->mayLoad() && !isInvariantLoad(AA))
1014    // Otherwise, this is a real load.  If there is a store between the load and
1015    // end of block, or if the load is volatile, we can't move it.
1016    return !SawStore && !hasVolatileMemoryRef();
1017
1018  return true;
1019}
1020
1021/// isSafeToReMat - Return true if it's safe to rematerialize the specified
1022/// instruction which defined the specified register instead of copying it.
1023bool MachineInstr::isSafeToReMat(const TargetInstrInfo *TII,
1024                                 AliasAnalysis *AA,
1025                                 unsigned DstReg) const {
1026  bool SawStore = false;
1027  if (!TII->isTriviallyReMaterializable(this, AA) ||
1028      !isSafeToMove(TII, AA, SawStore))
1029    return false;
1030  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1031    const MachineOperand &MO = getOperand(i);
1032    if (!MO.isReg())
1033      continue;
1034    // FIXME: For now, do not remat any instruction with register operands.
1035    // Later on, we can loosen the restriction is the register operands have
1036    // not been modified between the def and use. Note, this is different from
1037    // MachineSink because the code is no longer in two-address form (at least
1038    // partially).
1039    if (MO.isUse())
1040      return false;
1041    else if (!MO.isDead() && MO.getReg() != DstReg)
1042      return false;
1043  }
1044  return true;
1045}
1046
1047/// hasVolatileMemoryRef - Return true if this instruction may have a
1048/// volatile memory reference, or if the information describing the
1049/// memory reference is not available. Return false if it is known to
1050/// have no volatile memory references.
1051bool MachineInstr::hasVolatileMemoryRef() const {
1052  // An instruction known never to access memory won't have a volatile access.
1053  if (!TID->mayStore() &&
1054      !TID->mayLoad() &&
1055      !TID->isCall() &&
1056      !TID->hasUnmodeledSideEffects())
1057    return false;
1058
1059  // Otherwise, if the instruction has no memory reference information,
1060  // conservatively assume it wasn't preserved.
1061  if (memoperands_empty())
1062    return true;
1063
1064  // Check the memory reference information for volatile references.
1065  for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1066    if ((*I)->isVolatile())
1067      return true;
1068
1069  return false;
1070}
1071
1072/// isInvariantLoad - Return true if this instruction is loading from a
1073/// location whose value is invariant across the function.  For example,
1074/// loading a value from the constant pool or from the argument area
1075/// of a function if it does not change.  This should only return true of
1076/// *all* loads the instruction does are invariant (if it does multiple loads).
1077bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1078  // If the instruction doesn't load at all, it isn't an invariant load.
1079  if (!TID->mayLoad())
1080    return false;
1081
1082  // If the instruction has lost its memoperands, conservatively assume that
1083  // it may not be an invariant load.
1084  if (memoperands_empty())
1085    return false;
1086
1087  const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1088
1089  for (mmo_iterator I = memoperands_begin(),
1090       E = memoperands_end(); I != E; ++I) {
1091    if ((*I)->isVolatile()) return false;
1092    if ((*I)->isStore()) return false;
1093
1094    if (const Value *V = (*I)->getValue()) {
1095      // A load from a constant PseudoSourceValue is invariant.
1096      if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
1097        if (PSV->isConstant(MFI))
1098          continue;
1099      // If we have an AliasAnalysis, ask it whether the memory is constant.
1100      if (AA && AA->pointsToConstantMemory(V))
1101        continue;
1102    }
1103
1104    // Otherwise assume conservatively.
1105    return false;
1106  }
1107
1108  // Everything checks out.
1109  return true;
1110}
1111
1112/// isConstantValuePHI - If the specified instruction is a PHI that always
1113/// merges together the same virtual register, return the register, otherwise
1114/// return 0.
1115unsigned MachineInstr::isConstantValuePHI() const {
1116  if (!isPHI())
1117    return 0;
1118  assert(getNumOperands() >= 3 &&
1119         "It's illegal to have a PHI without source operands");
1120
1121  unsigned Reg = getOperand(1).getReg();
1122  for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1123    if (getOperand(i).getReg() != Reg)
1124      return 0;
1125  return Reg;
1126}
1127
1128void MachineInstr::dump() const {
1129  dbgs() << "  " << *this;
1130}
1131
1132void MachineInstr::print(raw_ostream &OS, const TargetMachine *TM) const {
1133  // We can be a bit tidier if we know the TargetMachine and/or MachineFunction.
1134  const MachineFunction *MF = 0;
1135  if (const MachineBasicBlock *MBB = getParent()) {
1136    MF = MBB->getParent();
1137    if (!TM && MF)
1138      TM = &MF->getTarget();
1139  }
1140
1141  // Print explicitly defined operands on the left of an assignment syntax.
1142  unsigned StartOp = 0, e = getNumOperands();
1143  for (; StartOp < e && getOperand(StartOp).isReg() &&
1144         getOperand(StartOp).isDef() &&
1145         !getOperand(StartOp).isImplicit();
1146       ++StartOp) {
1147    if (StartOp != 0) OS << ", ";
1148    getOperand(StartOp).print(OS, TM);
1149  }
1150
1151  if (StartOp != 0)
1152    OS << " = ";
1153
1154  // Print the opcode name.
1155  OS << getDesc().getName();
1156
1157  // Print the rest of the operands.
1158  bool OmittedAnyCallClobbers = false;
1159  bool FirstOp = true;
1160  for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1161    const MachineOperand &MO = getOperand(i);
1162
1163    // Omit call-clobbered registers which aren't used anywhere. This makes
1164    // call instructions much less noisy on targets where calls clobber lots
1165    // of registers. Don't rely on MO.isDead() because we may be called before
1166    // LiveVariables is run, or we may be looking at a non-allocatable reg.
1167    if (MF && getDesc().isCall() &&
1168        MO.isReg() && MO.isImplicit() && MO.isDef()) {
1169      unsigned Reg = MO.getReg();
1170      if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
1171        const MachineRegisterInfo &MRI = MF->getRegInfo();
1172        if (MRI.use_empty(Reg) && !MRI.isLiveOut(Reg)) {
1173          bool HasAliasLive = false;
1174          for (const unsigned *Alias = TM->getRegisterInfo()->getAliasSet(Reg);
1175               unsigned AliasReg = *Alias; ++Alias)
1176            if (!MRI.use_empty(AliasReg) || MRI.isLiveOut(AliasReg)) {
1177              HasAliasLive = true;
1178              break;
1179            }
1180          if (!HasAliasLive) {
1181            OmittedAnyCallClobbers = true;
1182            continue;
1183          }
1184        }
1185      }
1186    }
1187
1188    if (FirstOp) FirstOp = false; else OS << ",";
1189    OS << " ";
1190    if (i < getDesc().NumOperands) {
1191      const TargetOperandInfo &TOI = getDesc().OpInfo[i];
1192      if (TOI.isPredicate())
1193        OS << "pred:";
1194      if (TOI.isOptionalDef())
1195        OS << "opt:";
1196    }
1197    MO.print(OS, TM);
1198  }
1199
1200  // Briefly indicate whether any call clobbers were omitted.
1201  if (OmittedAnyCallClobbers) {
1202    if (!FirstOp) OS << ",";
1203    OS << " ...";
1204  }
1205
1206  bool HaveSemi = false;
1207  if (!memoperands_empty()) {
1208    if (!HaveSemi) OS << ";"; HaveSemi = true;
1209
1210    OS << " mem:";
1211    for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1212         i != e; ++i) {
1213      OS << **i;
1214      if (next(i) != e)
1215        OS << " ";
1216    }
1217  }
1218
1219  if (!debugLoc.isUnknown() && MF) {
1220    if (!HaveSemi) OS << ";";
1221
1222    // TODO: print InlinedAtLoc information
1223
1224    DIScope Scope(debugLoc.getScope(MF->getFunction()->getContext()));
1225    OS << " dbg:";
1226    // Omit the directory, since it's usually long and uninteresting.
1227    if (Scope.Verify())
1228      OS << Scope.getFilename();
1229    else
1230      OS << "<unknown>";
1231    OS << ':' << debugLoc.getLine();
1232    if (debugLoc.getCol() != 0)
1233      OS << ':' << debugLoc.getCol();
1234  }
1235
1236  OS << "\n";
1237}
1238
1239bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1240                                     const TargetRegisterInfo *RegInfo,
1241                                     bool AddIfNotFound) {
1242  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1243  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1244  bool Found = false;
1245  SmallVector<unsigned,4> DeadOps;
1246  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1247    MachineOperand &MO = getOperand(i);
1248    if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1249      continue;
1250    unsigned Reg = MO.getReg();
1251    if (!Reg)
1252      continue;
1253
1254    if (Reg == IncomingReg) {
1255      if (!Found) {
1256        if (MO.isKill())
1257          // The register is already marked kill.
1258          return true;
1259        if (isPhysReg && isRegTiedToDefOperand(i))
1260          // Two-address uses of physregs must not be marked kill.
1261          return true;
1262        MO.setIsKill();
1263        Found = true;
1264      }
1265    } else if (hasAliases && MO.isKill() &&
1266               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1267      // A super-register kill already exists.
1268      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1269        return true;
1270      if (RegInfo->isSubRegister(IncomingReg, Reg))
1271        DeadOps.push_back(i);
1272    }
1273  }
1274
1275  // Trim unneeded kill operands.
1276  while (!DeadOps.empty()) {
1277    unsigned OpIdx = DeadOps.back();
1278    if (getOperand(OpIdx).isImplicit())
1279      RemoveOperand(OpIdx);
1280    else
1281      getOperand(OpIdx).setIsKill(false);
1282    DeadOps.pop_back();
1283  }
1284
1285  // If not found, this means an alias of one of the operands is killed. Add a
1286  // new implicit operand if required.
1287  if (!Found && AddIfNotFound) {
1288    addOperand(MachineOperand::CreateReg(IncomingReg,
1289                                         false /*IsDef*/,
1290                                         true  /*IsImp*/,
1291                                         true  /*IsKill*/));
1292    return true;
1293  }
1294  return Found;
1295}
1296
1297bool MachineInstr::addRegisterDead(unsigned IncomingReg,
1298                                   const TargetRegisterInfo *RegInfo,
1299                                   bool AddIfNotFound) {
1300  bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1301  bool hasAliases = isPhysReg && RegInfo->getAliasSet(IncomingReg);
1302  bool Found = false;
1303  SmallVector<unsigned,4> DeadOps;
1304  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1305    MachineOperand &MO = getOperand(i);
1306    if (!MO.isReg() || !MO.isDef())
1307      continue;
1308    unsigned Reg = MO.getReg();
1309    if (!Reg)
1310      continue;
1311
1312    if (Reg == IncomingReg) {
1313      if (!Found) {
1314        if (MO.isDead())
1315          // The register is already marked dead.
1316          return true;
1317        MO.setIsDead();
1318        Found = true;
1319      }
1320    } else if (hasAliases && MO.isDead() &&
1321               TargetRegisterInfo::isPhysicalRegister(Reg)) {
1322      // There exists a super-register that's marked dead.
1323      if (RegInfo->isSuperRegister(IncomingReg, Reg))
1324        return true;
1325      if (RegInfo->getSubRegisters(IncomingReg) &&
1326          RegInfo->getSuperRegisters(Reg) &&
1327          RegInfo->isSubRegister(IncomingReg, Reg))
1328        DeadOps.push_back(i);
1329    }
1330  }
1331
1332  // Trim unneeded dead operands.
1333  while (!DeadOps.empty()) {
1334    unsigned OpIdx = DeadOps.back();
1335    if (getOperand(OpIdx).isImplicit())
1336      RemoveOperand(OpIdx);
1337    else
1338      getOperand(OpIdx).setIsDead(false);
1339    DeadOps.pop_back();
1340  }
1341
1342  // If not found, this means an alias of one of the operands is dead. Add a
1343  // new implicit operand if required.
1344  if (Found || !AddIfNotFound)
1345    return Found;
1346
1347  addOperand(MachineOperand::CreateReg(IncomingReg,
1348                                       true  /*IsDef*/,
1349                                       true  /*IsImp*/,
1350                                       false /*IsKill*/,
1351                                       true  /*IsDead*/));
1352  return true;
1353}
1354
1355void MachineInstr::addRegisterDefined(unsigned IncomingReg,
1356                                      const TargetRegisterInfo *RegInfo) {
1357  MachineOperand *MO = findRegisterDefOperand(IncomingReg, false, RegInfo);
1358  if (!MO || MO->getSubReg())
1359    addOperand(MachineOperand::CreateReg(IncomingReg,
1360                                         true  /*IsDef*/,
1361                                         true  /*IsImp*/));
1362}
1363
1364unsigned
1365MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1366  unsigned Hash = MI->getOpcode() * 37;
1367  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1368    const MachineOperand &MO = MI->getOperand(i);
1369    uint64_t Key = (uint64_t)MO.getType() << 32;
1370    switch (MO.getType()) {
1371    default: break;
1372    case MachineOperand::MO_Register:
1373      if (MO.isDef() && MO.getReg() &&
1374          TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1375        continue;  // Skip virtual register defs.
1376      Key |= MO.getReg();
1377      break;
1378    case MachineOperand::MO_Immediate:
1379      Key |= MO.getImm();
1380      break;
1381    case MachineOperand::MO_FrameIndex:
1382    case MachineOperand::MO_ConstantPoolIndex:
1383    case MachineOperand::MO_JumpTableIndex:
1384      Key |= MO.getIndex();
1385      break;
1386    case MachineOperand::MO_MachineBasicBlock:
1387      Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
1388      break;
1389    case MachineOperand::MO_GlobalAddress:
1390      Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
1391      break;
1392    case MachineOperand::MO_BlockAddress:
1393      Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
1394      break;
1395    case MachineOperand::MO_MCSymbol:
1396      Key |= DenseMapInfo<void*>::getHashValue(MO.getMCSymbol());
1397      break;
1398    }
1399    Key += ~(Key << 32);
1400    Key ^= (Key >> 22);
1401    Key += ~(Key << 13);
1402    Key ^= (Key >> 8);
1403    Key += (Key << 3);
1404    Key ^= (Key >> 15);
1405    Key += ~(Key << 27);
1406    Key ^= (Key >> 31);
1407    Hash = (unsigned)Key + Hash * 37;
1408  }
1409  return Hash;
1410}
1411